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| Commit | Line | Data |
|---|---|---|
| edabd38e SB |
1 | /* |
| 2 | * arch/arm/mach-dove/include/mach/pm.h | |
| 3 | * | |
| 4 | * This file is licensed under the terms of the GNU General Public | |
| 5 | * License version 2. This program is licensed "as is" without any | |
| 6 | * warranty of any kind, whether express or implied. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __ASM_ARCH_PM_H | |
| 10 | #define __ASM_ARCH_PM_H | |
| 11 | ||
| 12 | #include <asm/errno.h> | |
| 13 | #include <mach/irqs.h> | |
| 14 | ||
| 15 | #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) | |
| 52167471 SH |
16 | #define CLOCK_GATING_BIT_USB0 0 |
| 17 | #define CLOCK_GATING_BIT_USB1 1 | |
| 18 | #define CLOCK_GATING_BIT_GBE 2 | |
| 19 | #define CLOCK_GATING_BIT_SATA 3 | |
| 20 | #define CLOCK_GATING_BIT_PCIE0 4 | |
| 21 | #define CLOCK_GATING_BIT_PCIE1 5 | |
| 22 | #define CLOCK_GATING_BIT_SDIO0 8 | |
| 23 | #define CLOCK_GATING_BIT_SDIO1 9 | |
| 24 | #define CLOCK_GATING_BIT_NAND 10 | |
| 25 | #define CLOCK_GATING_BIT_CAMERA 11 | |
| 26 | #define CLOCK_GATING_BIT_I2S0 12 | |
| 27 | #define CLOCK_GATING_BIT_I2S1 13 | |
| 28 | #define CLOCK_GATING_BIT_CRYPTO 15 | |
| 29 | #define CLOCK_GATING_BIT_AC97 21 | |
| 30 | #define CLOCK_GATING_BIT_PDMA 22 | |
| 31 | #define CLOCK_GATING_BIT_XOR0 23 | |
| 32 | #define CLOCK_GATING_BIT_XOR1 24 | |
| 33 | #define CLOCK_GATING_BIT_GIGA_PHY 30 | |
| 34 | #define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0) | |
| 35 | #define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1) | |
| 36 | #define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE) | |
| 37 | #define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA) | |
| 38 | #define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0) | |
| 39 | #define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1) | |
| 40 | #define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0) | |
| 41 | #define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1) | |
| 42 | #define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND) | |
| 43 | #define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA) | |
| 44 | #define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0) | |
| 45 | #define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1) | |
| 46 | #define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO) | |
| 47 | #define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97) | |
| 48 | #define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA) | |
| 49 | #define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0) | |
| 50 | #define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1) | |
| 51 | #define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) | |
| edabd38e SB |
52 | |
| 53 | #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) | |
| 54 | #define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) | |
| 55 | ||
| 56 | static inline int pmu_to_irq(int pin) | |
| 57 | { | |
| 58 | if (pin < NR_PMU_IRQS) | |
| 59 | return pin + IRQ_DOVE_PMU_START; | |
| 60 | ||
| 61 | return -EINVAL; | |
| 62 | } | |
| 63 | ||
| 64 | static inline int irq_to_pmu(int irq) | |
| 65 | { | |
| d356cf5a | 66 | if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS) |
| edabd38e SB |
67 | return irq - IRQ_DOVE_PMU_START; |
| 68 | ||
| 69 | return -EINVAL; | |
| 70 | } | |
| 71 | ||
| 72 | #endif |