[deliverable/linux.git] / arch / arm / mach-dove / irq.c

/*
 * arch/arm/mach-dove/irq.c
 *
 * Dove IRQ handling.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <plat/irq.h>
#include <asm/mach/irq.h>
#include <mach/pm.h>
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include "common.h"

static void pmu_irq_mask(struct irq_data *d)
{
	int pin = irq_to_pmu(d->irq);
	u32 u;

	u = readl(PMU_INTERRUPT_MASK);
	u &= ~(1 << (pin & 31));
	writel(u, PMU_INTERRUPT_MASK);
}

static void pmu_irq_unmask(struct irq_data *d)
{
	int pin = irq_to_pmu(d->irq);
	u32 u;

	u = readl(PMU_INTERRUPT_MASK);
	u |= 1 << (pin & 31);
	writel(u, PMU_INTERRUPT_MASK);
}

static void pmu_irq_ack(struct irq_data *d)
{
	int pin = irq_to_pmu(d->irq);
	u32 u;

	/*
	 * The PMU mask register is not RW0C: it is RW.  This means that
	 * the bits take whatever value is written to them; if you write
	 * a '1', you will set the interrupt.
	 *
	 * Unfortunately this means there is NO race free way to clear
	 * these interrupts.
	 *
	 * So, let's structure the code so that the window is as small as
	 * possible.
	 */
	u = ~(1 << (pin & 31));
	u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
	writel_relaxed(u, PMU_INTERRUPT_CAUSE);
}

static struct irq_chip pmu_irq_chip = {
	.name		= "pmu_irq",
	.irq_mask	= pmu_irq_mask,
	.irq_unmask	= pmu_irq_unmask,
	.irq_ack	= pmu_irq_ack,
};

static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
{
	unsigned int irq = irq_desc_get_irq(desc);
	unsigned long cause = readl(PMU_INTERRUPT_CAUSE);

	cause &= readl(PMU_INTERRUPT_MASK);
	if (cause == 0) {
		do_bad_IRQ(irq, desc);
		return;
	}

	for (irq = 0; irq < NR_PMU_IRQS; irq++) {
		if (!(cause & (1 << irq)))
			continue;
		irq = pmu_to_irq(irq);
		generic_handle_irq(irq);
	}
}

static int __initdata gpio0_irqs[4] = {
	IRQ_DOVE_GPIO_0_7,
	IRQ_DOVE_GPIO_8_15,
	IRQ_DOVE_GPIO_16_23,
	IRQ_DOVE_GPIO_24_31,
};

static int __initdata gpio1_irqs[4] = {
	IRQ_DOVE_HIGH_GPIO,
	0,
	0,
	0,
};

static int __initdata gpio2_irqs[4] = {
	0,
	0,
	0,
	0,
};

#ifdef CONFIG_MULTI_IRQ_HANDLER
/*
 * Compiling with both non-DT and DT support enabled, will
 * break asm irq handler used by non-DT boards. Therefore,
 * we provide a C-style irq handler even for non-DT boards,
 * if MULTI_IRQ_HANDLER is set.
 */

static void __iomem *dove_irq_base = IRQ_VIRT_BASE;

static asmlinkage void
__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
{
	u32 stat;

	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
	if (stat) {
		unsigned int hwirq = 1 + __fls(stat);
		handle_IRQ(hwirq, regs);
		return;
	}
	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
	if (stat) {
		unsigned int hwirq = 33 + __fls(stat);
		handle_IRQ(hwirq, regs);
		return;
	}
}
#endif

void __init dove_init_irq(void)
{
	int i;

	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);

#ifdef CONFIG_MULTI_IRQ_HANDLER
	set_handle_irq(dove_legacy_handle_irq);
#endif

	/*
	 * Initialize gpiolib for GPIOs 0-71.
	 */
	orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
			IRQ_DOVE_GPIO_START, gpio0_irqs);

	orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
			IRQ_DOVE_GPIO_START + 32, gpio1_irqs);

	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);

	/*
	 * Mask and clear PMU interrupts
	 */
	writel(0, PMU_INTERRUPT_MASK);
	writel(0, PMU_INTERRUPT_CAUSE);

	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
		irq_set_status_flags(i, IRQ_LEVEL);
		irq_clear_status_flags(i, IRQ_NOREQUEST);
	}
	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/irq.c
	3	*
	4	* Dove IRQ handling.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/irq.h>
	14	#include <linux/gpio.h>
	15	#include <linux/io.h>
	16	#include <asm/mach/arch.h>
	17	#include <plat/irq.h>
	18	#include <asm/mach/irq.h>
	19	#include <mach/pm.h>
	20	#include <mach/bridge-regs.h>
ce91574c	21	#include <plat/orion-gpio.h>
edabd38e SB	22	#include "common.h"
edabd38e SB	23
aa456a6e	24	static void pmu_irq_mask(struct irq_data *d)
edabd38e	25	{
aa456a6e	26	int pin = irq_to_pmu(d->irq);
edabd38e SB	27	u32 u;
	28
	29	u = readl(PMU_INTERRUPT_MASK);
	30	u &= ~(1 << (pin & 31));
	31	writel(u, PMU_INTERRUPT_MASK);
	32	}
	33
aa456a6e	34	static void pmu_irq_unmask(struct irq_data *d)
edabd38e	35	{
aa456a6e	36	int pin = irq_to_pmu(d->irq);
edabd38e SB	37	u32 u;
	38
	39	u = readl(PMU_INTERRUPT_MASK);
	40	u \|= 1 << (pin & 31);
	41	writel(u, PMU_INTERRUPT_MASK);
	42	}
	43
aa456a6e	44	static void pmu_irq_ack(struct irq_data *d)
edabd38e	45	{
aa456a6e	46	int pin = irq_to_pmu(d->irq);
edabd38e SB	47	u32 u;
edabd38e SB	48
5d3df935 RKAL	49	/*
	50	* The PMU mask register is not RW0C: it is RW. This means that
	51	* the bits take whatever value is written to them; if you write
	52	* a '1', you will set the interrupt.
	53	*
	54	* Unfortunately this means there is NO race free way to clear
	55	* these interrupts.
	56	*
	57	* So, let's structure the code so that the window is as small as
	58	* possible.
	59	*/
edabd38e	60	u = ~(1 << (pin & 31));
5d3df935 RKAL	61	u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
5d3df935 RKAL	62	writel_relaxed(u, PMU_INTERRUPT_CAUSE);
edabd38e SB	63	}
	64
	65	static struct irq_chip pmu_irq_chip = {
	66	.name = "pmu_irq",
aa456a6e LB	67	.irq_mask = pmu_irq_mask,
	68	.irq_unmask = pmu_irq_unmask,
	69	.irq_ack = pmu_irq_ack,
edabd38e SB	70	};
edabd38e SB	71
1c2d4afa	72	static void pmu_irq_handler(unsigned int __irq, struct irq_desc *desc)
edabd38e	73	{
1c2d4afa	74	unsigned int irq = irq_desc_get_irq(desc);
edabd38e SB	75	unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
	76
	77	cause &= readl(PMU_INTERRUPT_MASK);
	78	if (cause == 0) {
	79	do_bad_IRQ(irq, desc);
	80	return;
	81	}
	82
	83	for (irq = 0; irq < NR_PMU_IRQS; irq++) {
	84	if (!(cause & (1 << irq)))
	85	continue;
	86	irq = pmu_to_irq(irq);
cf0d6b76	87	generic_handle_irq(irq);
edabd38e SB	88	}
	89	}
	90
278b45b0 AL	91	static int __initdata gpio0_irqs[4] = {
	92	IRQ_DOVE_GPIO_0_7,
	93	IRQ_DOVE_GPIO_8_15,
	94	IRQ_DOVE_GPIO_16_23,
	95	IRQ_DOVE_GPIO_24_31,
	96	};
	97
	98	static int __initdata gpio1_irqs[4] = {
	99	IRQ_DOVE_HIGH_GPIO,
	100	0,
	101	0,
	102	0,
	103	};
	104
	105	static int __initdata gpio2_irqs[4] = {
	106	0,
	107	0,
	108	0,
	109	0,
	110	};
	111
deac3d87 TP	112	#ifdef CONFIG_MULTI_IRQ_HANDLER
	113	/*
	114	* Compiling with both non-DT and DT support enabled, will
	115	* break asm irq handler used by non-DT boards. Therefore,
	116	* we provide a C-style irq handler even for non-DT boards,
	117	* if MULTI_IRQ_HANDLER is set.
	118	*/
	119
	120	static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
	121
	122	static asmlinkage void
	123	__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
	124	{
	125	u32 stat;
	126
	127	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
	128	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
	129	if (stat) {
5d6bed2a	130	unsigned int hwirq = 1 + __fls(stat);
deac3d87 TP	131	handle_IRQ(hwirq, regs);
	132	return;
	133	}
	134	stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
	135	stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
	136	if (stat) {
5d6bed2a	137	unsigned int hwirq = 33 + __fls(stat);
deac3d87 TP	138	handle_IRQ(hwirq, regs);
	139	return;
	140	}
	141	}
	142	#endif
	143
edabd38e SB	144	void __init dove_init_irq(void)
	145	{
	146	int i;
	147
5d6bed2a RK	148	orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
5d6bed2a RK	149	orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
edabd38e	150
deac3d87 TP	151	#ifdef CONFIG_MULTI_IRQ_HANDLER
	152	set_handle_irq(dove_legacy_handle_irq);
	153	#endif
	154
edabd38e	155	/*
9eac6d0a	156	* Initialize gpiolib for GPIOs 0-71.
edabd38e	157	*/
c3c5a281	158	orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
278b45b0 AL	159	IRQ_DOVE_GPIO_START, gpio0_irqs);
278b45b0 AL	160
c3c5a281	161	orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
278b45b0 AL	162	IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
278b45b0 AL	163
c3c5a281	164	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
278b45b0	165	IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
edabd38e SB	166
	167	/*
	168	* Mask and clear PMU interrupts
	169	*/
	170	writel(0, PMU_INTERRUPT_MASK);
	171	writel(0, PMU_INTERRUPT_CAUSE);
	172
edabd38e	173	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
f38c02f3	174	irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
cf0d6b76	175	irq_set_status_flags(i, IRQ_LEVEL);
e8d36d5d	176	irq_clear_status_flags(i, IRQ_NOREQUEST);
edabd38e	177	}
6845664a	178	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
edabd38e	179	}