[deliverable/linux.git] / arch / arm / mach-dove / pcie.c

/*
 * arch/arm/mach-dove/pcie.c
 *
 * PCIe functions for Marvell Dove 88AP510 SoC
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
#include <asm/delay.h>
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
#include <plat/addr-map.h>
#include "common.h"

struct pcie_port {
	u8			index;
	u8			root_bus_nr;
	void __iomem		*base;
	spinlock_t		conf_lock;
	char			io_space_name[16];
	char			mem_space_name[16];
	struct resource		res[2];
};

static struct pcie_port pcie_port[2];
static int num_pcie_ports;


static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
{
	struct pcie_port *pp;

	if (nr >= num_pcie_ports)
		return 0;

	pp = &pcie_port[nr];
	pp->root_bus_nr = sys->busnr;

	/*
	 * Generic PCIe unit setup.
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base, &orion_mbus_dram_info);

	/*
	 * IORESOURCE_IO
	 */
	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
		 "PCIe %d I/O", pp->index);
	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
	pp->res[0].name = pp->io_space_name;
	if (pp->index == 0) {
		pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
		pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
	} else {
		pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
		pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
	}
	pp->res[0].flags = IORESOURCE_IO;
	if (request_resource(&ioport_resource, &pp->res[0]))
		panic("Request PCIe IO resource failed\n");
	sys->resource[0] = &pp->res[0];

	/*
	 * IORESOURCE_MEM
	 */
	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
		 "PCIe %d MEM", pp->index);
	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
	pp->res[1].name = pp->mem_space_name;
	if (pp->index == 0) {
		pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
		pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
	} else {
		pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
		pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
	}
	pp->res[1].flags = IORESOURCE_MEM;
	if (request_resource(&iomem_resource, &pp->res[1]))
		panic("Request PCIe Memory resource failed\n");
	sys->resource[1] = &pp->res[1];

	sys->resource[2] = NULL;

	return 1;
}

static struct pcie_port *bus_to_port(int bus)
{
	int i;

	for (i = num_pcie_ports - 1; i >= 0; i--) {
		int rbus = pcie_port[i].root_bus_nr;
		if (rbus != -1 && rbus <= bus)
			break;
	}

	return i >= 0 ? pcie_port + i : NULL;
}

static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
	/*
	 * Don't go out when trying to access nonexisting devices
	 * on the local bus.
	 */
	if (bus == pp->root_bus_nr && dev > 1)
		return 0;

	return 1;
}

static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
{
	struct pcie_port *pp = bus_to_port(bus->number);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
{
	struct pcie_port *pp = bus_to_port(bus->number);
	unsigned long flags;
	int ret;

	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;

	spin_lock_irqsave(&pp->conf_lock, flags);
	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
	spin_unlock_irqrestore(&pp->conf_lock, flags);

	return ret;
}

static struct pci_ops pcie_ops = {
	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
};

static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

static struct pci_bus __init *
dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
{
	struct pci_bus *bus;

	if (nr < num_pcie_ports) {
		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
	} else {
		bus = NULL;
		BUG();
	}

	return bus;
}

static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct pcie_port *pp = bus_to_port(dev->bus->number);

	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
}

static struct hw_pci dove_pci __initdata = {
	.nr_controllers	= 2,
	.swizzle	= pci_std_swizzle,
	.setup		= dove_pcie_setup,
	.scan		= dove_pcie_scan_bus,
	.map_irq	= dove_pcie_map_irq,
};

static void __init add_pcie_port(int index, unsigned long base)
{
	printk(KERN_INFO "Dove PCIe port %d: ", index);

	if (orion_pcie_link_up((void __iomem *)base)) {
		struct pcie_port *pp = &pcie_port[num_pcie_ports++];

		printk(KERN_INFO "link up\n");

		pp->index = index;
		pp->root_bus_nr = -1;
		pp->base = (void __iomem *)base;
		spin_lock_init(&pp->conf_lock);
		memset(pp->res, 0, sizeof(pp->res));
	} else {
		printk(KERN_INFO "link down, ignoring\n");
	}
}

void __init dove_pcie_init(int init_port0, int init_port1)
{
	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;

	if (init_port0)
		add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);

	if (init_port1)
		add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);

	pci_common_init(&dove_pci);
}
Commit	Line	Data
edabd38e SB	1	/*
	2	* arch/arm/mach-dove/pcie.c
	3	*
	4	* PCIe functions for Marvell Dove 88AP510 SoC
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/pci.h>
	13	#include <linux/mbus.h>
cc22b4c1	14	#include <video/vga.h>
edabd38e SB	15	#include <asm/mach/pci.h>
	16	#include <asm/mach/arch.h>
	17	#include <asm/setup.h>
	18	#include <asm/delay.h>
	19	#include <plat/pcie.h>
	20	#include <mach/irqs.h>
	21	#include <mach/bridge-regs.h>
45173d5e	22	#include <plat/addr-map.h>
edabd38e SB	23	#include "common.h"
	24
	25	struct pcie_port {
	26	u8 index;
	27	u8 root_bus_nr;
	28	void __iomem *base;
	29	spinlock_t conf_lock;
	30	char io_space_name[16];
	31	char mem_space_name[16];
	32	struct resource res[2];
	33	};
	34
	35	static struct pcie_port pcie_port[2];
	36	static int num_pcie_ports;
	37
	38
	39	static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
	40	{
	41	struct pcie_port *pp;
	42
	43	if (nr >= num_pcie_ports)
	44	return 0;
	45
	46	pp = &pcie_port[nr];
	47	pp->root_bus_nr = sys->busnr;
	48
	49	/*
	50	* Generic PCIe unit setup.
	51	*/
	52	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
	53
45173d5e	54	orion_pcie_setup(pp->base, &orion_mbus_dram_info);
edabd38e SB	55
	56	/*
	57	* IORESOURCE_IO
	58	*/
	59	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
	60	"PCIe %d I/O", pp->index);
	61	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
	62	pp->res[0].name = pp->io_space_name;
	63	if (pp->index == 0) {
	64	pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
	65	pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
	66	} else {
	67	pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
	68	pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
	69	}
	70	pp->res[0].flags = IORESOURCE_IO;
	71	if (request_resource(&ioport_resource, &pp->res[0]))
	72	panic("Request PCIe IO resource failed\n");
	73	sys->resource[0] = &pp->res[0];
	74
	75	/*
	76	* IORESOURCE_MEM
	77	*/
	78	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
	79	"PCIe %d MEM", pp->index);
	80	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
	81	pp->res[1].name = pp->mem_space_name;
	82	if (pp->index == 0) {
	83	pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
	84	pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
	85	} else {
	86	pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
	87	pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
	88	}
	89	pp->res[1].flags = IORESOURCE_MEM;
	90	if (request_resource(&iomem_resource, &pp->res[1]))
	91	panic("Request PCIe Memory resource failed\n");
	92	sys->resource[1] = &pp->res[1];
	93
	94	sys->resource[2] = NULL;
	95
	96	return 1;
	97	}
	98
	99	static struct pcie_port *bus_to_port(int bus)
	100	{
	101	int i;
	102
	103	for (i = num_pcie_ports - 1; i >= 0; i--) {
	104	int rbus = pcie_port[i].root_bus_nr;
	105	if (rbus != -1 && rbus <= bus)
	106	break;
	107	}
	108
	109	return i >= 0 ? pcie_port + i : NULL;
	110	}
	111
	112	static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
	113	{
	114	/*
	115	* Don't go out when trying to access nonexisting devices
	116	* on the local bus.
	117	*/
	118	if (bus == pp->root_bus_nr && dev > 1)
119	return 0;
120
121	return 1;
122	}
123
124	static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
125	int size, u32 *val)
126	{
127	struct pcie_port *pp = bus_to_port(bus->number);
128	unsigned long flags;
129	int ret;
130
131	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
132	*val = 0xffffffff;
133	return PCIBIOS_DEVICE_NOT_FOUND;
134	}
135
136	spin_lock_irqsave(&pp->conf_lock, flags);
137	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
138	spin_unlock_irqrestore(&pp->conf_lock, flags);
139
140	return ret;
141	}
142
143	static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
144	int where, int size, u32 val)
145	{
146	struct pcie_port *pp = bus_to_port(bus->number);
147	unsigned long flags;
148	int ret;
149
150	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
151	return PCIBIOS_DEVICE_NOT_FOUND;
152
153	spin_lock_irqsave(&pp->conf_lock, flags);
154	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
155	spin_unlock_irqrestore(&pp->conf_lock, flags);
156
157	return ret;
158	}
159
160	static struct pci_ops pcie_ops = {
161	.read = pcie_rd_conf,
162	.write = pcie_wr_conf,
163	};
164
165	static void __devinit rc_pci_fixup(struct pci_dev *dev)
166	{
167	/*
168	* Prevent enumeration of root complex.
169	*/
170	if (dev->bus->parent == NULL && dev->devfn == 0) {
171	int i;
172
173	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
174	dev->resource[i].start = 0;
175	dev->resource[i].end = 0;
176	dev->resource[i].flags = 0;
177	}
178	}
179	}
180	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
181
182	static struct pci_bus __init *
183	dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
184	{
185	struct pci_bus *bus;
186
187	if (nr < num_pcie_ports) {
188	bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
189	} else {
190	bus = NULL;
191	BUG();
192	}
193
194	return bus;
195	}
196
d5341942	197	static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
edabd38e SB	198	{
	199	struct pcie_port *pp = bus_to_port(dev->bus->number);
	200
	201	return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
	202	}
	203
	204	static struct hw_pci dove_pci __initdata = {
	205	.nr_controllers = 2,
	206	.swizzle = pci_std_swizzle,
	207	.setup = dove_pcie_setup,
	208	.scan = dove_pcie_scan_bus,
	209	.map_irq = dove_pcie_map_irq,
	210	};
	211
	212	static void __init add_pcie_port(int index, unsigned long base)
	213	{
	214	printk(KERN_INFO "Dove PCIe port %d: ", index);
	215
	216	if (orion_pcie_link_up((void __iomem *)base)) {
	217	struct pcie_port *pp = &pcie_port[num_pcie_ports++];
	218
	219	printk(KERN_INFO "link up\n");
	220
	221	pp->index = index;
	222	pp->root_bus_nr = -1;
	223	pp->base = (void __iomem *)base;
	224	spin_lock_init(&pp->conf_lock);
	225	memset(pp->res, 0, sizeof(pp->res));
	226	} else {
	227	printk(KERN_INFO "link down, ignoring\n");
	228	}
	229	}
	230
	231	void __init dove_pcie_init(int init_port0, int init_port1)
	232	{
cc22b4c1 RH	233	vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
cc22b4c1 RH	234
edabd38e SB	235	if (init_port0)
	236	add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
	237
	238	if (init_port1)
	239	add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
	240
	241	pci_common_init(&dove_pci);
	242	}