[deliverable/linux.git] / arch / arm / mach-ep93xx / clock.c

/*
 * arch/arm/mach-ep93xx/clock.c
 * Clock control for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>

#include <asm/clkdev.h>
#include <asm/div64.h>


struct clk {
	struct clk	*parent;
	unsigned long	rate;
	int		users;
	int		sw_locked;
	void __iomem	*enable_reg;
	u32		enable_mask;

	unsigned long	(*get_rate)(struct clk *clk);
	int		(*set_rate)(struct clk *clk, unsigned long rate);
};


static unsigned long get_uart_rate(struct clk *clk);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
static int set_div_rate(struct clk *clk, unsigned long rate);


static struct clk clk_xtali = {
	.rate		= EP93XX_EXT_CLK_RATE,
};
static struct clk clk_uart1 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U1EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart2 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U2EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_uart3 = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_DEVCFG,
	.enable_mask	= EP93XX_SYSCON_DEVCFG_U3EN,
	.get_rate	= get_uart_rate,
};
static struct clk clk_pll1 = {
	.parent		= &clk_xtali,
};
static struct clk clk_f = {
	.parent		= &clk_pll1,
};
static struct clk clk_h = {
	.parent		= &clk_pll1,
};
static struct clk clk_p = {
	.parent		= &clk_pll1,
};
static struct clk clk_pll2 = {
	.parent		= &clk_xtali,
};
static struct clk clk_usb_host = {
	.parent		= &clk_pll2,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_USH_EN,
};
static struct clk clk_keypad = {
	.parent		= &clk_xtali,
	.sw_locked	= 1,
	.enable_reg	= EP93XX_SYSCON_KEYTCHCLKDIV,
	.enable_mask	= EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	.set_rate	= set_keytchclk_rate,
};
static struct clk clk_pwm = {
	.parent		= &clk_xtali,
	.rate		= EP93XX_EXT_CLK_RATE,
};

static struct clk clk_video = {
	.sw_locked	= 1,
	.enable_reg     = EP93XX_SYSCON_VIDCLKDIV,
	.enable_mask    = EP93XX_SYSCON_CLKDIV_ENABLE,
	.set_rate	= set_div_rate,
};

/* DMA Clocks */
static struct clk clk_m2p0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P0,
};
static struct clk clk_m2p1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P1,
};
static struct clk clk_m2p2 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P2,
};
static struct clk clk_m2p3 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P3,
};
static struct clk clk_m2p4 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P4,
};
static struct clk clk_m2p5 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P5,
};
static struct clk clk_m2p6 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P6,
};
static struct clk clk_m2p7 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P7,
};
static struct clk clk_m2p8 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P8,
};
static struct clk clk_m2p9 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2P9,
};
static struct clk clk_m2m0 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M0,
};
static struct clk clk_m2m1 = {
	.parent		= &clk_h,
	.enable_reg	= EP93XX_SYSCON_PWRCNT,
	.enable_mask	= EP93XX_SYSCON_PWRCNT_DMA_M2M1,
};

#define INIT_CK(dev,con,ck)					\
	{ .dev_id = dev, .con_id = con, .clk = ck }

static struct clk_lookup clocks[] = {
	INIT_CK(NULL,			"xtali",	&clk_xtali),
	INIT_CK("apb:uart1",		NULL,		&clk_uart1),
	INIT_CK("apb:uart2",		NULL,		&clk_uart2),
	INIT_CK("apb:uart3",		NULL,		&clk_uart3),
	INIT_CK(NULL,			"pll1",		&clk_pll1),
	INIT_CK(NULL,			"fclk",		&clk_f),
	INIT_CK(NULL,			"hclk",		&clk_h),
	INIT_CK(NULL,			"pclk",		&clk_p),
	INIT_CK(NULL,			"pll2",		&clk_pll2),
	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
	INIT_CK(NULL,			"m2p2",		&clk_m2p2),
	INIT_CK(NULL,			"m2p3",		&clk_m2p3),
	INIT_CK(NULL,			"m2p4",		&clk_m2p4),
	INIT_CK(NULL,			"m2p5",		&clk_m2p5),
	INIT_CK(NULL,			"m2p6",		&clk_m2p6),
	INIT_CK(NULL,			"m2p7",		&clk_m2p7),
	INIT_CK(NULL,			"m2p8",		&clk_m2p8),
	INIT_CK(NULL,			"m2p9",		&clk_m2p9),
	INIT_CK(NULL,			"m2m0",		&clk_m2m0),
	INIT_CK(NULL,			"m2m1",		&clk_m2m1),
};

static DEFINE_SPINLOCK(clk_lock);

static void __clk_enable(struct clk *clk)
{
	if (!clk->users++) {
		if (clk->parent)
			__clk_enable(clk->parent);

		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v |= clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}
	}
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return -EINVAL;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	if (!--clk->users) {
		if (clk->enable_reg) {
			u32 v;

			v = __raw_readl(clk->enable_reg);
			v &= ~clk->enable_mask;
			if (clk->sw_locked)
				ep93xx_syscon_swlocked_write(v, clk->enable_reg);
			else
				__raw_writel(v, clk->enable_reg);
		}

		if (clk->parent)
			__clk_disable(clk->parent);
	}
}

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	if (!clk)
		return;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

static unsigned long get_uart_rate(struct clk *clk)
{
	unsigned long rate = clk_get_rate(clk->parent);
	u32 value;

	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
		return rate;
	else
		return rate / 2;
}

unsigned long clk_get_rate(struct clk *clk)
{
	if (clk->get_rate)
		return clk->get_rate(clk);

	return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);

static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
{
	u32 val;
	u32 div_bit;

	val = __raw_readl(clk->enable_reg);

	/*
	 * The Key Matrix and ADC clocks are configured using the same
	 * System Controller register.  The clock used will be either
	 * 1/4 or 1/16 the external clock rate depending on the
	 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	 * bit being set or cleared.
	 */
	div_bit = clk->enable_mask >> 15;

	if (rate == EP93XX_KEYTCHCLK_DIV4)
		val |= div_bit;
	else if (rate == EP93XX_KEYTCHCLK_DIV16)
		val &= ~div_bit;
	else
		return -EINVAL;

	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	clk->rate = rate;
	return 0;
}

static int calc_clk_div(struct clk *clk, unsigned long rate,
			int *psel, int *esel, int *pdiv, int *div)
{
	struct clk *mclk;
	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
	int i, found = 0, __div = 0, __pdiv = 0;

	/* Don't exceed the maximum rate */
	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
		       clk_xtali.rate / 4);
	rate = min(rate, max_rate);

	/*
	 * Try the two pll's and the external clock
	 * Because the valid predividers are 2, 2.5 and 3, we multiply
	 * all the clocks by 2 to avoid floating point math.
	 *
	 * This is based on the algorithm in the ep93xx raster guide:
	 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	 *
	 */
	for (i = 0; i < 3; i++) {
		if (i == 0)
			mclk = &clk_xtali;
		else if (i == 1)
			mclk = &clk_pll1;
		else
			mclk = &clk_pll2;
		mclk_rate = mclk->rate * 2;

		/* Try each predivider value */
		for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
			__div = mclk_rate / (rate * __pdiv);
			if (__div < 2 || __div > 127)
				continue;

			actual_rate = mclk_rate / (__pdiv * __div);

			if (!found || abs(actual_rate - rate) < rate_err) {
				*pdiv = __pdiv - 3;
				*div = __div;
				*psel = (i == 2);
				*esel = (i != 0);
				clk->parent = mclk;
				clk->rate = actual_rate;
				rate_err = abs(actual_rate - rate);
				found = 1;
			}
		}
	}

	if (!found)
		return -EINVAL;

	return 0;
}

static int set_div_rate(struct clk *clk, unsigned long rate)
{
	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
	u32 val;

	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	if (err)
		return err;

	/* Clear the esel, psel, pdiv and div bits */
	val = __raw_readl(clk->enable_reg);
	val &= ~0x7fff;

	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
		(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
		(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	return 0;
}

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	if (clk->set_rate)
		return clk->set_rate(clk, rate);

	return -EINVAL;
}
EXPORT_SYMBOL(clk_set_rate);


static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
static char pclk_divisors[] = { 1, 2, 4, 8 };

/*
 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
 */
static unsigned long calc_pll_rate(u32 config_word)
{
	unsigned long long rate;
	int i;

	rate = clk_xtali.rate;
	rate *= ((config_word >> 11) & 0x1f) + 1;		/* X1FBD */
	rate *= ((config_word >> 5) & 0x3f) + 1;		/* X2FBD */
	do_div(rate, (config_word & 0x1f) + 1);			/* X2IPD */
	for (i = 0; i < ((config_word >> 16) & 3); i++)		/* PS */
		rate >>= 1;

	return (unsigned long)rate;
}

static void __init ep93xx_dma_clock_init(void)
{
	clk_m2p0.rate = clk_h.rate;
	clk_m2p1.rate = clk_h.rate;
	clk_m2p2.rate = clk_h.rate;
	clk_m2p3.rate = clk_h.rate;
	clk_m2p4.rate = clk_h.rate;
	clk_m2p5.rate = clk_h.rate;
	clk_m2p6.rate = clk_h.rate;
	clk_m2p7.rate = clk_h.rate;
	clk_m2p8.rate = clk_h.rate;
	clk_m2p9.rate = clk_h.rate;
	clk_m2m0.rate = clk_h.rate;
	clk_m2m1.rate = clk_h.rate;
}

static int __init ep93xx_clock_init(void)
{
	u32 value;

	/* Determine the bootloader configured pll1 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
		clk_pll1.rate = clk_xtali.rate;
	else
		clk_pll1.rate = calc_pll_rate(value);

	/* Initialize the pll1 derived clocks */
	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
	ep93xx_dma_clock_init();

	/* Determine the bootloader configured pll2 rate */
	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
		clk_pll2.rate = clk_xtali.rate;
	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
		clk_pll2.rate = calc_pll_rate(value);
	else
		clk_pll2.rate = 0;

	/* Initialize the pll2 derived clocks */
	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);

	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
		clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
		clk_f.rate / 1000000, clk_h.rate / 1000000,
		clk_p.rate / 1000000);

	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
	return 0;
}
arch_initcall(ep93xx_clock_init);
Commit	Line	Data
1d81eedb LB	1	/*
	2	* arch/arm/mach-ep93xx/clock.c
	3	* Clock control for Cirrus EP93xx chips.
	4	*
	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or (at
	10	* your option) any later version.
	11	*/
	12
99acbb90 HS	13	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
99acbb90 HS	14
1d81eedb LB	15	#include <linux/kernel.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
51dd249e	18	#include <linux/module.h>
1d81eedb	19	#include <linux/string.h>
fced80c7	20	#include <linux/io.h>
ebd00c08 HS	21	#include <linux/spinlock.h>
	22
	23	#include <mach/hardware.h>
ae696fd5 RK	24
ae696fd5 RK	25	#include <asm/clkdev.h>
1d81eedb	26	#include <asm/div64.h>
1d81eedb	27
ff05c033	28
1d81eedb	29	struct clk {
ebd00c08	30	struct clk *parent;
1d81eedb LB	31	unsigned long rate;
1d81eedb LB	32	int users;
ff05c033	33	int sw_locked;
c3e3badd	34	void __iomem *enable_reg;
1d81eedb	35	u32 enable_mask;
ff05c033 HS	36
ff05c033 HS	37	unsigned long (get_rate)(struct clk clk);
701fac82	38	int (set_rate)(struct clk clk, unsigned long rate);
1d81eedb LB	39	};
1d81eedb LB	40
ff05c033 HS	41
	42	static unsigned long get_uart_rate(struct clk *clk);
	43
701fac82	44	static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
c6012189	45	static int set_div_rate(struct clk *clk, unsigned long rate);
ff05c033	46
ebd00c08 HS	47
	48	static struct clk clk_xtali = {
	49	.rate = EP93XX_EXT_CLK_RATE,
	50	};
ff05c033	51	static struct clk clk_uart1 = {
ebd00c08	52	.parent = &clk_xtali,
ff05c033	53	.sw_locked = 1,
02239f0a HS	54	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	55	.enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
ff05c033 HS	56	.get_rate = get_uart_rate,
	57	};
	58	static struct clk clk_uart2 = {
ebd00c08	59	.parent = &clk_xtali,
ff05c033	60	.sw_locked = 1,
02239f0a HS	61	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	62	.enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
ff05c033 HS	63	.get_rate = get_uart_rate,
	64	};
	65	static struct clk clk_uart3 = {
ebd00c08	66	.parent = &clk_xtali,
ff05c033	67	.sw_locked = 1,
02239f0a HS	68	.enable_reg = EP93XX_SYSCON_DEVCFG,
02239f0a HS	69	.enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
ff05c033	70	.get_rate = get_uart_rate,
ed519ded	71	};
ebd00c08 HS	72	static struct clk clk_pll1 = {
	73	.parent = &clk_xtali,
	74	};
	75	static struct clk clk_f = {
	76	.parent = &clk_pll1,
	77	};
	78	static struct clk clk_h = {
	79	.parent = &clk_pll1,
	80	};
	81	static struct clk clk_p = {
	82	.parent = &clk_pll1,
	83	};
	84	static struct clk clk_pll2 = {
	85	.parent = &clk_xtali,
	86	};
1d81eedb	87	static struct clk clk_usb_host = {
ebd00c08	88	.parent = &clk_pll2,
40702432 HS	89	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	90	.enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
1d81eedb	91	};
701fac82	92	static struct clk clk_keypad = {
ebd00c08	93	.parent = &clk_xtali,
701fac82 HS	94	.sw_locked = 1,
	95	.enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
	96	.enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
	97	.set_rate = set_keytchclk_rate,
	98	};
ef12379f	99	static struct clk clk_pwm = {
ebd00c08	100	.parent = &clk_xtali,
ef12379f HS	101	.rate = EP93XX_EXT_CLK_RATE,
ef12379f HS	102	};
1d81eedb	103
c6012189 RM	104	static struct clk clk_video = {
	105	.sw_locked = 1,
	106	.enable_reg = EP93XX_SYSCON_VIDCLKDIV,
	107	.enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
	108	.set_rate = set_div_rate,
	109	};
	110
1c8daabe RM	111	/* DMA Clocks */
1c8daabe RM	112	static struct clk clk_m2p0 = {
ebd00c08	113	.parent = &clk_h,
40702432 HS	114	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	115	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
1c8daabe RM	116	};
1c8daabe RM	117	static struct clk clk_m2p1 = {
ebd00c08	118	.parent = &clk_h,
40702432 HS	119	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	120	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
1c8daabe RM	121	};
1c8daabe RM	122	static struct clk clk_m2p2 = {
ebd00c08	123	.parent = &clk_h,
40702432 HS	124	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	125	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
1c8daabe RM	126	};
1c8daabe RM	127	static struct clk clk_m2p3 = {
ebd00c08	128	.parent = &clk_h,
40702432 HS	129	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	130	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
1c8daabe RM	131	};
1c8daabe RM	132	static struct clk clk_m2p4 = {
ebd00c08	133	.parent = &clk_h,
40702432 HS	134	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	135	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
1c8daabe RM	136	};
1c8daabe RM	137	static struct clk clk_m2p5 = {
ebd00c08	138	.parent = &clk_h,
40702432 HS	139	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	140	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
1c8daabe RM	141	};
1c8daabe RM	142	static struct clk clk_m2p6 = {
ebd00c08	143	.parent = &clk_h,
40702432 HS	144	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	145	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
1c8daabe RM	146	};
1c8daabe RM	147	static struct clk clk_m2p7 = {
ebd00c08	148	.parent = &clk_h,
40702432 HS	149	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	150	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
1c8daabe RM	151	};
1c8daabe RM	152	static struct clk clk_m2p8 = {
ebd00c08	153	.parent = &clk_h,
40702432 HS	154	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	155	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
1c8daabe RM	156	};
1c8daabe RM	157	static struct clk clk_m2p9 = {
ebd00c08	158	.parent = &clk_h,
40702432 HS	159	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	160	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
1c8daabe RM	161	};
1c8daabe RM	162	static struct clk clk_m2m0 = {
ebd00c08	163	.parent = &clk_h,
40702432 HS	164	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	165	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
1c8daabe RM	166	};
1c8daabe RM	167	static struct clk clk_m2m1 = {
ebd00c08	168	.parent = &clk_h,
40702432 HS	169	.enable_reg = EP93XX_SYSCON_PWRCNT,
40702432 HS	170	.enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
1c8daabe RM	171	};
1c8daabe RM	172
ae696fd5 RK	173	#define INIT_CK(dev,con,ck) \
	174	{ .dev_id = dev, .con_id = con, .clk = ck }
	175
	176	static struct clk_lookup clocks[] = {
ebd00c08	177	INIT_CK(NULL, "xtali", &clk_xtali),
701fac82 HS	178	INIT_CK("apb:uart1", NULL, &clk_uart1),
	179	INIT_CK("apb:uart2", NULL, &clk_uart2),
	180	INIT_CK("apb:uart3", NULL, &clk_uart3),
	181	INIT_CK(NULL, "pll1", &clk_pll1),
	182	INIT_CK(NULL, "fclk", &clk_f),
	183	INIT_CK(NULL, "hclk", &clk_h),
	184	INIT_CK(NULL, "pclk", &clk_p),
	185	INIT_CK(NULL, "pll2", &clk_pll2),
	186	INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
	187	INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
c6012189	188	INIT_CK("ep93xx-fb", NULL, &clk_video),
ef12379f	189	INIT_CK(NULL, "pwm_clk", &clk_pwm),
701fac82 HS	190	INIT_CK(NULL, "m2p0", &clk_m2p0),
	191	INIT_CK(NULL, "m2p1", &clk_m2p1),
	192	INIT_CK(NULL, "m2p2", &clk_m2p2),
	193	INIT_CK(NULL, "m2p3", &clk_m2p3),
	194	INIT_CK(NULL, "m2p4", &clk_m2p4),
	195	INIT_CK(NULL, "m2p5", &clk_m2p5),
	196	INIT_CK(NULL, "m2p6", &clk_m2p6),
	197	INIT_CK(NULL, "m2p7", &clk_m2p7),
	198	INIT_CK(NULL, "m2p8", &clk_m2p8),
	199	INIT_CK(NULL, "m2p9", &clk_m2p9),
	200	INIT_CK(NULL, "m2m0", &clk_m2m0),
	201	INIT_CK(NULL, "m2m1", &clk_m2m1),
1d81eedb LB	202	};
1d81eedb LB	203
ebd00c08 HS	204	static DEFINE_SPINLOCK(clk_lock);
	205
	206	static void __clk_enable(struct clk *clk)
	207	{
	208	if (!clk->users++) {
	209	if (clk->parent)
	210	__clk_enable(clk->parent);
	211
	212	if (clk->enable_reg) {
	213	u32 v;
	214
	215	v = __raw_readl(clk->enable_reg);
	216	v \|= clk->enable_mask;
	217	if (clk->sw_locked)
	218	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	219	else
	220	__raw_writel(v, clk->enable_reg);
	221	}
	222	}
	223	}
1d81eedb LB	224
	225	int clk_enable(struct clk *clk)
	226	{
ebd00c08	227	unsigned long flags;
1d81eedb	228
ebd00c08 HS	229	if (!clk)
	230	return -EINVAL;
	231
	232	spin_lock_irqsave(&clk_lock, flags);
	233	__clk_enable(clk);
	234	spin_unlock_irqrestore(&clk_lock, flags);
1d81eedb LB	235
	236	return 0;
	237	}
0c5d5b70	238	EXPORT_SYMBOL(clk_enable);
1d81eedb	239
ebd00c08	240	static void __clk_disable(struct clk *clk)
1d81eedb	241	{
ebd00c08 HS	242	if (!--clk->users) {
	243	if (clk->enable_reg) {
	244	u32 v;
	245
	246	v = __raw_readl(clk->enable_reg);
	247	v &= ~clk->enable_mask;
	248	if (clk->sw_locked)
	249	ep93xx_syscon_swlocked_write(v, clk->enable_reg);
	250	else
	251	__raw_writel(v, clk->enable_reg);
	252	}
1d81eedb	253
ebd00c08 HS	254	if (clk->parent)
ebd00c08 HS	255	__clk_disable(clk->parent);
1d81eedb LB	256	}
1d81eedb LB	257	}
ebd00c08 HS	258
	259	void clk_disable(struct clk *clk)
	260	{
	261	unsigned long flags;
	262
	263	if (!clk)
	264	return;
	265
	266	spin_lock_irqsave(&clk_lock, flags);
	267	__clk_disable(clk);
	268	spin_unlock_irqrestore(&clk_lock, flags);
	269	}
0c5d5b70	270	EXPORT_SYMBOL(clk_disable);
1d81eedb	271
ff05c033 HS	272	static unsigned long get_uart_rate(struct clk *clk)
ff05c033 HS	273	{
ebd00c08	274	unsigned long rate = clk_get_rate(clk->parent);
ff05c033 HS	275	u32 value;
ff05c033 HS	276
ca8cbc83 MK	277	value = __raw_readl(EP93XX_SYSCON_PWRCNT);
ca8cbc83 MK	278	if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
ebd00c08	279	return rate;
ff05c033	280	else
ebd00c08	281	return rate / 2;
ff05c033 HS	282	}
ff05c033 HS	283
1d81eedb LB	284	unsigned long clk_get_rate(struct clk *clk)
1d81eedb LB	285	{
ff05c033 HS	286	if (clk->get_rate)
	287	return clk->get_rate(clk);
	288
1d81eedb LB	289	return clk->rate;
1d81eedb LB	290	}
0c5d5b70	291	EXPORT_SYMBOL(clk_get_rate);
1d81eedb	292
701fac82 HS	293	static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
	294	{
	295	u32 val;
	296	u32 div_bit;
	297
	298	val = __raw_readl(clk->enable_reg);
	299
	300	/*
	301	* The Key Matrix and ADC clocks are configured using the same
	302	* System Controller register. The clock used will be either
	303	* 1/4 or 1/16 the external clock rate depending on the
	304	* EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
	305	* bit being set or cleared.
	306	*/
	307	div_bit = clk->enable_mask >> 15;
	308
	309	if (rate == EP93XX_KEYTCHCLK_DIV4)
	310	val \|= div_bit;
	311	else if (rate == EP93XX_KEYTCHCLK_DIV16)
	312	val &= ~div_bit;
	313	else
	314	return -EINVAL;
	315
	316	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	317	clk->rate = rate;
	318	return 0;
	319	}
	320
ebd00c08 HS	321	static int calc_clk_div(struct clk *clk, unsigned long rate,
ebd00c08 HS	322	int psel, int esel, int pdiv, int div)
c6012189	323	{
ebd00c08 HS	324	struct clk *mclk;
ebd00c08 HS	325	unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
c6012189 RM	326	int i, found = 0, __div = 0, __pdiv = 0;
	327
	328	/* Don't exceed the maximum rate */
	329	max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
ebd00c08	330	clk_xtali.rate / 4);
c6012189 RM	331	rate = min(rate, max_rate);
	332
	333	/*
	334	* Try the two pll's and the external clock
	335	* Because the valid predividers are 2, 2.5 and 3, we multiply
	336	* all the clocks by 2 to avoid floating point math.
	337	*
	338	* This is based on the algorithm in the ep93xx raster guide:
	339	* http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
	340	*
	341	*/
	342	for (i = 0; i < 3; i++) {
	343	if (i == 0)
ebd00c08	344	mclk = &clk_xtali;
c6012189	345	else if (i == 1)
ebd00c08 HS	346	mclk = &clk_pll1;
	347	else
	348	mclk = &clk_pll2;
	349	mclk_rate = mclk->rate * 2;
c6012189 RM	350
	351	/* Try each predivider value */
	352	for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
	353	__div = mclk_rate / (rate * __pdiv);
	354	if (__div < 2 \|\| __div > 127)
	355	continue;
	356
	357	actual_rate = mclk_rate / (__pdiv * __div);
	358
	359	if (!found \|\| abs(actual_rate - rate) < rate_err) {
	360	*pdiv = __pdiv - 3;
	361	*div = __div;
	362	*psel = (i == 2);
	363	*esel = (i != 0);
ebd00c08 HS	364	clk->parent = mclk;
ebd00c08 HS	365	clk->rate = actual_rate;
c6012189 RM	366	rate_err = abs(actual_rate - rate);
	367	found = 1;
	368	}
	369	}
	370	}
	371
	372	if (!found)
ebd00c08	373	return -EINVAL;
c6012189	374
ebd00c08	375	return 0;
c6012189 RM	376	}
	377
	378	static int set_div_rate(struct clk *clk, unsigned long rate)
	379	{
ebd00c08	380	int err, psel = 0, esel = 0, pdiv = 0, div = 0;
c6012189 RM	381	u32 val;
c6012189 RM	382
ebd00c08 HS	383	err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
	384	if (err)
	385	return err;
c6012189 RM	386
	387	/* Clear the esel, psel, pdiv and div bits */
	388	val = __raw_readl(clk->enable_reg);
	389	val &= ~0x7fff;
	390
	391	/* Set the new esel, psel, pdiv and div bits for the new clock rate */
	392	val \|= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) \|
	393	(psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) \|
	394	(pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) \| div;
	395	ep93xx_syscon_swlocked_write(val, clk->enable_reg);
	396	return 0;
	397	}
	398
701fac82 HS	399	int clk_set_rate(struct clk *clk, unsigned long rate)
	400	{
	401	if (clk->set_rate)
	402	return clk->set_rate(clk, rate);
	403
	404	return -EINVAL;
	405	}
	406	EXPORT_SYMBOL(clk_set_rate);
	407
1d81eedb LB	408
	409	static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
	410	static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
	411	static char pclk_divisors[] = { 1, 2, 4, 8 };
	412
	413	/*
	414	* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
	415	*/
	416	static unsigned long calc_pll_rate(u32 config_word)
	417	{
	418	unsigned long long rate;
	419	int i;
	420
ebd00c08	421	rate = clk_xtali.rate;
1d81eedb LB	422	rate = ((config_word >> 11) & 0x1f) + 1; / X1FBD */
	423	rate = ((config_word >> 5) & 0x3f) + 1; / X2FBD */
	424	do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
	425	for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
	426	rate >>= 1;
	427
	428	return (unsigned long)rate;
	429	}
	430
1c8daabe RM	431	static void __init ep93xx_dma_clock_init(void)
	432	{
	433	clk_m2p0.rate = clk_h.rate;
	434	clk_m2p1.rate = clk_h.rate;
	435	clk_m2p2.rate = clk_h.rate;
	436	clk_m2p3.rate = clk_h.rate;
	437	clk_m2p4.rate = clk_h.rate;
	438	clk_m2p5.rate = clk_h.rate;
	439	clk_m2p6.rate = clk_h.rate;
	440	clk_m2p7.rate = clk_h.rate;
	441	clk_m2p8.rate = clk_h.rate;
	442	clk_m2p9.rate = clk_h.rate;
	443	clk_m2m0.rate = clk_h.rate;
	444	clk_m2m1.rate = clk_h.rate;
	445	}
	446
51dd249e	447	static int __init ep93xx_clock_init(void)
1d81eedb LB	448	{
	449	u32 value;
	450
346e34ab HS	451	/* Determine the bootloader configured pll1 rate */
	452	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
	453	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
ebd00c08	454	clk_pll1.rate = clk_xtali.rate;
346e34ab	455	else
1d81eedb	456	clk_pll1.rate = calc_pll_rate(value);
346e34ab HS	457
346e34ab HS	458	/* Initialize the pll1 derived clocks */
1d81eedb LB	459	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
	460	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
	461	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
1c8daabe	462	ep93xx_dma_clock_init();
1d81eedb	463
346e34ab	464	/* Determine the bootloader configured pll2 rate */
ba7c6a3b	465	value = __raw_readl(EP93XX_SYSCON_CLKSET2);
346e34ab	466	if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
ebd00c08	467	clk_pll2.rate = clk_xtali.rate;
346e34ab	468	else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
1d81eedb	469	clk_pll2.rate = calc_pll_rate(value);
346e34ab	470	else
1d81eedb	471	clk_pll2.rate = 0;
346e34ab HS	472
346e34ab HS	473	/* Initialize the pll2 derived clocks */
1d81eedb LB	474	clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
1d81eedb LB	475
99acbb90	476	pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
1d81eedb	477	clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
99acbb90	478	pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
1d81eedb LB	479	clk_f.rate / 1000000, clk_h.rate / 1000000,
1d81eedb LB	480	clk_p.rate / 1000000);
51dd249e	481
0a0300dc	482	clkdev_add_table(clocks, ARRAY_SIZE(clocks));
51dd249e	483	return 0;
1d81eedb	484	}
51dd249e	485	arch_initcall(ep93xx_clock_init);