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Merge tag 'rdma-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[deliverable/linux.git] / arch / arm / mach-ep93xx / core.c
CommitLineData
e7736d47
LB		 1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47
LB		 7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
64d6882d
HS		 17#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
e7736d47
LB		 19#include <linux/kernel.h>
20#include <linux/init.h>
583ddafe 21#include <linux/platform_device.h>
e7736d47 22#include <linux/interrupt.h>
63890a0e 23#include <linux/dma-mapping.h>
b19e11fb 24#include <linux/sys_soc.h>
e7736d47 25#include <linux/timex.h>
6bd4b382 26#include <linux/irq.h>
583ddafe
HS		 27#include <linux/io.h>
28#include <linux/gpio.h>
3aa7a9a3 29#include <linux/leds.h>
aee85fe8 30#include <linux/termios.h>
e7736d47 31#include <linux/amba/bus.h>
aee85fe8 32#include <linux/amba/serial.h>
16bcf78f 33#include <linux/mtd/physmap.h>
d52a26a9
HS		 34#include <linux/i2c.h>
35#include <linux/i2c-gpio.h>
4fec9978 36#include <linux/spi/spi.h>
dc28094b 37#include <linux/export.h>
9e47b8bf 38#include <linux/irqchip/arm-vic.h>
7b6d864b 39#include <linux/reboot.h>
e55f7cd2 40#include <linux/usb/ohci_pdriver.h>
e7736d47 41
a09e64fb 42#include <mach/hardware.h>
a3b29245
AB		 43#include <linux/platform_data/video-ep93xx.h>
44#include <linux/platform_data/keypad-ep93xx.h>
45#include <linux/platform_data/spi-ep93xx.h>
bd5f12a2 46#include <mach/gpio-ep93xx.h>
e7736d47 47
b19e11fb 48#include <asm/mach/arch.h>
e7736d47
LB		 49#include <asm/mach/map.h>
50#include <asm/mach/time.h>
e7736d47 51
a05baf33 52#include "soc.h"
e7736d47
LB		 53
54/*************************************************************************
55 * Static I/O mappings that are needed for all EP93xx platforms
56 *************************************************************************/
57static struct map_desc ep93xx_io_desc[] __initdata = {
58 {
59 .virtual = EP93XX_AHB_VIRT_BASE,
60 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
61 .length = EP93XX_AHB_SIZE,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = EP93XX_APB_VIRT_BASE,
65 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
66 .length = EP93XX_APB_SIZE,
67 .type = MT_DEVICE,
68 },
69};
70
71void __init ep93xx_map_io(void)
72{
73 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
74}
75
76
77/*************************************************************************
78 * Timer handling for EP93xx
79 *************************************************************************
80 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
81 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
82 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
83 * is free-running, and can't generate interrupts.
84 *
85 * The 508 kHz timers are ideal for use for the timer interrupt, as the
86 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
87 * bit timers (timer 1) since we don't need more than 16 bits of reload
88 * value as long as HZ >= 8.
89 *
90 * The higher clock rate of timer 4 makes it a better choice than the
91 * other timers for use in gettimeoffset(), while the fact that it can't
92 * generate interrupts means we don't have to worry about not being able
93 * to use this timer for something else. We also use timer 4 for keeping
94 * track of lost jiffies.
95 */
1587a373
HS		 96#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
97#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
98#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
99#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
100#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
101#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
102#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
103#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
104#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
105#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
106#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
107#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
108#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
109#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
110#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
111#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
112#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
113#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
114#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
115
116#define EP93XX_TIMER123_CLOCK 508469
117#define EP93XX_TIMER4_CLOCK 983040
118
119#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
a509ad0c 120#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)
e7736d47 121
1587a373
HS		 122static unsigned int last_jiffy_time;
123
d5565f76 124static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47 125{
1587a373 126 /* Writing any value clears the timer interrupt */
e7736d47 127 __raw_writel(1, EP93XX_TIMER1_CLEAR);
1587a373
HS		 128
129 /* Recover lost jiffies */
f869afab
LB		 130 while ((signed long)
131 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47
LB		 132 >= TIMER4_TICKS_PER_JIFFY) {
133 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68 134 timer_tick();
e7736d47
LB		 135 }
136
e7736d47
LB		 137 return IRQ_HANDLED;
138}
139
140static struct irqaction ep93xx_timer_irq = {
141 .name = "ep93xx timer",
3a71ae47 142 .flags = IRQF_TIMER | IRQF_IRQPOLL,
e7736d47
LB		 143 .handler = ep93xx_timer_interrupt,
144};
145
23c197b7
SW		 146static u32 ep93xx_gettimeoffset(void)
147{
148 int offset;
149
150 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
151
152 /*
153 * Timer 4 is based on a 983.04 kHz reference clock,
154 * so dividing by 983040 gives the fraction of a second,
155 * so dividing by 0.983040 converts to uS.
156 * Refactor the calculation to avoid overflow.
157 * Finally, multiply by 1000 to give nS.
158 */
159 return (offset + (53 * offset / 3072)) * 1000;
160}
161
6bb27d73 162void __init ep93xx_timer_init(void)
e7736d47 163{
1587a373
HS		 164 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
165 EP93XX_TIMER123_CONTROL_CLKSEL;
166
23c197b7
SW		 167 arch_gettimeoffset = ep93xx_gettimeoffset;
168
e7736d47 169 /* Enable periodic HZ timer. */
1587a373
HS		 170 __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
171 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
172 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
173 EP93XX_TIMER1_CONTROL);
e7736d47
LB		 174
175 /* Enable lost jiffy timer. */
1587a373
HS		 176 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
177 EP93XX_TIMER4_VALUE_HIGH);
e7736d47
LB		 178
179 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
180}
181
e7736d47
LB		 182
183/*************************************************************************
184 * EP93xx IRQ handling
185 *************************************************************************/
186void __init ep93xx_init_irq(void)
187{
5396730b
HS		 188 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
189 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
e7736d47
LB		 190}
191
192
02239f0a
HS		 193/*************************************************************************
194 * EP93xx System Controller Software Locked register handling
195 *************************************************************************/
196
197/*
198 * syscon_swlock prevents anything else from writing to the syscon
199 * block while a software locked register is being written.
200 */
201static DEFINE_SPINLOCK(syscon_swlock);
202
fbeeea53 203void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
02239f0a
HS		 204{
205 unsigned long flags;
206
207 spin_lock_irqsave(&syscon_swlock, flags);
208
209 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
210 __raw_writel(val, reg);
211
212 spin_unlock_irqrestore(&syscon_swlock, flags);
213}
02239f0a
HS		 214
215void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
216{
217 unsigned long flags;
218 unsigned int val;
219
220 spin_lock_irqsave(&syscon_swlock, flags);
221
222 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
02239f0a 223 val &= ~clear_bits;
a0fb007b 224 val |= set_bits;
02239f0a
HS		 225 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
226 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
227
228 spin_unlock_irqrestore(&syscon_swlock, flags);
229}
02239f0a 230
99e6a23a
MW		 231/**
232 * ep93xx_chip_revision() - returns the EP93xx chip revision
233 *
234 * See <mach/platform.h> for more information.
235 */
236unsigned int ep93xx_chip_revision(void)
237{
238 unsigned int v;
239
240 v = __raw_readl(EP93XX_SYSCON_SYSCFG);
241 v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
242 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
243 return v;
244}
67e108c5 245EXPORT_SYMBOL_GPL(ep93xx_chip_revision);
02239f0a 246
1e4c8842
HS		 247/*************************************************************************
248 * EP93xx GPIO
249 *************************************************************************/
250static struct resource ep93xx_gpio_resource[] = {
ede55aaa 251 DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
1e4c8842
HS		 252};
253
254static struct platform_device ep93xx_gpio_device = {
255 .name = "gpio-ep93xx",
256 .id = -1,
257 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
258 .resource = ep93xx_gpio_resource,
259};
260
e7736d47
LB		 261/*************************************************************************
262 * EP93xx peripheral handling
263 *************************************************************************/
aee85fe8
LB		 264#define EP93XX_UART_MCR_OFFSET (0x0100)
265
266static void ep93xx_uart_set_mctrl(struct amba_device *dev,
267 void __iomem *base, unsigned int mctrl)
268{
269 unsigned int mcr;
270
271 mcr = 0;
186dcaa4 272 if (mctrl & TIOCM_RTS)
aee85fe8 273 mcr |= 2;
186dcaa4 274 if (mctrl & TIOCM_DTR)
aee85fe8
LB		 275 mcr |= 1;
276
277 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
278}
279
280static struct amba_pl010_data ep93xx_uart_data = {
281 .set_mctrl = ep93xx_uart_set_mctrl,
282};
283
0b26051b
RK		 284static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
285 { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
aee85fe8 286
0b26051b 287static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
cc3874fe 288 { IRQ_EP93XX_UART2 }, NULL);
aee85fe8 289
0b26051b
RK		 290static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
291 { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
41658132 292
38f7b009 293static struct resource ep93xx_rtc_resource[] = {
ede55aaa 294 DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
38f7b009
HS		 295};
296
41658132 297static struct platform_device ep93xx_rtc_device = {
38f7b009
HS		 298 .name = "ep93xx-rtc",
299 .id = -1,
300 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
301 .resource = ep93xx_rtc_resource,
41658132
LB		 302};
303
e55f7cd2
HS		 304/*************************************************************************
305 * EP93xx OHCI USB Host
306 *************************************************************************/
307
308static struct clk *ep93xx_ohci_host_clock;
309
310static int ep93xx_ohci_power_on(struct platform_device *pdev)
311{
312 if (!ep93xx_ohci_host_clock) {
313 ep93xx_ohci_host_clock = devm_clk_get(&pdev->dev, NULL);
314 if (IS_ERR(ep93xx_ohci_host_clock))
315 return PTR_ERR(ep93xx_ohci_host_clock);
316 }
317
318 return clk_enable(ep93xx_ohci_host_clock);
319}
320
321static void ep93xx_ohci_power_off(struct platform_device *pdev)
322{
323 clk_disable(ep93xx_ohci_host_clock);
324}
325
326static struct usb_ohci_pdata ep93xx_ohci_pdata = {
327 .power_on = ep93xx_ohci_power_on,
328 .power_off = ep93xx_ohci_power_off,
329 .power_suspend = ep93xx_ohci_power_off,
330};
41658132 331
1f64eb37 332static struct resource ep93xx_ohci_resources[] = {
ede55aaa
HS		 333 DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
334 DEFINE_RES_IRQ(IRQ_EP93XX_USB),
1f64eb37
LB		 335};
336
e55f7cd2 337static u64 ep93xx_ohci_dma_mask = DMA_BIT_MASK(32);
63890a0e 338
1f64eb37 339static struct platform_device ep93xx_ohci_device = {
e55f7cd2 340 .name = "ohci-platform",
1f64eb37 341 .id = -1,
e55f7cd2
HS		 342 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
343 .resource = ep93xx_ohci_resources,
1f64eb37 344 .dev = {
e55f7cd2 345 .dma_mask = &ep93xx_ohci_dma_mask,
63890a0e 346 .coherent_dma_mask = DMA_BIT_MASK(32),
e55f7cd2 347 .platform_data = &ep93xx_ohci_pdata,
1f64eb37 348 },
1f64eb37
LB		 349};
350
16bcf78f
HS		 351/*************************************************************************
352 * EP93xx physmap'ed flash
353 *************************************************************************/
354static struct physmap_flash_data ep93xx_flash_data;
355
356static struct resource ep93xx_flash_resource = {
357 .flags = IORESOURCE_MEM,
358};
359
360static struct platform_device ep93xx_flash = {
361 .name = "physmap-flash",
362 .id = 0,
363 .dev = {
364 .platform_data = &ep93xx_flash_data,
365 },
366 .num_resources = 1,
367 .resource = &ep93xx_flash_resource,
368};
369
370/**
371 * ep93xx_register_flash() - Register the external flash device.
372 * @width: bank width in octets
373 * @start: resource start address
374 * @size: resource size
375 */
376void __init ep93xx_register_flash(unsigned int width,
377 resource_size_t start, resource_size_t size)
378{
379 ep93xx_flash_data.width = width;
380
381 ep93xx_flash_resource.start = start;
382 ep93xx_flash_resource.end = start + size - 1;
383
384 platform_device_register(&ep93xx_flash);
385}
386
387
b370e082
HS		 388/*************************************************************************
389 * EP93xx ethernet peripheral handling
390 *************************************************************************/
a0a08fdc
HS		 391static struct ep93xx_eth_data ep93xx_eth_data;
392
393static struct resource ep93xx_eth_resource[] = {
ede55aaa 394 DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
011b2e84 395 DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
a0a08fdc
HS		 396};
397
fa70cf47
MW		 398static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
399
a0a08fdc
HS		 400static struct platform_device ep93xx_eth_device = {
401 .name = "ep93xx-eth",
402 .id = -1,
403 .dev = {
fa70cf47
MW		 404 .platform_data = &ep93xx_eth_data,
405 .coherent_dma_mask = DMA_BIT_MASK(32),
406 .dma_mask = &ep93xx_eth_dma_mask,
a0a08fdc
HS		 407 },
408 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
409 .resource = ep93xx_eth_resource,
410};
411
b370e082
HS		 412/**
413 * ep93xx_register_eth - Register the built-in ethernet platform device.
414 * @data: platform specific ethernet configuration (__initdata)
415 * @copy_addr: flag indicating that the MAC address should be copied
416 * from the IndAd registers (as programmed by the bootloader)
417 */
a0a08fdc
HS		 418void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
419{
5b1c3c85
HS		 420 if (copy_addr)
421 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
a0a08fdc
HS		 422
423 ep93xx_eth_data = *data;
424 platform_device_register(&ep93xx_eth_device);
425}
426
6531a991
HS		 427
428/*************************************************************************
429 * EP93xx i2c peripheral handling
430 *************************************************************************/
431static struct i2c_gpio_platform_data ep93xx_i2c_data;
d52a26a9
HS		 432
433static struct platform_device ep93xx_i2c_device = {
b370e082
HS		 434 .name = "i2c-gpio",
435 .id = 0,
436 .dev = {
437 .platform_data = &ep93xx_i2c_data,
438 },
d52a26a9
HS		 439};
440
b370e082
HS		 441/**
442 * ep93xx_register_i2c - Register the i2c platform device.
443 * @data: platform specific i2c-gpio configuration (__initdata)
444 * @devices: platform specific i2c bus device information (__initdata)
445 * @num: the number of devices on the i2c bus
446 */
6531a991
HS		 447void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
448 struct i2c_board_info *devices, int num)
d52a26a9 449{
6531a991
HS		 450 /*
451 * Set the EEPROM interface pin drive type control.
452 * Defines the driver type for the EECLK and EEDAT pins as either
453 * open drain, which will require an external pull-up, or a normal
454 * CMOS driver.
455 */
456 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
64d6882d 457 pr_warning("sda != EEDAT, open drain has no effect\n");
6531a991 458 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
64d6882d 459 pr_warning("scl != EECLK, open drain has no effect\n");
6531a991
HS		 460
461 __raw_writel((data->sda_is_open_drain << 1) |
462 (data->scl_is_open_drain << 0),
463 EP93XX_GPIO_EEDRIVE);
464
465 ep93xx_i2c_data = *data;
d52a26a9
HS		 466 i2c_register_board_info(0, devices, num);
467 platform_device_register(&ep93xx_i2c_device);
468}
469
4fec9978
MW		 470/*************************************************************************
471 * EP93xx SPI peripheral handling
472 *************************************************************************/
473static struct ep93xx_spi_info ep93xx_spi_master_data;
474
475static struct resource ep93xx_spi_resources[] = {
ede55aaa
HS		 476 DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
477 DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
4fec9978
MW		 478};
479
626a96db
MW		 480static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
481
4fec9978
MW		 482static struct platform_device ep93xx_spi_device = {
483 .name = "ep93xx-spi",
484 .id = 0,
485 .dev = {
626a96db
MW		 486 .platform_data = &ep93xx_spi_master_data,
487 .coherent_dma_mask = DMA_BIT_MASK(32),
488 .dma_mask = &ep93xx_spi_dma_mask,
4fec9978
MW		 489 },
490 .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
491 .resource = ep93xx_spi_resources,
492};
493
494/**
495 * ep93xx_register_spi() - registers spi platform device
496 * @info: ep93xx board specific spi master info (__initdata)
497 * @devices: SPI devices to register (__initdata)
498 * @num: number of SPI devices to register
499 *
500 * This function registers platform device for the EP93xx SPI controller and
501 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
502 */
503void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
504 struct spi_board_info *devices, int num)
505{
506 /*
507 * When SPI is used, we need to make sure that I2S is muxed off from
508 * SPI pins.
509 */
510 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
511
512 ep93xx_spi_master_data = *info;
513 spi_register_board_info(devices, num);
514 platform_device_register(&ep93xx_spi_device);
515}
3aa7a9a3
HS		 516
517/*************************************************************************
518 * EP93xx LEDs
519 *************************************************************************/
a1eacd79 520static const struct gpio_led ep93xx_led_pins[] __initconst = {
3aa7a9a3 521 {
b370e082
HS		 522 .name = "platform:grled",
523 .gpio = EP93XX_GPIO_LINE_GRLED,
3aa7a9a3 524 }, {
b370e082
HS		 525 .name = "platform:rdled",
526 .gpio = EP93XX_GPIO_LINE_RDLED,
3aa7a9a3
HS		 527 },
528};
529
a1eacd79 530static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
3aa7a9a3
HS		 531 .num_leds = ARRAY_SIZE(ep93xx_led_pins),
532 .leds = ep93xx_led_pins,
533};
534
ef12379f
HS		 535/*************************************************************************
536 * EP93xx pwm peripheral handling
537 *************************************************************************/
538static struct resource ep93xx_pwm0_resource[] = {
ede55aaa 539 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
ef12379f
HS		 540};
541
542static struct platform_device ep93xx_pwm0_device = {
543 .name = "ep93xx-pwm",
544 .id = 0,
545 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
546 .resource = ep93xx_pwm0_resource,
547};
548
549static struct resource ep93xx_pwm1_resource[] = {
ede55aaa 550 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
ef12379f
HS		 551};
552
553static struct platform_device ep93xx_pwm1_device = {
554 .name = "ep93xx-pwm",
555 .id = 1,
556 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
557 .resource = ep93xx_pwm1_resource,
558};
559
560void __init ep93xx_register_pwm(int pwm0, int pwm1)
561{
562 if (pwm0)
563 platform_device_register(&ep93xx_pwm0_device);
564
565 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
566 if (pwm1)
567 platform_device_register(&ep93xx_pwm1_device);
568}
569
570int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
571{
572 int err;
573
574 if (pdev->id == 0) {
575 err = 0;
576 } else if (pdev->id == 1) {
577 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
578 dev_name(&pdev->dev));
579 if (err)
580 return err;
581 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
582 if (err)
583 goto fail;
584
585 /* PWM 1 output on EGPIO[14] */
586 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
587 } else {
588 err = -ENODEV;
589 }
590
591 return err;
592
593fail:
594 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
595 return err;
596}
597EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
598
599void ep93xx_pwm_release_gpio(struct platform_device *pdev)
600{
601 if (pdev->id == 1) {
602 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
603 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
604
605 /* EGPIO[14] used for GPIO */
606 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
607 }
608}
609EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
610
611
c6012189
RM		 612/*************************************************************************
613 * EP93xx video peripheral handling
614 *************************************************************************/
615static struct ep93xxfb_mach_info ep93xxfb_data;
616
617static struct resource ep93xx_fb_resource[] = {
ede55aaa 618 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
c6012189
RM		 619};
620
621static struct platform_device ep93xx_fb_device = {
622 .name = "ep93xx-fb",
623 .id = -1,
624 .dev = {
b370e082 625 .platform_data = &ep93xxfb_data,
c6012189
RM		 626 .coherent_dma_mask = DMA_BIT_MASK(32),
627 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
628 },
629 .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
630 .resource = ep93xx_fb_resource,
631};
632
0fd19580
RM		 633/* The backlight use a single register in the framebuffer's register space */
634#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
635
636static struct resource ep93xx_bl_resources[] = {
637 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
638 EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
639};
640
6ea4b741
HS		 641static struct platform_device ep93xx_bl_device = {
642 .name = "ep93xx-bl",
643 .id = -1,
0fd19580
RM		 644 .num_resources = ARRAY_SIZE(ep93xx_bl_resources),
645 .resource = ep93xx_bl_resources,
6ea4b741
HS		 646};
647
b370e082
HS		 648/**
649 * ep93xx_register_fb - Register the framebuffer platform device.
650 * @data: platform specific framebuffer configuration (__initdata)
651 */
c6012189
RM		 652void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
653{
654 ep93xxfb_data = *data;
655 platform_device_register(&ep93xx_fb_device);
6ea4b741 656 platform_device_register(&ep93xx_bl_device);
c6012189
RM		 657}
658
12f56c68
HS		 659
660/*************************************************************************
661 * EP93xx matrix keypad peripheral handling
662 *************************************************************************/
b370e082
HS		 663static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
664
12f56c68 665static struct resource ep93xx_keypad_resource[] = {
ede55aaa
HS		 666 DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
667 DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
12f56c68
HS		 668};
669
670static struct platform_device ep93xx_keypad_device = {
b370e082
HS		 671 .name = "ep93xx-keypad",
672 .id = -1,
673 .dev = {
674 .platform_data = &ep93xx_keypad_data,
675 },
676 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
677 .resource = ep93xx_keypad_resource,
12f56c68
HS		 678};
679
b370e082
HS		 680/**
681 * ep93xx_register_keypad - Register the keypad platform device.
682 * @data: platform specific keypad configuration (__initdata)
683 */
12f56c68
HS		 684void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
685{
b370e082 686 ep93xx_keypad_data = *data;
12f56c68
HS		 687 platform_device_register(&ep93xx_keypad_device);
688}
689
690int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
691{
692 int err;
693 int i;
694
695 for (i = 0; i < 8; i++) {
696 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
697 if (err)
698 goto fail_gpio_c;
699 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
700 if (err)
701 goto fail_gpio_d;
702 }
703
704 /* Enable the keypad controller; GPIO ports C and D used for keypad */
705 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
706 EP93XX_SYSCON_DEVCFG_GONK);
707
708 return 0;
709
710fail_gpio_d:
711 gpio_free(EP93XX_GPIO_LINE_C(i));
712fail_gpio_c:
5528a846 713 for (--i; i >= 0; --i) {
12f56c68
HS		 714 gpio_free(EP93XX_GPIO_LINE_C(i));
715 gpio_free(EP93XX_GPIO_LINE_D(i));
716 }
717 return err;
718}
719EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
720
721void ep93xx_keypad_release_gpio(struct platform_device *pdev)
722{
723 int i;
724
725 for (i = 0; i < 8; i++) {
726 gpio_free(EP93XX_GPIO_LINE_C(i));
727 gpio_free(EP93XX_GPIO_LINE_D(i));
728 }
729
730 /* Disable the keypad controller; GPIO ports C and D used for GPIO */
731 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
732 EP93XX_SYSCON_DEVCFG_GONK);
733}
734EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
735
ed67ea82
RM		 736/*************************************************************************
737 * EP93xx I2S audio peripheral handling
738 *************************************************************************/
739static struct resource ep93xx_i2s_resource[] = {
ede55aaa 740 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
ed67ea82
RM		 741};
742
743static struct platform_device ep93xx_i2s_device = {
744 .name = "ep93xx-i2s",
745 .id = -1,
746 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
747 .resource = ep93xx_i2s_resource,
748};
749
f0fba2ad
LG		 750static struct platform_device ep93xx_pcm_device = {
751 .name = "ep93xx-pcm-audio",
752 .id = -1,
753};
754
ed67ea82
RM		 755void __init ep93xx_register_i2s(void)
756{
757 platform_device_register(&ep93xx_i2s_device);
f0fba2ad 758 platform_device_register(&ep93xx_pcm_device);
ed67ea82
RM		 759}
760
761#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
762 EP93XX_SYSCON_DEVCFG_I2SONAC97)
763
764#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
765 EP93XX_SYSCON_I2SCLKDIV_SPOL)
766
f15855bf 767int ep93xx_i2s_acquire(void)
ed67ea82
RM		 768{
769 unsigned val;
770
f15855bf
RM		 771 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
772 EP93XX_SYSCON_DEVCFG_I2S_MASK);
ed67ea82
RM		 773
774 /*
775 * This is potentially racy with the clock api for i2s_mclk, sclk and
776 * lrclk. Since the i2s driver is the only user of those clocks we
777 * rely on it to prevent parallel use of this function and the
778 * clock api for the i2s clocks.
779 */
780 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
781 val &= ~EP93XX_I2SCLKDIV_MASK;
f15855bf 782 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
ed67ea82
RM		 783 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
784
785 return 0;
786}
787EXPORT_SYMBOL(ep93xx_i2s_acquire);
788
789void ep93xx_i2s_release(void)
790{
791 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
792}
793EXPORT_SYMBOL(ep93xx_i2s_release);
12f56c68 794
534bc7fa
MW		 795/*************************************************************************
796 * EP93xx AC97 audio peripheral handling
797 *************************************************************************/
798static struct resource ep93xx_ac97_resources[] = {
ede55aaa
HS		 799 DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
800 DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
534bc7fa
MW		 801};
802
803static struct platform_device ep93xx_ac97_device = {
804 .name = "ep93xx-ac97",
805 .id = -1,
806 .num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
807 .resource = ep93xx_ac97_resources,
808};
809
810void __init ep93xx_register_ac97(void)
811{
812 /*
813 * Make sure that the AC97 pins are not used by I2S.
814 */
815 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
816
817 platform_device_register(&ep93xx_ac97_device);
818 platform_device_register(&ep93xx_pcm_device);
819}
820
73303d12
HS		 821/*************************************************************************
822 * EP93xx Watchdog
823 *************************************************************************/
824static struct resource ep93xx_wdt_resources[] = {
825 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
826};
827
828static struct platform_device ep93xx_wdt_device = {
829 .name = "ep93xx-wdt",
830 .id = -1,
831 .num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
832 .resource = ep93xx_wdt_resources,
833};
834
eb774a09
RP		 835/*************************************************************************
836 * EP93xx IDE
837 *************************************************************************/
838static struct resource ep93xx_ide_resources[] = {
839 DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
840 DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
841};
842
843static struct platform_device ep93xx_ide_device = {
844 .name = "ep93xx-ide",
845 .id = -1,
846 .dev = {
847 .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
848 .coherent_dma_mask = DMA_BIT_MASK(32),
849 },
850 .num_resources = ARRAY_SIZE(ep93xx_ide_resources),
851 .resource = ep93xx_ide_resources,
852};
853
854void __init ep93xx_register_ide(void)
855{
856 platform_device_register(&ep93xx_ide_device);
857}
858
859int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
860{
861 int err;
862 int i;
863
864 err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
865 if (err)
866 return err;
867 err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
868 if (err)
869 goto fail_egpio15;
870 for (i = 2; i < 8; i++) {
871 err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
872 if (err)
873 goto fail_gpio_e;
874 }
875 for (i = 4; i < 8; i++) {
876 err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
877 if (err)
878 goto fail_gpio_g;
879 }
880 for (i = 0; i < 8; i++) {
881 err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
882 if (err)
883 goto fail_gpio_h;
884 }
885
886 /* GPIO ports E[7:2], G[7:4] and H used by IDE */
887 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
888 EP93XX_SYSCON_DEVCFG_GONIDE |
889 EP93XX_SYSCON_DEVCFG_HONIDE);
890 return 0;
891
892fail_gpio_h:
893 for (--i; i >= 0; --i)
894 gpio_free(EP93XX_GPIO_LINE_H(i));
895 i = 8;
896fail_gpio_g:
897 for (--i; i >= 4; --i)
898 gpio_free(EP93XX_GPIO_LINE_G(i));
899 i = 8;
900fail_gpio_e:
901 for (--i; i >= 2; --i)
902 gpio_free(EP93XX_GPIO_LINE_E(i));
903 gpio_free(EP93XX_GPIO_LINE_EGPIO15);
904fail_egpio15:
905 gpio_free(EP93XX_GPIO_LINE_EGPIO2);
906 return err;
907}
908EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
909
910void ep93xx_ide_release_gpio(struct platform_device *pdev)
911{
912 int i;
913
914 for (i = 2; i < 8; i++)
915 gpio_free(EP93XX_GPIO_LINE_E(i));
916 for (i = 4; i < 8; i++)
917 gpio_free(EP93XX_GPIO_LINE_G(i));
918 for (i = 0; i < 8; i++)
919 gpio_free(EP93XX_GPIO_LINE_H(i));
920 gpio_free(EP93XX_GPIO_LINE_EGPIO15);
921 gpio_free(EP93XX_GPIO_LINE_EGPIO2);
922
923
924 /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
925 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
926 EP93XX_SYSCON_DEVCFG_GONIDE |
927 EP93XX_SYSCON_DEVCFG_HONIDE);
928}
929EXPORT_SYMBOL(ep93xx_ide_release_gpio);
930
b19e11fb
HS		 931/*************************************************************************
932 * EP93xx Security peripheral
933 *************************************************************************/
934
935/*
936 * The Maverick Key is 256 bits of micro fuses blown at the factory during
937 * manufacturing to uniquely identify a part.
938 *
939 * See: http://arm.cirrus.com/forum/viewtopic.php?t=486&highlight=maverick+key
940 */
941#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x))
942#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400)
943#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410)
944#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440)
945#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450)
946#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460)
947#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500)
948#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504)
949#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520)
950#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524)
951#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700)
952#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704)
953#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708)
954#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c)
955
956static char ep93xx_soc_id[33];
957
958static const char __init *ep93xx_get_soc_id(void)
e7736d47 959{
b19e11fb
HS		 960 unsigned int id, id2, id3, id4, id5;
961
962 if (__raw_readl(EP93XX_SECURITY_UNIQVAL) != 1)
963 return "bad Hamming code";
964
965 id = __raw_readl(EP93XX_SECURITY_UNIQID);
966 id2 = __raw_readl(EP93XX_SECURITY_UNIQID2);
967 id3 = __raw_readl(EP93XX_SECURITY_UNIQID3);
968 id4 = __raw_readl(EP93XX_SECURITY_UNIQID4);
969 id5 = __raw_readl(EP93XX_SECURITY_UNIQID5);
970
971 if (id != id2)
972 return "invalid";
973
974 snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id),
975 "%08x%08x%08x%08x", id2, id3, id4, id5);
976
977 return ep93xx_soc_id;
978}
979
980static const char __init *ep93xx_get_soc_rev(void)
981{
982 int rev = ep93xx_chip_revision();
983
984 switch (rev) {
985 case EP93XX_CHIP_REV_D0:
986 return "D0";
987 case EP93XX_CHIP_REV_D1:
988 return "D1";
989 case EP93XX_CHIP_REV_E0:
990 return "E0";
991 case EP93XX_CHIP_REV_E1:
992 return "E1";
993 case EP93XX_CHIP_REV_E2:
994 return "E2";
995 default:
996 return "unknown";
997 }
998}
999
1000static const char __init *ep93xx_get_machine_name(void)
1001{
1002 return kasprintf(GFP_KERNEL,"%s", machine_desc->name);
1003}
1004
1005static struct device __init *ep93xx_init_soc(void)
1006{
1007 struct soc_device_attribute *soc_dev_attr;
1008 struct soc_device *soc_dev;
1009
1010 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
1011 if (!soc_dev_attr)
1012 return NULL;
1013
1014 soc_dev_attr->machine = ep93xx_get_machine_name();
1015 soc_dev_attr->family = "Cirrus Logic EP93xx";
1016 soc_dev_attr->revision = ep93xx_get_soc_rev();
1017 soc_dev_attr->soc_id = ep93xx_get_soc_id();
1018
1019 soc_dev = soc_device_register(soc_dev_attr);
1020 if (IS_ERR(soc_dev)) {
1021 kfree(soc_dev_attr->machine);
1022 kfree(soc_dev_attr);
1023 return NULL;
1024 }
1025
1026 return soc_device_to_device(soc_dev);
1027}
1028
1029struct device __init *ep93xx_init_devices(void)
1030{
1031 struct device *parent;
1032
02239f0a
HS		 1033 /* Disallow access to MaverickCrunch initially */
1034 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8 1035
08932d81
RM		 1036 /* Default all ports to GPIO */
1037 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
1038 EP93XX_SYSCON_DEVCFG_GONK |
1039 EP93XX_SYSCON_DEVCFG_EONIDE |
1040 EP93XX_SYSCON_DEVCFG_GONIDE |
1041 EP93XX_SYSCON_DEVCFG_HONIDE);
1042
b19e11fb
HS		 1043 parent = ep93xx_init_soc();
1044
1e4c8842
HS		 1045 /* Get the GPIO working early, other devices need it */
1046 platform_device_register(&ep93xx_gpio_device);
b685004f 1047
aee85fe8
LB		 1048 amba_device_register(&uart1_device, &iomem_resource);
1049 amba_device_register(&uart2_device, &iomem_resource);
1050 amba_device_register(&uart3_device, &iomem_resource);
41658132
LB		 1051
1052 platform_device_register(&ep93xx_rtc_device);
1f64eb37 1053 platform_device_register(&ep93xx_ohci_device);
73303d12 1054 platform_device_register(&ep93xx_wdt_device);
a1eacd79
HS		 1055
1056 gpio_led_register_device(-1, &ep93xx_led_data);
b19e11fb
HS		 1057
1058 return parent;
e7736d47 1059}
3275166e 1060
7b6d864b 1061void ep93xx_restart(enum reboot_mode mode, const char *cmd)
3275166e
RK		 1062{
1063 /*
1064 * Set then clear the SWRST bit to initiate a software reset
1065 */
1066 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1067 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
1068
1069 while (1)
1070 ;
1071}
c914283f
SG		 1072
1073void __init ep93xx_init_late(void)
1074{
1075 crunch_init();
1076}
Linux kernel - Deliverables
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