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Merge branch 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux...
[deliverable/linux.git] / arch / arm / mach-ep93xx / core.c
CommitLineData
e7736d47
LB		 1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47
LB		 7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
64d6882d
HS		 17#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
e7736d47
LB		 19#include <linux/kernel.h>
20#include <linux/init.h>
583ddafe 21#include <linux/platform_device.h>
e7736d47 22#include <linux/interrupt.h>
63890a0e 23#include <linux/dma-mapping.h>
e7736d47 24#include <linux/timex.h>
6bd4b382 25#include <linux/irq.h>
583ddafe
HS		 26#include <linux/io.h>
27#include <linux/gpio.h>
3aa7a9a3 28#include <linux/leds.h>
aee85fe8 29#include <linux/termios.h>
e7736d47 30#include <linux/amba/bus.h>
aee85fe8 31#include <linux/amba/serial.h>
16bcf78f 32#include <linux/mtd/physmap.h>
d52a26a9
HS		 33#include <linux/i2c.h>
34#include <linux/i2c-gpio.h>
4fec9978 35#include <linux/spi/spi.h>
dc28094b 36#include <linux/export.h>
9e47b8bf 37#include <linux/irqchip/arm-vic.h>
e7736d47 38
a09e64fb 39#include <mach/hardware.h>
a3b29245
AB		 40#include <linux/platform_data/video-ep93xx.h>
41#include <linux/platform_data/keypad-ep93xx.h>
42#include <linux/platform_data/spi-ep93xx.h>
bd5f12a2 43#include <mach/gpio-ep93xx.h>
e7736d47
LB		 44
45#include <asm/mach/map.h>
46#include <asm/mach/time.h>
e7736d47 47
a05baf33 48#include "soc.h"
e7736d47
LB		 49
50/*************************************************************************
51 * Static I/O mappings that are needed for all EP93xx platforms
52 *************************************************************************/
53static struct map_desc ep93xx_io_desc[] __initdata = {
54 {
55 .virtual = EP93XX_AHB_VIRT_BASE,
56 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
57 .length = EP93XX_AHB_SIZE,
58 .type = MT_DEVICE,
59 }, {
60 .virtual = EP93XX_APB_VIRT_BASE,
61 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
62 .length = EP93XX_APB_SIZE,
63 .type = MT_DEVICE,
64 },
65};
66
67void __init ep93xx_map_io(void)
68{
69 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
70}
71
72
73/*************************************************************************
74 * Timer handling for EP93xx
75 *************************************************************************
76 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
77 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
78 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
79 * is free-running, and can't generate interrupts.
80 *
81 * The 508 kHz timers are ideal for use for the timer interrupt, as the
82 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
83 * bit timers (timer 1) since we don't need more than 16 bits of reload
84 * value as long as HZ >= 8.
85 *
86 * The higher clock rate of timer 4 makes it a better choice than the
87 * other timers for use in gettimeoffset(), while the fact that it can't
88 * generate interrupts means we don't have to worry about not being able
89 * to use this timer for something else. We also use timer 4 for keeping
90 * track of lost jiffies.
91 */
1587a373
HS		 92#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
93#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
94#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
95#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
96#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
97#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
98#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
99#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
100#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
101#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
102#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
103#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
104#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
105#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
106#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
107#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
108#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
109#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
110#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
111
112#define EP93XX_TIMER123_CLOCK 508469
113#define EP93XX_TIMER4_CLOCK 983040
114
115#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
af1057ab 116#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
e7736d47 117
1587a373
HS		 118static unsigned int last_jiffy_time;
119
d5565f76 120static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47 121{
1587a373 122 /* Writing any value clears the timer interrupt */
e7736d47 123 __raw_writel(1, EP93XX_TIMER1_CLEAR);
1587a373
HS		 124
125 /* Recover lost jiffies */
f869afab
LB		 126 while ((signed long)
127 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47
LB		 128 >= TIMER4_TICKS_PER_JIFFY) {
129 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68 130 timer_tick();
e7736d47
LB		 131 }
132
e7736d47
LB		 133 return IRQ_HANDLED;
134}
135
136static struct irqaction ep93xx_timer_irq = {
137 .name = "ep93xx timer",
b30fabad 138 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
e7736d47
LB		 139 .handler = ep93xx_timer_interrupt,
140};
141
23c197b7
SW		 142static u32 ep93xx_gettimeoffset(void)
143{
144 int offset;
145
146 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
147
148 /*
149 * Timer 4 is based on a 983.04 kHz reference clock,
150 * so dividing by 983040 gives the fraction of a second,
151 * so dividing by 0.983040 converts to uS.
152 * Refactor the calculation to avoid overflow.
153 * Finally, multiply by 1000 to give nS.
154 */
155 return (offset + (53 * offset / 3072)) * 1000;
156}
157
6bb27d73 158void __init ep93xx_timer_init(void)
e7736d47 159{
1587a373
HS		 160 u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
161 EP93XX_TIMER123_CONTROL_CLKSEL;
162
23c197b7
SW		 163 arch_gettimeoffset = ep93xx_gettimeoffset;
164
e7736d47 165 /* Enable periodic HZ timer. */
1587a373
HS		 166 __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
167 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
168 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
169 EP93XX_TIMER1_CONTROL);
e7736d47
LB		 170
171 /* Enable lost jiffy timer. */
1587a373
HS		 172 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
173 EP93XX_TIMER4_VALUE_HIGH);
e7736d47
LB		 174
175 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
176}
177
e7736d47
LB		 178
179/*************************************************************************
180 * EP93xx IRQ handling
181 *************************************************************************/
182void __init ep93xx_init_irq(void)
183{
5396730b
HS		 184 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
185 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
e7736d47
LB		 186}
187
188
02239f0a
HS		 189/*************************************************************************
190 * EP93xx System Controller Software Locked register handling
191 *************************************************************************/
192
193/*
194 * syscon_swlock prevents anything else from writing to the syscon
195 * block while a software locked register is being written.
196 */
197static DEFINE_SPINLOCK(syscon_swlock);
198
fbeeea53 199void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
02239f0a
HS		 200{
201 unsigned long flags;
202
203 spin_lock_irqsave(&syscon_swlock, flags);
204
205 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
206 __raw_writel(val, reg);
207
208 spin_unlock_irqrestore(&syscon_swlock, flags);
209}
02239f0a
HS		 210
211void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
212{
213 unsigned long flags;
214 unsigned int val;
215
216 spin_lock_irqsave(&syscon_swlock, flags);
217
218 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
02239f0a 219 val &= ~clear_bits;
a0fb007b 220 val |= set_bits;
02239f0a
HS		 221 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
222 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
223
224 spin_unlock_irqrestore(&syscon_swlock, flags);
225}
02239f0a 226
99e6a23a
MW		 227/**
228 * ep93xx_chip_revision() - returns the EP93xx chip revision
229 *
230 * See <mach/platform.h> for more information.
231 */
232unsigned int ep93xx_chip_revision(void)
233{
234 unsigned int v;
235
236 v = __raw_readl(EP93XX_SYSCON_SYSCFG);
237 v &= EP93XX_SYSCON_SYSCFG_REV_MASK;
238 v >>= EP93XX_SYSCON_SYSCFG_REV_SHIFT;
239 return v;
240}
02239f0a 241
1e4c8842
HS		 242/*************************************************************************
243 * EP93xx GPIO
244 *************************************************************************/
245static struct resource ep93xx_gpio_resource[] = {
ede55aaa 246 DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
1e4c8842
HS		 247};
248
249static struct platform_device ep93xx_gpio_device = {
250 .name = "gpio-ep93xx",
251 .id = -1,
252 .num_resources = ARRAY_SIZE(ep93xx_gpio_resource),
253 .resource = ep93xx_gpio_resource,
254};
255
e7736d47
LB		 256/*************************************************************************
257 * EP93xx peripheral handling
258 *************************************************************************/
aee85fe8
LB		 259#define EP93XX_UART_MCR_OFFSET (0x0100)
260
261static void ep93xx_uart_set_mctrl(struct amba_device *dev,
262 void __iomem *base, unsigned int mctrl)
263{
264 unsigned int mcr;
265
266 mcr = 0;
186dcaa4 267 if (mctrl & TIOCM_RTS)
aee85fe8 268 mcr |= 2;
186dcaa4 269 if (mctrl & TIOCM_DTR)
aee85fe8
LB		 270 mcr |= 1;
271
272 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
273}
274
275static struct amba_pl010_data ep93xx_uart_data = {
276 .set_mctrl = ep93xx_uart_set_mctrl,
277};
278
0b26051b
RK		 279static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE,
280 { IRQ_EP93XX_UART1 }, &ep93xx_uart_data);
aee85fe8 281
0b26051b
RK		 282static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE,
283 { IRQ_EP93XX_UART2 }, &ep93xx_uart_data);
aee85fe8 284
0b26051b
RK		 285static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
286 { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
41658132 287
38f7b009 288static struct resource ep93xx_rtc_resource[] = {
ede55aaa 289 DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
38f7b009
HS		 290};
291
41658132 292static struct platform_device ep93xx_rtc_device = {
38f7b009
HS		 293 .name = "ep93xx-rtc",
294 .id = -1,
295 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
296 .resource = ep93xx_rtc_resource,
41658132
LB		 297};
298
299
1f64eb37 300static struct resource ep93xx_ohci_resources[] = {
ede55aaa
HS		 301 DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
302 DEFINE_RES_IRQ(IRQ_EP93XX_USB),
1f64eb37
LB		 303};
304
63890a0e 305
1f64eb37
LB		 306static struct platform_device ep93xx_ohci_device = {
307 .name = "ep93xx-ohci",
308 .id = -1,
309 .dev = {
63890a0e
MK		 310 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
311 .coherent_dma_mask = DMA_BIT_MASK(32),
1f64eb37
LB		 312 },
313 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
314 .resource = ep93xx_ohci_resources,
315};
316
b370e082 317
16bcf78f
HS		 318/*************************************************************************
319 * EP93xx physmap'ed flash
320 *************************************************************************/
321static struct physmap_flash_data ep93xx_flash_data;
322
323static struct resource ep93xx_flash_resource = {
324 .flags = IORESOURCE_MEM,
325};
326
327static struct platform_device ep93xx_flash = {
328 .name = "physmap-flash",
329 .id = 0,
330 .dev = {
331 .platform_data = &ep93xx_flash_data,
332 },
333 .num_resources = 1,
334 .resource = &ep93xx_flash_resource,
335};
336
337/**
338 * ep93xx_register_flash() - Register the external flash device.
339 * @width: bank width in octets
340 * @start: resource start address
341 * @size: resource size
342 */
343void __init ep93xx_register_flash(unsigned int width,
344 resource_size_t start, resource_size_t size)
345{
346 ep93xx_flash_data.width = width;
347
348 ep93xx_flash_resource.start = start;
349 ep93xx_flash_resource.end = start + size - 1;
350
351 platform_device_register(&ep93xx_flash);
352}
353
354
b370e082
HS		 355/*************************************************************************
356 * EP93xx ethernet peripheral handling
357 *************************************************************************/
a0a08fdc
HS		 358static struct ep93xx_eth_data ep93xx_eth_data;
359
360static struct resource ep93xx_eth_resource[] = {
ede55aaa 361 DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
011b2e84 362 DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
a0a08fdc
HS		 363};
364
fa70cf47
MW		 365static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
366
a0a08fdc
HS		 367static struct platform_device ep93xx_eth_device = {
368 .name = "ep93xx-eth",
369 .id = -1,
370 .dev = {
fa70cf47
MW		 371 .platform_data = &ep93xx_eth_data,
372 .coherent_dma_mask = DMA_BIT_MASK(32),
373 .dma_mask = &ep93xx_eth_dma_mask,
a0a08fdc
HS		 374 },
375 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
376 .resource = ep93xx_eth_resource,
377};
378
b370e082
HS		 379/**
380 * ep93xx_register_eth - Register the built-in ethernet platform device.
381 * @data: platform specific ethernet configuration (__initdata)
382 * @copy_addr: flag indicating that the MAC address should be copied
383 * from the IndAd registers (as programmed by the bootloader)
384 */
a0a08fdc
HS		 385void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
386{
5b1c3c85
HS		 387 if (copy_addr)
388 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
a0a08fdc
HS		 389
390 ep93xx_eth_data = *data;
391 platform_device_register(&ep93xx_eth_device);
392}
393
6531a991
HS		 394
395/*************************************************************************
396 * EP93xx i2c peripheral handling
397 *************************************************************************/
398static struct i2c_gpio_platform_data ep93xx_i2c_data;
d52a26a9
HS		 399
400static struct platform_device ep93xx_i2c_device = {
b370e082
HS		 401 .name = "i2c-gpio",
402 .id = 0,
403 .dev = {
404 .platform_data = &ep93xx_i2c_data,
405 },
d52a26a9
HS		 406};
407
b370e082
HS		 408/**
409 * ep93xx_register_i2c - Register the i2c platform device.
410 * @data: platform specific i2c-gpio configuration (__initdata)
411 * @devices: platform specific i2c bus device information (__initdata)
412 * @num: the number of devices on the i2c bus
413 */
6531a991
HS		 414void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
415 struct i2c_board_info *devices, int num)
d52a26a9 416{
6531a991
HS		 417 /*
418 * Set the EEPROM interface pin drive type control.
419 * Defines the driver type for the EECLK and EEDAT pins as either
420 * open drain, which will require an external pull-up, or a normal
421 * CMOS driver.
422 */
423 if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
64d6882d 424 pr_warning("sda != EEDAT, open drain has no effect\n");
6531a991 425 if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
64d6882d 426 pr_warning("scl != EECLK, open drain has no effect\n");
6531a991
HS		 427
428 __raw_writel((data->sda_is_open_drain << 1) |
429 (data->scl_is_open_drain << 0),
430 EP93XX_GPIO_EEDRIVE);
431
432 ep93xx_i2c_data = *data;
d52a26a9
HS		 433 i2c_register_board_info(0, devices, num);
434 platform_device_register(&ep93xx_i2c_device);
435}
436
4fec9978
MW		 437/*************************************************************************
438 * EP93xx SPI peripheral handling
439 *************************************************************************/
440static struct ep93xx_spi_info ep93xx_spi_master_data;
441
442static struct resource ep93xx_spi_resources[] = {
ede55aaa
HS		 443 DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
444 DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
4fec9978
MW		 445};
446
626a96db
MW		 447static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
448
4fec9978
MW		 449static struct platform_device ep93xx_spi_device = {
450 .name = "ep93xx-spi",
451 .id = 0,
452 .dev = {
626a96db
MW		 453 .platform_data = &ep93xx_spi_master_data,
454 .coherent_dma_mask = DMA_BIT_MASK(32),
455 .dma_mask = &ep93xx_spi_dma_mask,
4fec9978
MW		 456 },
457 .num_resources = ARRAY_SIZE(ep93xx_spi_resources),
458 .resource = ep93xx_spi_resources,
459};
460
461/**
462 * ep93xx_register_spi() - registers spi platform device
463 * @info: ep93xx board specific spi master info (__initdata)
464 * @devices: SPI devices to register (__initdata)
465 * @num: number of SPI devices to register
466 *
467 * This function registers platform device for the EP93xx SPI controller and
468 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
469 */
470void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
471 struct spi_board_info *devices, int num)
472{
473 /*
474 * When SPI is used, we need to make sure that I2S is muxed off from
475 * SPI pins.
476 */
477 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP);
478
479 ep93xx_spi_master_data = *info;
480 spi_register_board_info(devices, num);
481 platform_device_register(&ep93xx_spi_device);
482}
3aa7a9a3
HS		 483
484/*************************************************************************
485 * EP93xx LEDs
486 *************************************************************************/
a1eacd79 487static const struct gpio_led ep93xx_led_pins[] __initconst = {
3aa7a9a3 488 {
b370e082
HS		 489 .name = "platform:grled",
490 .gpio = EP93XX_GPIO_LINE_GRLED,
3aa7a9a3 491 }, {
b370e082
HS		 492 .name = "platform:rdled",
493 .gpio = EP93XX_GPIO_LINE_RDLED,
3aa7a9a3
HS		 494 },
495};
496
a1eacd79 497static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
3aa7a9a3
HS		 498 .num_leds = ARRAY_SIZE(ep93xx_led_pins),
499 .leds = ep93xx_led_pins,
500};
501
ef12379f
HS		 502/*************************************************************************
503 * EP93xx pwm peripheral handling
504 *************************************************************************/
505static struct resource ep93xx_pwm0_resource[] = {
ede55aaa 506 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
ef12379f
HS		 507};
508
509static struct platform_device ep93xx_pwm0_device = {
510 .name = "ep93xx-pwm",
511 .id = 0,
512 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
513 .resource = ep93xx_pwm0_resource,
514};
515
516static struct resource ep93xx_pwm1_resource[] = {
ede55aaa 517 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
ef12379f
HS		 518};
519
520static struct platform_device ep93xx_pwm1_device = {
521 .name = "ep93xx-pwm",
522 .id = 1,
523 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
524 .resource = ep93xx_pwm1_resource,
525};
526
527void __init ep93xx_register_pwm(int pwm0, int pwm1)
528{
529 if (pwm0)
530 platform_device_register(&ep93xx_pwm0_device);
531
532 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
533 if (pwm1)
534 platform_device_register(&ep93xx_pwm1_device);
535}
536
537int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
538{
539 int err;
540
541 if (pdev->id == 0) {
542 err = 0;
543 } else if (pdev->id == 1) {
544 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
545 dev_name(&pdev->dev));
546 if (err)
547 return err;
548 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
549 if (err)
550 goto fail;
551
552 /* PWM 1 output on EGPIO[14] */
553 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
554 } else {
555 err = -ENODEV;
556 }
557
558 return err;
559
560fail:
561 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
562 return err;
563}
564EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
565
566void ep93xx_pwm_release_gpio(struct platform_device *pdev)
567{
568 if (pdev->id == 1) {
569 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
570 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
571
572 /* EGPIO[14] used for GPIO */
573 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
574 }
575}
576EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
577
578
c6012189
RM		 579/*************************************************************************
580 * EP93xx video peripheral handling
581 *************************************************************************/
582static struct ep93xxfb_mach_info ep93xxfb_data;
583
584static struct resource ep93xx_fb_resource[] = {
ede55aaa 585 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
c6012189
RM		 586};
587
588static struct platform_device ep93xx_fb_device = {
589 .name = "ep93xx-fb",
590 .id = -1,
591 .dev = {
b370e082 592 .platform_data = &ep93xxfb_data,
c6012189
RM		 593 .coherent_dma_mask = DMA_BIT_MASK(32),
594 .dma_mask = &ep93xx_fb_device.dev.coherent_dma_mask,
595 },
596 .num_resources = ARRAY_SIZE(ep93xx_fb_resource),
597 .resource = ep93xx_fb_resource,
598};
599
0fd19580
RM		 600/* The backlight use a single register in the framebuffer's register space */
601#define EP93XX_RASTER_REG_BRIGHTNESS 0x20
602
603static struct resource ep93xx_bl_resources[] = {
604 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE +
605 EP93XX_RASTER_REG_BRIGHTNESS, 0x04),
606};
607
6ea4b741
HS		 608static struct platform_device ep93xx_bl_device = {
609 .name = "ep93xx-bl",
610 .id = -1,
0fd19580
RM		 611 .num_resources = ARRAY_SIZE(ep93xx_bl_resources),
612 .resource = ep93xx_bl_resources,
6ea4b741
HS		 613};
614
b370e082
HS		 615/**
616 * ep93xx_register_fb - Register the framebuffer platform device.
617 * @data: platform specific framebuffer configuration (__initdata)
618 */
c6012189
RM		 619void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
620{
621 ep93xxfb_data = *data;
622 platform_device_register(&ep93xx_fb_device);
6ea4b741 623 platform_device_register(&ep93xx_bl_device);
c6012189
RM		 624}
625
12f56c68
HS		 626
627/*************************************************************************
628 * EP93xx matrix keypad peripheral handling
629 *************************************************************************/
b370e082
HS		 630static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
631
12f56c68 632static struct resource ep93xx_keypad_resource[] = {
ede55aaa
HS		 633 DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
634 DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
12f56c68
HS		 635};
636
637static struct platform_device ep93xx_keypad_device = {
b370e082
HS		 638 .name = "ep93xx-keypad",
639 .id = -1,
640 .dev = {
641 .platform_data = &ep93xx_keypad_data,
642 },
643 .num_resources = ARRAY_SIZE(ep93xx_keypad_resource),
644 .resource = ep93xx_keypad_resource,
12f56c68
HS		 645};
646
b370e082
HS		 647/**
648 * ep93xx_register_keypad - Register the keypad platform device.
649 * @data: platform specific keypad configuration (__initdata)
650 */
12f56c68
HS		 651void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
652{
b370e082 653 ep93xx_keypad_data = *data;
12f56c68
HS		 654 platform_device_register(&ep93xx_keypad_device);
655}
656
657int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
658{
659 int err;
660 int i;
661
662 for (i = 0; i < 8; i++) {
663 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
664 if (err)
665 goto fail_gpio_c;
666 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
667 if (err)
668 goto fail_gpio_d;
669 }
670
671 /* Enable the keypad controller; GPIO ports C and D used for keypad */
672 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
673 EP93XX_SYSCON_DEVCFG_GONK);
674
675 return 0;
676
677fail_gpio_d:
678 gpio_free(EP93XX_GPIO_LINE_C(i));
679fail_gpio_c:
5528a846 680 for (--i; i >= 0; --i) {
12f56c68
HS		 681 gpio_free(EP93XX_GPIO_LINE_C(i));
682 gpio_free(EP93XX_GPIO_LINE_D(i));
683 }
684 return err;
685}
686EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
687
688void ep93xx_keypad_release_gpio(struct platform_device *pdev)
689{
690 int i;
691
692 for (i = 0; i < 8; i++) {
693 gpio_free(EP93XX_GPIO_LINE_C(i));
694 gpio_free(EP93XX_GPIO_LINE_D(i));
695 }
696
697 /* Disable the keypad controller; GPIO ports C and D used for GPIO */
698 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
699 EP93XX_SYSCON_DEVCFG_GONK);
700}
701EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
702
ed67ea82
RM		 703/*************************************************************************
704 * EP93xx I2S audio peripheral handling
705 *************************************************************************/
706static struct resource ep93xx_i2s_resource[] = {
ede55aaa 707 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
ed67ea82
RM		 708};
709
710static struct platform_device ep93xx_i2s_device = {
711 .name = "ep93xx-i2s",
712 .id = -1,
713 .num_resources = ARRAY_SIZE(ep93xx_i2s_resource),
714 .resource = ep93xx_i2s_resource,
715};
716
f0fba2ad
LG		 717static struct platform_device ep93xx_pcm_device = {
718 .name = "ep93xx-pcm-audio",
719 .id = -1,
720};
721
ed67ea82
RM		 722void __init ep93xx_register_i2s(void)
723{
724 platform_device_register(&ep93xx_i2s_device);
f0fba2ad 725 platform_device_register(&ep93xx_pcm_device);
ed67ea82
RM		 726}
727
728#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
729 EP93XX_SYSCON_DEVCFG_I2SONAC97)
730
731#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
732 EP93XX_SYSCON_I2SCLKDIV_SPOL)
733
f15855bf 734int ep93xx_i2s_acquire(void)
ed67ea82
RM		 735{
736 unsigned val;
737
f15855bf
RM		 738 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97,
739 EP93XX_SYSCON_DEVCFG_I2S_MASK);
ed67ea82
RM		 740
741 /*
742 * This is potentially racy with the clock api for i2s_mclk, sclk and
743 * lrclk. Since the i2s driver is the only user of those clocks we
744 * rely on it to prevent parallel use of this function and the
745 * clock api for the i2s clocks.
746 */
747 val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
748 val &= ~EP93XX_I2SCLKDIV_MASK;
f15855bf 749 val |= EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL;
ed67ea82
RM		 750 ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
751
752 return 0;
753}
754EXPORT_SYMBOL(ep93xx_i2s_acquire);
755
756void ep93xx_i2s_release(void)
757{
758 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
759}
760EXPORT_SYMBOL(ep93xx_i2s_release);
12f56c68 761
534bc7fa
MW		 762/*************************************************************************
763 * EP93xx AC97 audio peripheral handling
764 *************************************************************************/
765static struct resource ep93xx_ac97_resources[] = {
ede55aaa
HS		 766 DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
767 DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
534bc7fa
MW		 768};
769
770static struct platform_device ep93xx_ac97_device = {
771 .name = "ep93xx-ac97",
772 .id = -1,
773 .num_resources = ARRAY_SIZE(ep93xx_ac97_resources),
774 .resource = ep93xx_ac97_resources,
775};
776
777void __init ep93xx_register_ac97(void)
778{
779 /*
780 * Make sure that the AC97 pins are not used by I2S.
781 */
782 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97);
783
784 platform_device_register(&ep93xx_ac97_device);
785 platform_device_register(&ep93xx_pcm_device);
786}
787
73303d12
HS		 788/*************************************************************************
789 * EP93xx Watchdog
790 *************************************************************************/
791static struct resource ep93xx_wdt_resources[] = {
792 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08),
793};
794
795static struct platform_device ep93xx_wdt_device = {
796 .name = "ep93xx-wdt",
797 .id = -1,
798 .num_resources = ARRAY_SIZE(ep93xx_wdt_resources),
799 .resource = ep93xx_wdt_resources,
800};
801
eb774a09
RP		 802/*************************************************************************
803 * EP93xx IDE
804 *************************************************************************/
805static struct resource ep93xx_ide_resources[] = {
806 DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
807 DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
808};
809
810static struct platform_device ep93xx_ide_device = {
811 .name = "ep93xx-ide",
812 .id = -1,
813 .dev = {
814 .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask,
815 .coherent_dma_mask = DMA_BIT_MASK(32),
816 },
817 .num_resources = ARRAY_SIZE(ep93xx_ide_resources),
818 .resource = ep93xx_ide_resources,
819};
820
821void __init ep93xx_register_ide(void)
822{
823 platform_device_register(&ep93xx_ide_device);
824}
825
826int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
827{
828 int err;
829 int i;
830
831 err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
832 if (err)
833 return err;
834 err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
835 if (err)
836 goto fail_egpio15;
837 for (i = 2; i < 8; i++) {
838 err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
839 if (err)
840 goto fail_gpio_e;
841 }
842 for (i = 4; i < 8; i++) {
843 err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
844 if (err)
845 goto fail_gpio_g;
846 }
847 for (i = 0; i < 8; i++) {
848 err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
849 if (err)
850 goto fail_gpio_h;
851 }
852
853 /* GPIO ports E[7:2], G[7:4] and H used by IDE */
854 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
855 EP93XX_SYSCON_DEVCFG_GONIDE |
856 EP93XX_SYSCON_DEVCFG_HONIDE);
857 return 0;
858
859fail_gpio_h:
860 for (--i; i >= 0; --i)
861 gpio_free(EP93XX_GPIO_LINE_H(i));
862 i = 8;
863fail_gpio_g:
864 for (--i; i >= 4; --i)
865 gpio_free(EP93XX_GPIO_LINE_G(i));
866 i = 8;
867fail_gpio_e:
868 for (--i; i >= 2; --i)
869 gpio_free(EP93XX_GPIO_LINE_E(i));
870 gpio_free(EP93XX_GPIO_LINE_EGPIO15);
871fail_egpio15:
872 gpio_free(EP93XX_GPIO_LINE_EGPIO2);
873 return err;
874}
875EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
876
877void ep93xx_ide_release_gpio(struct platform_device *pdev)
878{
879 int i;
880
881 for (i = 2; i < 8; i++)
882 gpio_free(EP93XX_GPIO_LINE_E(i));
883 for (i = 4; i < 8; i++)
884 gpio_free(EP93XX_GPIO_LINE_G(i));
885 for (i = 0; i < 8; i++)
886 gpio_free(EP93XX_GPIO_LINE_H(i));
887 gpio_free(EP93XX_GPIO_LINE_EGPIO15);
888 gpio_free(EP93XX_GPIO_LINE_EGPIO2);
889
890
891 /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
892 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
893 EP93XX_SYSCON_DEVCFG_GONIDE |
894 EP93XX_SYSCON_DEVCFG_HONIDE);
895}
896EXPORT_SYMBOL(ep93xx_ide_release_gpio);
897
e7736d47
LB		 898void __init ep93xx_init_devices(void)
899{
02239f0a
HS		 900 /* Disallow access to MaverickCrunch initially */
901 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8 902
08932d81
RM		 903 /* Default all ports to GPIO */
904 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
905 EP93XX_SYSCON_DEVCFG_GONK |
906 EP93XX_SYSCON_DEVCFG_EONIDE |
907 EP93XX_SYSCON_DEVCFG_GONIDE |
908 EP93XX_SYSCON_DEVCFG_HONIDE);
909
1e4c8842
HS		 910 /* Get the GPIO working early, other devices need it */
911 platform_device_register(&ep93xx_gpio_device);
b685004f 912
aee85fe8
LB		 913 amba_device_register(&uart1_device, &iomem_resource);
914 amba_device_register(&uart2_device, &iomem_resource);
915 amba_device_register(&uart3_device, &iomem_resource);
41658132
LB		 916
917 platform_device_register(&ep93xx_rtc_device);
1f64eb37 918 platform_device_register(&ep93xx_ohci_device);
73303d12 919 platform_device_register(&ep93xx_wdt_device);
a1eacd79
HS		 920
921 gpio_led_register_device(-1, &ep93xx_led_data);
e7736d47 922}
3275166e
RK		 923
924void ep93xx_restart(char mode, const char *cmd)
925{
926 /*
927 * Set then clear the SWRST bit to initiate a software reset
928 */
929 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
930 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
931
932 while (1)
933 ;
934}
c914283f
SG		 935
936void __init ep93xx_init_late(void)
937{
938 crunch_init();
939}
Linux kernel - Deliverables
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