[deliverable/linux.git] / arch / arm / mach-ep93xx / core.c

/*
 * arch/arm/mach-ep93xx/core.c
 * Core routines for Cirrus EP93xx chips.
 *
 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
 *
 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
 * role in the ep93xx linux community.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/bitops.h>
#include <linux/serial_8250.h>
#include <linux/serial_core.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/delay.h>
#include <linux/termios.h>
#include <linux/amba/bus.h>
#include <linux/amba/serial.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/tlbflush.h>
#include <asm/pgtable.h>

#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <mach/gpio.h>

#include <asm/hardware/vic.h>


/*************************************************************************
 * Static I/O mappings that are needed for all EP93xx platforms
 *************************************************************************/
static struct map_desc ep93xx_io_desc[] __initdata = {
	{
		.virtual	= EP93XX_AHB_VIRT_BASE,
		.pfn		= __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
		.length		= EP93XX_AHB_SIZE,
		.type		= MT_DEVICE,
	}, {
		.virtual	= EP93XX_APB_VIRT_BASE,
		.pfn		= __phys_to_pfn(EP93XX_APB_PHYS_BASE),
		.length		= EP93XX_APB_SIZE,
		.type		= MT_DEVICE,
	},
};

void __init ep93xx_map_io(void)
{
	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
}


/*************************************************************************
 * Timer handling for EP93xx
 *************************************************************************
 * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
 * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
 * is free-running, and can't generate interrupts.
 *
 * The 508 kHz timers are ideal for use for the timer interrupt, as the
 * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
 * bit timers (timer 1) since we don't need more than 16 bits of reload
 * value as long as HZ >= 8.
 *
 * The higher clock rate of timer 4 makes it a better choice than the
 * other timers for use in gettimeoffset(), while the fact that it can't
 * generate interrupts means we don't have to worry about not being able
 * to use this timer for something else.  We also use timer 4 for keeping
 * track of lost jiffies.
 */
static unsigned int last_jiffy_time;

#define TIMER4_TICKS_PER_JIFFY		((CLOCK_TICK_RATE + (HZ/2)) / HZ)

static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
{
	__raw_writel(1, EP93XX_TIMER1_CLEAR);
	while ((signed long)
		(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
						>= TIMER4_TICKS_PER_JIFFY) {
		last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
		timer_tick();
	}

	return IRQ_HANDLED;
}

static struct irqaction ep93xx_timer_irq = {
	.name		= "ep93xx timer",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= ep93xx_timer_interrupt,
};

static void __init ep93xx_timer_init(void)
{
	/* Enable periodic HZ timer.  */
	__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
	__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
	__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);

	/* Enable lost jiffy timer.  */
	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);

	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
}

static unsigned long ep93xx_gettimeoffset(void)
{
	int offset;

	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;

	/* Calculate (1000000 / 983040) * offset.  */
	return offset + (53 * offset / 3072);
}

struct sys_timer ep93xx_timer = {
	.init		= ep93xx_timer_init,
	.offset		= ep93xx_gettimeoffset,
};


/*************************************************************************
 * GPIO handling for EP93xx
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

void ep93xx_gpio_update_int_params(unsigned port)
{
	BUG_ON(port > 2);

	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));

	__raw_writeb(gpio_int_type2[port],
		EP93XX_GPIO_REG(int_type2_register_offset[port]));

	__raw_writeb(gpio_int_type1[port],
		EP93XX_GPIO_REG(int_type1_register_offset[port]));

	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
		EP93XX_GPIO_REG(int_en_register_offset[port]));
}

void ep93xx_gpio_int_mask(unsigned line)
{
	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
}

void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	__raw_writeb(gpio_int_debounce[port],
		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}
EXPORT_SYMBOL(ep93xx_gpio_int_debounce);

/*************************************************************************
 * EP93xx IRQ handling
 *************************************************************************/
static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned char status;
	int i;

	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}

	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
			desc = irq_desc + gpio_irq;
			generic_handle_irq(gpio_irq);
		}
	}
}

static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	 */
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;

	generic_handle_irq(gpio_irq);
}

static void ep93xx_gpio_irq_ack(unsigned int irq)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(port);
	}

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(port);

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask(unsigned int irq)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;

	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	ep93xx_gpio_update_int_params(port);
}

static void ep93xx_gpio_irq_unmask(unsigned int irq)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;

	gpio_int_unmasked[port] |= 1 << (line & 7);
	ep93xx_gpio_update_int_params(port);
}


/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
{
	struct irq_desc *desc = irq_desc + irq;
	const int gpio = irq_to_gpio(irq);
	const int port = gpio >> 3;
	const int port_mask = 1 << (gpio & 7);

	gpio_direction_input(gpio);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		desc->handle_irq = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		desc->handle_irq = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		desc->handle_irq = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		desc->handle_irq = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gpio_get_value(gpio))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		desc->handle_irq = handle_edge_irq;
		break;
	default:
		pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
		       type, gpio);
		return -EINVAL;
	}

	gpio_int_enabled[port] |= port_mask;

	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	desc->status |= type & IRQ_TYPE_SENSE_MASK;

	ep93xx_gpio_update_int_params(port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.ack		= ep93xx_gpio_irq_ack,
	.mask_ack	= ep93xx_gpio_irq_mask_ack,
	.mask		= ep93xx_gpio_irq_mask,
	.unmask		= ep93xx_gpio_irq_unmask,
	.set_type	= ep93xx_gpio_irq_type,
};


void __init ep93xx_init_irq(void)
{
	int gpio_irq;

	vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
	vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);

	for (gpio_irq = gpio_to_irq(0);
	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
		set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
		set_irq_handler(gpio_irq, handle_level_irq);
		set_irq_flags(gpio_irq, IRQF_VALID);
	}

	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
}


/*************************************************************************
 * EP93xx System Controller Software Locked register handling
 *************************************************************************/

/*
 * syscon_swlock prevents anything else from writing to the syscon
 * block while a software locked register is being written.
 */
static DEFINE_SPINLOCK(syscon_swlock);

void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg)
{
	unsigned long flags;

	spin_lock_irqsave(&syscon_swlock, flags);

	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
	__raw_writel(val, reg);

	spin_unlock_irqrestore(&syscon_swlock, flags);
}
EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);

void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
{
	unsigned long flags;
	unsigned int val;

	spin_lock_irqsave(&syscon_swlock, flags);

	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
	val |= set_bits;
	val &= ~clear_bits;
	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
	__raw_writel(val, EP93XX_SYSCON_DEVCFG);

	spin_unlock_irqrestore(&syscon_swlock, flags);
}
EXPORT_SYMBOL(ep93xx_devcfg_set_clear);


/*************************************************************************
 * EP93xx peripheral handling
 *************************************************************************/
#define EP93XX_UART_MCR_OFFSET		(0x0100)

static void ep93xx_uart_set_mctrl(struct amba_device *dev,
				  void __iomem *base, unsigned int mctrl)
{
	unsigned int mcr;

	mcr = 0;
	if (!(mctrl & TIOCM_RTS))
		mcr |= 2;
	if (!(mctrl & TIOCM_DTR))
		mcr |= 1;

	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
}

static struct amba_pl010_data ep93xx_uart_data = {
	.set_mctrl	= ep93xx_uart_set_mctrl,
};

static struct amba_device uart1_device = {
	.dev		= {
		.init_name	= "apb:uart1",
		.platform_data	= &ep93xx_uart_data,
	},
	.res		= {
		.start	= EP93XX_UART1_PHYS_BASE,
		.end	= EP93XX_UART1_PHYS_BASE + 0x0fff,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_EP93XX_UART1, NO_IRQ },
	.periphid	= 0x00041010,
};

static struct amba_device uart2_device = {
	.dev		= {
		.init_name	= "apb:uart2",
		.platform_data	= &ep93xx_uart_data,
	},
	.res		= {
		.start	= EP93XX_UART2_PHYS_BASE,
		.end	= EP93XX_UART2_PHYS_BASE + 0x0fff,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_EP93XX_UART2, NO_IRQ },
	.periphid	= 0x00041010,
};

static struct amba_device uart3_device = {
	.dev		= {
		.init_name	= "apb:uart3",
		.platform_data	= &ep93xx_uart_data,
	},
	.res		= {
		.start	= EP93XX_UART3_PHYS_BASE,
		.end	= EP93XX_UART3_PHYS_BASE + 0x0fff,
		.flags	= IORESOURCE_MEM,
	},
	.irq		= { IRQ_EP93XX_UART3, NO_IRQ },
	.periphid	= 0x00041010,
};


static struct resource ep93xx_rtc_resource[] = {
	{
		.start		= EP93XX_RTC_PHYS_BASE,
		.end		= EP93XX_RTC_PHYS_BASE + 0x10c - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device ep93xx_rtc_device = {
	.name		= "ep93xx-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(ep93xx_rtc_resource),
	.resource	= ep93xx_rtc_resource,
};


static struct resource ep93xx_ohci_resources[] = {
	[0] = {
		.start	= EP93XX_USB_PHYS_BASE,
		.end	= EP93XX_USB_PHYS_BASE + 0x0fff,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_EP93XX_USB,
		.end	= IRQ_EP93XX_USB,
		.flags	= IORESOURCE_IRQ,
	},
};


static struct platform_device ep93xx_ohci_device = {
	.name		= "ep93xx-ohci",
	.id		= -1,
	.dev		= {
		.dma_mask		= &ep93xx_ohci_device.dev.coherent_dma_mask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(ep93xx_ohci_resources),
	.resource	= ep93xx_ohci_resources,
};

static struct ep93xx_eth_data ep93xx_eth_data;

static struct resource ep93xx_eth_resource[] = {
	{
		.start	= EP93XX_ETHERNET_PHYS_BASE,
		.end	= EP93XX_ETHERNET_PHYS_BASE + 0xffff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= IRQ_EP93XX_ETHERNET,
		.end	= IRQ_EP93XX_ETHERNET,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device ep93xx_eth_device = {
	.name		= "ep93xx-eth",
	.id		= -1,
	.dev		= {
		.platform_data	= &ep93xx_eth_data,
	},
	.num_resources	= ARRAY_SIZE(ep93xx_eth_resource),
	.resource	= ep93xx_eth_resource,
};

void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
{
	if (copy_addr) {
		memcpy(data->dev_addr,
			(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
	}

	ep93xx_eth_data = *data;
	platform_device_register(&ep93xx_eth_device);
}

static struct i2c_gpio_platform_data ep93xx_i2c_data = {
	.sda_pin		= EP93XX_GPIO_LINE_EEDAT,
	.sda_is_open_drain	= 0,
	.scl_pin		= EP93XX_GPIO_LINE_EECLK,
	.scl_is_open_drain	= 0,
	.udelay			= 2,
};

static struct platform_device ep93xx_i2c_device = {
	.name			= "i2c-gpio",
	.id			= 0,
	.dev.platform_data	= &ep93xx_i2c_data,
};

void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
{
	i2c_register_board_info(0, devices, num);
	platform_device_register(&ep93xx_i2c_device);
}

extern void ep93xx_gpio_init(void);

void __init ep93xx_init_devices(void)
{
	/* Disallow access to MaverickCrunch initially */
	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);

	ep93xx_gpio_init();

	amba_device_register(&uart1_device, &iomem_resource);
	amba_device_register(&uart2_device, &iomem_resource);
	amba_device_register(&uart3_device, &iomem_resource);

	platform_device_register(&ep93xx_rtc_device);
	platform_device_register(&ep93xx_ohci_device);
}
Commit	Line	Data
e7736d47 LB	1	/*
	2	* arch/arm/mach-ep93xx/core.c
	3	* Core routines for Cirrus EP93xx chips.
	4	*
	5	* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d	6	* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47 LB	7	*
	8	* Thanks go to Michael Burian and Ray Lehtiniemi for their key
	9	* role in the ep93xx linux community.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or (at
	14	* your option) any later version.
	15	*/
	16
e7736d47 LB	17	#include <linux/kernel.h>
	18	#include <linux/init.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/sched.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/serial.h>
	23	#include <linux/tty.h>
	24	#include <linux/bitops.h>
e7736d47 LB	25	#include <linux/serial_8250.h>
	26	#include <linux/serial_core.h>
	27	#include <linux/device.h>
	28	#include <linux/mm.h>
63890a0e	29	#include <linux/dma-mapping.h>
e7736d47 LB	30	#include <linux/time.h>
	31	#include <linux/timex.h>
	32	#include <linux/delay.h>
aee85fe8	33	#include <linux/termios.h>
e7736d47	34	#include <linux/amba/bus.h>
aee85fe8	35	#include <linux/amba/serial.h>
fced80c7	36	#include <linux/io.h>
d52a26a9 HS	37	#include <linux/i2c.h>
d52a26a9 HS	38	#include <linux/i2c-gpio.h>
e7736d47 LB	39
	40	#include <asm/types.h>
	41	#include <asm/setup.h>
	42	#include <asm/memory.h>
a09e64fb	43	#include <mach/hardware.h>
e7736d47 LB	44	#include <asm/irq.h>
	45	#include <asm/system.h>
	46	#include <asm/tlbflush.h>
	47	#include <asm/pgtable.h>
e7736d47 LB	48
	49	#include <asm/mach/map.h>
	50	#include <asm/mach/time.h>
	51	#include <asm/mach/irq.h>
a09e64fb	52	#include <mach/gpio.h>
e7736d47 LB	53
	54	#include <asm/hardware/vic.h>
	55
	56
	57	/*************************************************************************
	58	* Static I/O mappings that are needed for all EP93xx platforms
	59	*************************************************************************/
	60	static struct map_desc ep93xx_io_desc[] __initdata = {
	61	{
	62	.virtual = EP93XX_AHB_VIRT_BASE,
	63	.pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
	64	.length = EP93XX_AHB_SIZE,
	65	.type = MT_DEVICE,
	66	}, {
	67	.virtual = EP93XX_APB_VIRT_BASE,
	68	.pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
	69	.length = EP93XX_APB_SIZE,
	70	.type = MT_DEVICE,
	71	},
	72	};
	73
	74	void __init ep93xx_map_io(void)
	75	{
	76	iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
	77	}
	78
	79
	80	/*************************************************************************
	81	* Timer handling for EP93xx
	82	*************************************************************************
	83	* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
	84	* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
	85	* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
	86	* is free-running, and can't generate interrupts.
	87	*
	88	* The 508 kHz timers are ideal for use for the timer interrupt, as the
	89	* most common values of HZ divide 508 kHz nicely. We pick one of the 16
	90	* bit timers (timer 1) since we don't need more than 16 bits of reload
	91	* value as long as HZ >= 8.
	92	*
	93	* The higher clock rate of timer 4 makes it a better choice than the
	94	* other timers for use in gettimeoffset(), while the fact that it can't
	95	* generate interrupts means we don't have to worry about not being able
	96	* to use this timer for something else. We also use timer 4 for keeping
	97	* track of lost jiffies.
	98	*/
	99	static unsigned int last_jiffy_time;
	100
	101	#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
	102
d5565f76	103	static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47	104	{
e7736d47	105	__raw_writel(1, EP93XX_TIMER1_CLEAR);
f869afab LB	106	while ((signed long)
f869afab LB	107	(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47 LB	108	>= TIMER4_TICKS_PER_JIFFY) {
e7736d47 LB	109	last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68	110	timer_tick();
e7736d47 LB	111	}
e7736d47 LB	112
e7736d47 LB	113	return IRQ_HANDLED;
	114	}
	115
	116	static struct irqaction ep93xx_timer_irq = {
	117	.name = "ep93xx timer",
b30fabad	118	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
e7736d47 LB	119	.handler = ep93xx_timer_interrupt,
	120	};
	121
	122	static void __init ep93xx_timer_init(void)
	123	{
	124	/* Enable periodic HZ timer. */
	125	__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
a059e33c	126	__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
e7736d47 LB	127	__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
	128
	129	/* Enable lost jiffy timer. */
	130	__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
	131
	132	setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
	133	}
	134
	135	static unsigned long ep93xx_gettimeoffset(void)
	136	{
	137	int offset;
	138
	139	offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
	140
	141	/* Calculate (1000000 / 983040) * offset. */
	142	return offset + (53 * offset / 3072);
	143	}
	144
	145	struct sys_timer ep93xx_timer = {
	146	.init = ep93xx_timer_init,
	147	.offset = ep93xx_gettimeoffset,
	148	};
	149
	150
a8e19667 LB	151	/*************************************************************************
	152	* GPIO handling for EP93xx
	153	*************************************************************************/
271f5ca6 LB	154	static unsigned char gpio_int_unmasked[3];
271f5ca6 LB	155	static unsigned char gpio_int_enabled[3];
4932e397 LB	156	static unsigned char gpio_int_type1[3];
4932e397 LB	157	static unsigned char gpio_int_type2[3];
68ee3d83	158	static unsigned char gpio_int_debounce[3];
bd20ff57	159
7ca72253 HVR	160	/* Port ordering is: A B F */
	161	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	162	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	163	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
f69162ae	164	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
799a0600	165	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
7ca72253	166
b685004f	167	void ep93xx_gpio_update_int_params(unsigned port)
bd20ff57	168	{
7ca72253 HVR	169	BUG_ON(port > 2);
	170
	171	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
bd20ff57	172
7ca72253 HVR	173	__raw_writeb(gpio_int_type2[port],
7ca72253 HVR	174	EP93XX_GPIO_REG(int_type2_register_offset[port]));
bd20ff57	175
7ca72253 HVR	176	__raw_writeb(gpio_int_type1[port],
7ca72253 HVR	177	EP93XX_GPIO_REG(int_type1_register_offset[port]));
bd20ff57	178
7ca72253 HVR	179	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
	180	EP93XX_GPIO_REG(int_en_register_offset[port]));
	181	}
bd20ff57	182
b685004f	183	void ep93xx_gpio_int_mask(unsigned line)
a8e19667	184	{
b685004f	185	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
a8e19667	186	}
a8e19667	187
799a0600 HS	188	void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
	189	{
	190	int line = irq_to_gpio(irq);
	191	int port = line >> 3;
	192	int port_mask = 1 << (line & 7);
	193
	194	if (enable)
68ee3d83	195	gpio_int_debounce[port] \|= port_mask;
799a0600	196	else
68ee3d83	197	gpio_int_debounce[port] &= ~port_mask;
799a0600	198
68ee3d83	199	__raw_writeb(gpio_int_debounce[port],
799a0600 HS	200	EP93XX_GPIO_REG(int_debounce_register_offset[port]));
	201	}
	202	EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
	203
e7736d47 LB	204	/*************************************************************************
	205	* EP93xx IRQ handling
	206	*************************************************************************/
4932e397	207	static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
bd20ff57 LB	208	{
	209	unsigned char status;
	210	int i;
	211
	212	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	213	for (i = 0; i < 8; i++) {
	214	if (status & (1 << i)) {
7ca72253	215	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
d8aa0251	216	generic_handle_irq(gpio_irq);
bd20ff57 LB	217	}
	218	}
	219
	220	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	221	for (i = 0; i < 8; i++) {
	222	if (status & (1 << i)) {
7ca72253 HVR	223	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
7ca72253 HVR	224	desc = irq_desc + gpio_irq;
d8aa0251	225	generic_handle_irq(gpio_irq);
bd20ff57 LB	226	}
	227	}
	228	}
	229
4932e397 LB	230	static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
4932e397 LB	231	{
7ca72253 HVR	232	/*
	233	* map discontiguous hw irq range to continous sw irq range:
	234	*
	235	* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	236	*/
	237	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	238	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
4932e397	239
d8aa0251	240	generic_handle_irq(gpio_irq);
4932e397 LB	241	}
4932e397 LB	242
3c9a071d HVR	243	static void ep93xx_gpio_irq_ack(unsigned int irq)
	244	{
	245	int line = irq_to_gpio(irq);
	246	int port = line >> 3;
	247	int port_mask = 1 << (line & 7);
	248
6cab4860	249	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
3c9a071d	250	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
b685004f	251	ep93xx_gpio_update_int_params(port);
3c9a071d HVR	252	}
	253
	254	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
	255	}
	256
4932e397	257	static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
bd20ff57	258	{
7ca72253	259	int line = irq_to_gpio(irq);
bd20ff57	260	int port = line >> 3;
7ca72253	261	int port_mask = 1 << (line & 7);
bd20ff57	262
6cab4860	263	if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
3c9a071d HVR	264	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
3c9a071d HVR	265
7ca72253	266	gpio_int_unmasked[port] &= ~port_mask;
b685004f	267	ep93xx_gpio_update_int_params(port);
bd20ff57	268
7ca72253	269	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
bd20ff57 LB	270	}
bd20ff57 LB	271
4932e397	272	static void ep93xx_gpio_irq_mask(unsigned int irq)
bd20ff57	273	{
7ca72253	274	int line = irq_to_gpio(irq);
bd20ff57 LB	275	int port = line >> 3;
bd20ff57 LB	276
271f5ca6	277	gpio_int_unmasked[port] &= ~(1 << (line & 7));
b685004f	278	ep93xx_gpio_update_int_params(port);
bd20ff57 LB	279	}
bd20ff57 LB	280
4932e397	281	static void ep93xx_gpio_irq_unmask(unsigned int irq)
bd20ff57	282	{
7ca72253	283	int line = irq_to_gpio(irq);
bd20ff57 LB	284	int port = line >> 3;
bd20ff57 LB	285
271f5ca6	286	gpio_int_unmasked[port] \|= 1 << (line & 7);
b685004f	287	ep93xx_gpio_update_int_params(port);
bd20ff57 LB	288	}
	289
	290
	291	/*
	292	* gpio_int_type1 controls whether the interrupt is level (0) or
	293	* edge (1) triggered, while gpio_int_type2 controls whether it
	294	* triggers on low/falling (0) or high/rising (1).
	295	*/
4932e397	296	static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
bd20ff57	297	{
3c9a071d	298	struct irq_desc *desc = irq_desc + irq;
7ca72253 HVR	299	const int gpio = irq_to_gpio(irq);
	300	const int port = gpio >> 3;
	301	const int port_mask = 1 << (gpio & 7);
bd20ff57	302
f8b6389b	303	gpio_direction_input(gpio);
bd20ff57	304
3c9a071d	305	switch (type) {
6cab4860	306	case IRQ_TYPE_EDGE_RISING:
7ca72253 HVR	307	gpio_int_type1[port] \|= port_mask;
7ca72253 HVR	308	gpio_int_type2[port] \|= port_mask;
3c9a071d HVR	309	desc->handle_irq = handle_edge_irq;
3c9a071d HVR	310	break;
6cab4860	311	case IRQ_TYPE_EDGE_FALLING:
7ca72253 HVR	312	gpio_int_type1[port] \|= port_mask;
7ca72253 HVR	313	gpio_int_type2[port] &= ~port_mask;
3c9a071d HVR	314	desc->handle_irq = handle_edge_irq;
3c9a071d HVR	315	break;
6cab4860	316	case IRQ_TYPE_LEVEL_HIGH:
7ca72253 HVR	317	gpio_int_type1[port] &= ~port_mask;
7ca72253 HVR	318	gpio_int_type2[port] \|= port_mask;
3c9a071d HVR	319	desc->handle_irq = handle_level_irq;
3c9a071d HVR	320	break;
6cab4860	321	case IRQ_TYPE_LEVEL_LOW:
7ca72253 HVR	322	gpio_int_type1[port] &= ~port_mask;
7ca72253 HVR	323	gpio_int_type2[port] &= ~port_mask;
3c9a071d HVR	324	desc->handle_irq = handle_level_irq;
3c9a071d HVR	325	break;
6cab4860	326	case IRQ_TYPE_EDGE_BOTH:
3c9a071d HVR	327	gpio_int_type1[port] \|= port_mask;
	328	/* set initial polarity based on current input level */
	329	if (gpio_get_value(gpio))
	330	gpio_int_type2[port] &= ~port_mask; /* falling */
	331	else
	332	gpio_int_type2[port] \|= port_mask; /* rising */
	333	desc->handle_irq = handle_edge_irq;
	334	break;
	335	default:
	336	pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
	337	type, gpio);
	338	return -EINVAL;
4932e397	339	}
bd20ff57	340
3c9a071d HVR	341	gpio_int_enabled[port] \|= port_mask;
	342
	343	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	344	desc->status \|= type & IRQ_TYPE_SENSE_MASK;
	345
b685004f	346	ep93xx_gpio_update_int_params(port);
bd20ff57 LB	347
	348	return 0;
	349	}
	350
4932e397 LB	351	static struct irq_chip ep93xx_gpio_irq_chip = {
4932e397 LB	352	.name = "GPIO",
3c9a071d HVR	353	.ack = ep93xx_gpio_irq_ack,
3c9a071d HVR	354	.mask_ack = ep93xx_gpio_irq_mask_ack,
4932e397 LB	355	.mask = ep93xx_gpio_irq_mask,
	356	.unmask = ep93xx_gpio_irq_unmask,
	357	.set_type = ep93xx_gpio_irq_type,
bd20ff57 LB	358	};
	359
	360
e7736d47 LB	361	void __init ep93xx_init_irq(void)
e7736d47 LB	362	{
7ca72253	363	int gpio_irq;
bd20ff57	364
c07f87f2 BD	365	vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
c07f87f2 BD	366	vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
bd20ff57	367
7ca72253 HVR	368	for (gpio_irq = gpio_to_irq(0);
	369	gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
	370	set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
	371	set_irq_handler(gpio_irq, handle_level_irq);
	372	set_irq_flags(gpio_irq, IRQF_VALID);
bd20ff57	373	}
4932e397	374
bd20ff57	375	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
4932e397 LB	376	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
	377	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
	378	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
	379	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
	380	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
	381	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
	382	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
	383	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
e7736d47 LB	384	}
	385
	386
02239f0a HS	387	/*************************************************************************
	388	* EP93xx System Controller Software Locked register handling
	389	*************************************************************************/
	390
	391	/*
	392	* syscon_swlock prevents anything else from writing to the syscon
	393	* block while a software locked register is being written.
	394	*/
	395	static DEFINE_SPINLOCK(syscon_swlock);
	396
	397	void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg)
	398	{
	399	unsigned long flags;
	400
	401	spin_lock_irqsave(&syscon_swlock, flags);
	402
	403	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
	404	__raw_writel(val, reg);
	405
	406	spin_unlock_irqrestore(&syscon_swlock, flags);
	407	}
	408	EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
	409
	410	void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
	411	{
	412	unsigned long flags;
	413	unsigned int val;
	414
	415	spin_lock_irqsave(&syscon_swlock, flags);
	416
	417	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
	418	val \|= set_bits;
	419	val &= ~clear_bits;
	420	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
	421	__raw_writel(val, EP93XX_SYSCON_DEVCFG);
	422
	423	spin_unlock_irqrestore(&syscon_swlock, flags);
	424	}
	425	EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
	426
	427
e7736d47 LB	428	/*************************************************************************
	429	* EP93xx peripheral handling
	430	*************************************************************************/
aee85fe8 LB	431	#define EP93XX_UART_MCR_OFFSET (0x0100)
	432
	433	static void ep93xx_uart_set_mctrl(struct amba_device *dev,
	434	void __iomem *base, unsigned int mctrl)
	435	{
	436	unsigned int mcr;
	437
	438	mcr = 0;
	439	if (!(mctrl & TIOCM_RTS))
	440	mcr \|= 2;
	441	if (!(mctrl & TIOCM_DTR))
	442	mcr \|= 1;
	443
	444	__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
	445	}
	446
	447	static struct amba_pl010_data ep93xx_uart_data = {
	448	.set_mctrl = ep93xx_uart_set_mctrl,
	449	};
	450
	451	static struct amba_device uart1_device = {
	452	.dev = {
1d559e29	453	.init_name = "apb:uart1",
aee85fe8 LB	454	.platform_data = &ep93xx_uart_data,
	455	},
	456	.res = {
	457	.start = EP93XX_UART1_PHYS_BASE,
	458	.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
	459	.flags = IORESOURCE_MEM,
	460	},
	461	.irq = { IRQ_EP93XX_UART1, NO_IRQ },
	462	.periphid = 0x00041010,
	463	};
	464
	465	static struct amba_device uart2_device = {
	466	.dev = {
1d559e29	467	.init_name = "apb:uart2",
aee85fe8 LB	468	.platform_data = &ep93xx_uart_data,
	469	},
	470	.res = {
	471	.start = EP93XX_UART2_PHYS_BASE,
	472	.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
	473	.flags = IORESOURCE_MEM,
	474	},
	475	.irq = { IRQ_EP93XX_UART2, NO_IRQ },
	476	.periphid = 0x00041010,
	477	};
	478
	479	static struct amba_device uart3_device = {
	480	.dev = {
1d559e29	481	.init_name = "apb:uart3",
aee85fe8 LB	482	.platform_data = &ep93xx_uart_data,
	483	},
	484	.res = {
	485	.start = EP93XX_UART3_PHYS_BASE,
	486	.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
	487	.flags = IORESOURCE_MEM,
	488	},
	489	.irq = { IRQ_EP93XX_UART3, NO_IRQ },
	490	.periphid = 0x00041010,
	491	};
	492
41658132	493
38f7b009 HS	494	static struct resource ep93xx_rtc_resource[] = {
	495	{
	496	.start = EP93XX_RTC_PHYS_BASE,
	497	.end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
	498	.flags = IORESOURCE_MEM,
	499	},
	500	};
	501
41658132	502	static struct platform_device ep93xx_rtc_device = {
38f7b009 HS	503	.name = "ep93xx-rtc",
	504	.id = -1,
	505	.num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
	506	.resource = ep93xx_rtc_resource,
41658132 LB	507	};
	508
	509
1f64eb37 LB	510	static struct resource ep93xx_ohci_resources[] = {
	511	[0] = {
	512	.start = EP93XX_USB_PHYS_BASE,
	513	.end = EP93XX_USB_PHYS_BASE + 0x0fff,
	514	.flags = IORESOURCE_MEM,
	515	},
	516	[1] = {
	517	.start = IRQ_EP93XX_USB,
	518	.end = IRQ_EP93XX_USB,
	519	.flags = IORESOURCE_IRQ,
	520	},
	521	};
	522
63890a0e	523
1f64eb37 LB	524	static struct platform_device ep93xx_ohci_device = {
	525	.name = "ep93xx-ohci",
	526	.id = -1,
	527	.dev = {
63890a0e MK	528	.dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
63890a0e MK	529	.coherent_dma_mask = DMA_BIT_MASK(32),
1f64eb37 LB	530	},
	531	.num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
	532	.resource = ep93xx_ohci_resources,
	533	};
	534
a0a08fdc HS	535	static struct ep93xx_eth_data ep93xx_eth_data;
	536
	537	static struct resource ep93xx_eth_resource[] = {
	538	{
	539	.start = EP93XX_ETHERNET_PHYS_BASE,
	540	.end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
	541	.flags = IORESOURCE_MEM,
	542	}, {
	543	.start = IRQ_EP93XX_ETHERNET,
	544	.end = IRQ_EP93XX_ETHERNET,
	545	.flags = IORESOURCE_IRQ,
	546	}
	547	};
	548
	549	static struct platform_device ep93xx_eth_device = {
	550	.name = "ep93xx-eth",
	551	.id = -1,
	552	.dev = {
	553	.platform_data = &ep93xx_eth_data,
	554	},
	555	.num_resources = ARRAY_SIZE(ep93xx_eth_resource),
	556	.resource = ep93xx_eth_resource,
	557	};
	558
	559	void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
	560	{
	561	if (copy_addr) {
	562	memcpy(data->dev_addr,
	563	(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
	564	}
	565
	566	ep93xx_eth_data = *data;
	567	platform_device_register(&ep93xx_eth_device);
	568	}
	569
d52a26a9 HS	570	static struct i2c_gpio_platform_data ep93xx_i2c_data = {
	571	.sda_pin = EP93XX_GPIO_LINE_EEDAT,
	572	.sda_is_open_drain = 0,
	573	.scl_pin = EP93XX_GPIO_LINE_EECLK,
	574	.scl_is_open_drain = 0,
	575	.udelay = 2,
	576	};
	577
	578	static struct platform_device ep93xx_i2c_device = {
	579	.name = "i2c-gpio",
	580	.id = 0,
	581	.dev.platform_data = &ep93xx_i2c_data,
	582	};
	583
	584	void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
	585	{
	586	i2c_register_board_info(0, devices, num);
	587	platform_device_register(&ep93xx_i2c_device);
	588	}
	589
b685004f	590	extern void ep93xx_gpio_init(void);
1f64eb37	591
e7736d47 LB	592	void __init ep93xx_init_devices(void)
e7736d47 LB	593	{
02239f0a HS	594	/* Disallow access to MaverickCrunch initially */
02239f0a HS	595	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8	596
b685004f RM	597	ep93xx_gpio_init();
b685004f RM	598
aee85fe8 LB	599	amba_device_register(&uart1_device, &iomem_resource);
	600	amba_device_register(&uart2_device, &iomem_resource);
	601	amba_device_register(&uart3_device, &iomem_resource);
41658132 LB	602
41658132 LB	603	platform_device_register(&ep93xx_rtc_device);
1f64eb37	604	platform_device_register(&ep93xx_ohci_device);
e7736d47	605	}