[deliverable/linux.git] / arch / arm / mach-ep93xx / gpio.c

/*
 * linux/arch/arm/mach-ep93xx/gpio.c
 *
 * Generic EP93xx GPIO handling
 *
 * Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
 *
 * Based on code originally from:
 *  linux/arch/arm/mach-ep93xx/core.c
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/irq.h>

#include <mach/hardware.h>

/*************************************************************************
 * Interrupt handling for EP93xx on-chip GPIOs
 *************************************************************************/
static unsigned char gpio_int_unmasked[3];
static unsigned char gpio_int_enabled[3];
static unsigned char gpio_int_type1[3];
static unsigned char gpio_int_type2[3];
static unsigned char gpio_int_debounce[3];

/* Port ordering is: A B F */
static const u8 int_type1_register_offset[3]	= { 0x90, 0xac, 0x4c };
static const u8 int_type2_register_offset[3]	= { 0x94, 0xb0, 0x50 };
static const u8 eoi_register_offset[3]		= { 0x98, 0xb4, 0x54 };
static const u8 int_en_register_offset[3]	= { 0x9c, 0xb8, 0x58 };
static const u8 int_debounce_register_offset[3]	= { 0xa8, 0xc4, 0x64 };

static void ep93xx_gpio_update_int_params(unsigned port)
{
	BUG_ON(port > 2);

	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));

	__raw_writeb(gpio_int_type2[port],
		EP93XX_GPIO_REG(int_type2_register_offset[port]));

	__raw_writeb(gpio_int_type1[port],
		EP93XX_GPIO_REG(int_type1_register_offset[port]));

	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
		EP93XX_GPIO_REG(int_en_register_offset[port]));
}

static inline void ep93xx_gpio_int_mask(unsigned line)
{
	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
}

static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
{
	int line = irq_to_gpio(irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if (enable)
		gpio_int_debounce[port] |= port_mask;
	else
		gpio_int_debounce[port] &= ~port_mask;

	__raw_writeb(gpio_int_debounce[port],
		EP93XX_GPIO_REG(int_debounce_register_offset[port]));
}

static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned char status;
	int i;

	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}

	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	for (i = 0; i < 8; i++) {
		if (status & (1 << i)) {
			int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
			generic_handle_irq(gpio_irq);
		}
	}
}

static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	/*
	 * map discontiguous hw irq range to continous sw irq range:
	 *
	 *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	 */
	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;

	generic_handle_irq(gpio_irq);
}

static void ep93xx_gpio_irq_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */
		ep93xx_gpio_update_int_params(port);
	}

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;
	int port_mask = 1 << (line & 7);

	if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
		gpio_int_type2[port] ^= port_mask; /* switch edge direction */

	gpio_int_unmasked[port] &= ~port_mask;
	ep93xx_gpio_update_int_params(port);

	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
}

static void ep93xx_gpio_irq_mask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	ep93xx_gpio_update_int_params(port);
}

static void ep93xx_gpio_irq_unmask(struct irq_data *d)
{
	int line = irq_to_gpio(d->irq);
	int port = line >> 3;

	gpio_int_unmasked[port] |= 1 << (line & 7);
	ep93xx_gpio_update_int_params(port);
}

/*
 * gpio_int_type1 controls whether the interrupt is level (0) or
 * edge (1) triggered, while gpio_int_type2 controls whether it
 * triggers on low/falling (0) or high/rising (1).
 */
static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_desc *desc = irq_desc + d->irq;
	const int gpio = irq_to_gpio(d->irq);
	const int port = gpio >> 3;
	const int port_mask = 1 << (gpio & 7);

	gpio_direction_input(gpio);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] |= port_mask;
		desc->handle_irq = handle_edge_irq;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_int_type1[port] |= port_mask;
		gpio_int_type2[port] &= ~port_mask;
		desc->handle_irq = handle_edge_irq;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] |= port_mask;
		desc->handle_irq = handle_level_irq;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_int_type1[port] &= ~port_mask;
		gpio_int_type2[port] &= ~port_mask;
		desc->handle_irq = handle_level_irq;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		gpio_int_type1[port] |= port_mask;
		/* set initial polarity based on current input level */
		if (gpio_get_value(gpio))
			gpio_int_type2[port] &= ~port_mask; /* falling */
		else
			gpio_int_type2[port] |= port_mask; /* rising */
		desc->handle_irq = handle_edge_irq;
		break;
	default:
		pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
		return -EINVAL;
	}

	gpio_int_enabled[port] |= port_mask;

	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	desc->status |= type & IRQ_TYPE_SENSE_MASK;

	ep93xx_gpio_update_int_params(port);

	return 0;
}

static struct irq_chip ep93xx_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= ep93xx_gpio_irq_ack,
	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
	.irq_mask	= ep93xx_gpio_irq_mask,
	.irq_unmask	= ep93xx_gpio_irq_unmask,
	.irq_set_type	= ep93xx_gpio_irq_type,
};

void __init ep93xx_gpio_init_irq(void)
{
	int gpio_irq;

	for (gpio_irq = gpio_to_irq(0);
	     gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
		set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
		set_irq_handler(gpio_irq, handle_level_irq);
		set_irq_flags(gpio_irq, IRQF_VALID);
	}

	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
}


/*************************************************************************
 * gpiolib interface for EP93xx on-chip GPIOs
 *************************************************************************/
struct ep93xx_gpio_chip {
	struct gpio_chip	chip;

	void __iomem		*data_reg;
	void __iomem		*data_dir_reg;
};

#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)

static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	unsigned long flags;
	u8 v;

	local_irq_save(flags);
	v = __raw_readb(ep93xx_chip->data_dir_reg);
	v &= ~(1 << offset);
	__raw_writeb(v, ep93xx_chip->data_dir_reg);
	local_irq_restore(flags);

	return 0;
}

static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int val)
{
	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	unsigned long flags;
	int line;
	u8 v;

	local_irq_save(flags);

	/* Set the value */
	v = __raw_readb(ep93xx_chip->data_reg);
	if (val)
		v |= (1 << offset);
	else
		v &= ~(1 << offset);
	__raw_writeb(v, ep93xx_chip->data_reg);

	/* Drive as an output */
	line = chip->base + offset;
	if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
		/* Ports A/B/F */
		ep93xx_gpio_int_mask(line);
		ep93xx_gpio_update_int_params(line >> 3);
	}

	v = __raw_readb(ep93xx_chip->data_dir_reg);
	v |= (1 << offset);
	__raw_writeb(v, ep93xx_chip->data_dir_reg);

	local_irq_restore(flags);

	return 0;
}

static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);

	return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
}

static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	unsigned long flags;
	u8 v;

	local_irq_save(flags);
	v = __raw_readb(ep93xx_chip->data_reg);
	if (val)
		v |= (1 << offset);
	else
		v &= ~(1 << offset);
	__raw_writeb(v, ep93xx_chip->data_reg);
	local_irq_restore(flags);
}

static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
				    unsigned offset, unsigned debounce)
{
	int gpio = chip->base + offset;
	int irq = gpio_to_irq(gpio);

	if (irq < 0)
		return -EINVAL;

	ep93xx_gpio_int_debounce(irq, debounce ? true : false);

	return 0;
}

static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
{
	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	u8 data_reg, data_dir_reg;
	int gpio, i;

	data_reg = __raw_readb(ep93xx_chip->data_reg);
	data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);

	gpio = ep93xx_chip->chip.base;
	for (i = 0; i < chip->ngpio; i++, gpio++) {
		int is_out = data_dir_reg & (1 << i);
		int irq = gpio_to_irq(gpio);

		seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n",
				chip->label, i, gpio,
				gpiochip_is_requested(chip, i) ? : "",
				is_out ? "out" : "in ",
				(data_reg & (1<<  i)) ? "hi" : "lo",
				(!is_out && irq>= 0) ? "(interrupt)" : "");
	}
}

#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)			\
	{								\
		.chip = {						\
			.label		  = name,			\
			.direction_input  = ep93xx_gpio_direction_input, \
			.direction_output = ep93xx_gpio_direction_output, \
			.get		  = ep93xx_gpio_get,		\
			.set		  = ep93xx_gpio_set,		\
			.dbg_show	  = ep93xx_gpio_dbg_show,	\
			.base		  = base_gpio,			\
			.ngpio		  = 8,				\
		},							\
		.data_reg	= EP93XX_GPIO_REG(dr),			\
		.data_dir_reg	= EP93XX_GPIO_REG(ddr),			\
	}

static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
};

void __init ep93xx_gpio_init(void)
{
	int i;

	/* Set Ports C, D, E, G, and H for GPIO use */
	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
				 EP93XX_SYSCON_DEVCFG_GONK |
				 EP93XX_SYSCON_DEVCFG_EONIDE |
				 EP93XX_SYSCON_DEVCFG_GONIDE |
				 EP93XX_SYSCON_DEVCFG_HONIDE);

	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
		struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;

		/*
		 * Ports A, B, and F support input debouncing when
		 * used as interrupts.
		 */
		if (!strcmp(chip->label, "A") ||
		    !strcmp(chip->label, "B") ||
		    !strcmp(chip->label, "F"))
			chip->set_debounce = ep93xx_gpio_set_debounce;

		gpiochip_add(chip);
	}
}
Commit	Line	Data
b685004f RM	1	/*
	2	* linux/arch/arm/mach-ep93xx/gpio.c
	3	*
	4	* Generic EP93xx GPIO handling
	5	*
	6	* Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
	7	*
	8	* Based on code originally from:
	9	* linux/arch/arm/mach-ep93xx/core.c
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
d056ab78 HS	16	#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
d056ab78 HS	17
b685004f RM	18	#include <linux/init.h>
	19	#include <linux/module.h>
	20	#include <linux/seq_file.h>
fced80c7	21	#include <linux/io.h>
ddf4f3d9	22	#include <linux/gpio.h>
595c050d	23	#include <linux/irq.h>
b685004f	24
ddf4f3d9	25	#include <mach/hardware.h>
b685004f	26
d056ab78	27	/*************************************************************************
4742723c	28	* Interrupt handling for EP93xx on-chip GPIOs
d056ab78 HS	29	*************************************************************************/
	30	static unsigned char gpio_int_unmasked[3];
	31	static unsigned char gpio_int_enabled[3];
	32	static unsigned char gpio_int_type1[3];
	33	static unsigned char gpio_int_type2[3];
	34	static unsigned char gpio_int_debounce[3];
	35
	36	/* Port ordering is: A B F */
	37	static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
	38	static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
	39	static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
	40	static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
	41	static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
	42
4742723c	43	static void ep93xx_gpio_update_int_params(unsigned port)
d056ab78 HS	44	{
	45	BUG_ON(port > 2);
	46
	47	__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
	48
	49	__raw_writeb(gpio_int_type2[port],
	50	EP93XX_GPIO_REG(int_type2_register_offset[port]));
	51
	52	__raw_writeb(gpio_int_type1[port],
	53	EP93XX_GPIO_REG(int_type1_register_offset[port]));
	54
	55	__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
	56	EP93XX_GPIO_REG(int_en_register_offset[port]));
	57	}
	58
4742723c	59	static inline void ep93xx_gpio_int_mask(unsigned line)
d056ab78 HS	60	{
	61	gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
	62	}
	63
5d046af0	64	static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
d056ab78 HS	65	{
	66	int line = irq_to_gpio(irq);
	67	int port = line >> 3;
	68	int port_mask = 1 << (line & 7);
	69
	70	if (enable)
	71	gpio_int_debounce[port] \|= port_mask;
	72	else
	73	gpio_int_debounce[port] &= ~port_mask;
	74
	75	__raw_writeb(gpio_int_debounce[port],
	76	EP93XX_GPIO_REG(int_debounce_register_offset[port]));
	77	}
d056ab78 HS	78
	79	static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
	80	{
	81	unsigned char status;
	82	int i;
	83
	84	status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
	85	for (i = 0; i < 8; i++) {
	86	if (status & (1 << i)) {
	87	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
	88	generic_handle_irq(gpio_irq);
	89	}
	90	}
	91
	92	status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
	93	for (i = 0; i < 8; i++) {
	94	if (status & (1 << i)) {
	95	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
	96	generic_handle_irq(gpio_irq);
	97	}
	98	}
	99	}
	100
	101	static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
	102	{
	103	/*
	104	* map discontiguous hw irq range to continous sw irq range:
	105	*
	106	* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
	107	*/
	108	int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
	109	int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
	110
	111	generic_handle_irq(gpio_irq);
	112	}
	113
c0afc916	114	static void ep93xx_gpio_irq_ack(struct irq_data *d)
d056ab78	115	{
c0afc916	116	int line = irq_to_gpio(d->irq);
d056ab78 HS	117	int port = line >> 3;
	118	int port_mask = 1 << (line & 7);
	119
c0afc916	120	if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
d056ab78 HS	121	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	122	ep93xx_gpio_update_int_params(port);
	123	}
	124
	125	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
	126	}
	127
c0afc916	128	static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
d056ab78	129	{
c0afc916	130	int line = irq_to_gpio(d->irq);
d056ab78 HS	131	int port = line >> 3;
	132	int port_mask = 1 << (line & 7);
	133
c0afc916	134	if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
d056ab78 HS	135	gpio_int_type2[port] ^= port_mask; /* switch edge direction */
	136
	137	gpio_int_unmasked[port] &= ~port_mask;
	138	ep93xx_gpio_update_int_params(port);
	139
	140	__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
	141	}
	142
c0afc916	143	static void ep93xx_gpio_irq_mask(struct irq_data *d)
d056ab78	144	{
c0afc916	145	int line = irq_to_gpio(d->irq);
d056ab78 HS	146	int port = line >> 3;
	147
	148	gpio_int_unmasked[port] &= ~(1 << (line & 7));
	149	ep93xx_gpio_update_int_params(port);
	150	}
	151
c0afc916	152	static void ep93xx_gpio_irq_unmask(struct irq_data *d)
d056ab78	153	{
c0afc916	154	int line = irq_to_gpio(d->irq);
d056ab78 HS	155	int port = line >> 3;
	156
	157	gpio_int_unmasked[port] \|= 1 << (line & 7);
	158	ep93xx_gpio_update_int_params(port);
	159	}
	160
	161	/*
	162	* gpio_int_type1 controls whether the interrupt is level (0) or
	163	* edge (1) triggered, while gpio_int_type2 controls whether it
	164	* triggers on low/falling (0) or high/rising (1).
	165	*/
c0afc916	166	static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
d056ab78	167	{
c0afc916 LB	168	struct irq_desc *desc = irq_desc + d->irq;
c0afc916 LB	169	const int gpio = irq_to_gpio(d->irq);
d056ab78 HS	170	const int port = gpio >> 3;
	171	const int port_mask = 1 << (gpio & 7);
	172
	173	gpio_direction_input(gpio);
	174
	175	switch (type) {
	176	case IRQ_TYPE_EDGE_RISING:
	177	gpio_int_type1[port] \|= port_mask;
	178	gpio_int_type2[port] \|= port_mask;
	179	desc->handle_irq = handle_edge_irq;
	180	break;
	181	case IRQ_TYPE_EDGE_FALLING:
	182	gpio_int_type1[port] \|= port_mask;
	183	gpio_int_type2[port] &= ~port_mask;
	184	desc->handle_irq = handle_edge_irq;
	185	break;
	186	case IRQ_TYPE_LEVEL_HIGH:
	187	gpio_int_type1[port] &= ~port_mask;
	188	gpio_int_type2[port] \|= port_mask;
	189	desc->handle_irq = handle_level_irq;
	190	break;
	191	case IRQ_TYPE_LEVEL_LOW:
	192	gpio_int_type1[port] &= ~port_mask;
	193	gpio_int_type2[port] &= ~port_mask;
	194	desc->handle_irq = handle_level_irq;
	195	break;
	196	case IRQ_TYPE_EDGE_BOTH:
	197	gpio_int_type1[port] \|= port_mask;
	198	/* set initial polarity based on current input level */
	199	if (gpio_get_value(gpio))
	200	gpio_int_type2[port] &= ~port_mask; /* falling */
	201	else
	202	gpio_int_type2[port] \|= port_mask; /* rising */
	203	desc->handle_irq = handle_edge_irq;
	204	break;
	205	default:
	206	pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
	207	return -EINVAL;
	208	}
	209
	210	gpio_int_enabled[port] \|= port_mask;
	211
	212	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	213	desc->status \|= type & IRQ_TYPE_SENSE_MASK;
	214
	215	ep93xx_gpio_update_int_params(port);
	216
	217	return 0;
	218	}
	219
	220	static struct irq_chip ep93xx_gpio_irq_chip = {
	221	.name = "GPIO",
c0afc916 LB	222	.irq_ack = ep93xx_gpio_irq_ack,
	223	.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
	224	.irq_mask = ep93xx_gpio_irq_mask,
	225	.irq_unmask = ep93xx_gpio_irq_unmask,
	226	.irq_set_type = ep93xx_gpio_irq_type,
d056ab78 HS	227	};
	228
	229	void __init ep93xx_gpio_init_irq(void)
	230	{
	231	int gpio_irq;
	232
	233	for (gpio_irq = gpio_to_irq(0);
	234	gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
	235	set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
	236	set_irq_handler(gpio_irq, handle_level_irq);
	237	set_irq_flags(gpio_irq, IRQF_VALID);
	238	}
	239
	240	set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
	241	set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
	242	set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
	243	set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
	244	set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
	245	set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
	246	set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
	247	set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
	248	set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
	249	}
	250
	251
	252	/*************************************************************************
	253	* gpiolib interface for EP93xx on-chip GPIOs
	254	*************************************************************************/
b685004f RM	255	struct ep93xx_gpio_chip {
	256	struct gpio_chip chip;
	257
ddf4f3d9 HS	258	void __iomem *data_reg;
ddf4f3d9 HS	259	void __iomem *data_dir_reg;
b685004f RM	260	};
	261
	262	#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
	263
b685004f RM	264	static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	265	{
	266	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	267	unsigned long flags;
	268	u8 v;
	269
	270	local_irq_save(flags);
	271	v = __raw_readb(ep93xx_chip->data_dir_reg);
	272	v &= ~(1 << offset);
	273	__raw_writeb(v, ep93xx_chip->data_dir_reg);
	274	local_irq_restore(flags);
	275
	276	return 0;
	277	}
	278
	279	static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
	280	unsigned offset, int val)
	281	{
	282	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	283	unsigned long flags;
	284	int line;
	285	u8 v;
	286
	287	local_irq_save(flags);
	288
	289	/* Set the value */
	290	v = __raw_readb(ep93xx_chip->data_reg);
	291	if (val)
	292	v \|= (1 << offset);
	293	else
	294	v &= ~(1 << offset);
	295	__raw_writeb(v, ep93xx_chip->data_reg);
	296
	297	/* Drive as an output */
	298	line = chip->base + offset;
	299	if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
	300	/* Ports A/B/F */
	301	ep93xx_gpio_int_mask(line);
	302	ep93xx_gpio_update_int_params(line >> 3);
	303	}
	304
	305	v = __raw_readb(ep93xx_chip->data_dir_reg);
	306	v \|= (1 << offset);
	307	__raw_writeb(v, ep93xx_chip->data_dir_reg);
	308
	309	local_irq_restore(flags);
	310
	311	return 0;
	312	}
	313
	314	static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
	315	{
	316	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	317
	318	return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
	319	}
	320
	321	static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	322	{
	323	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	324	unsigned long flags;
	325	u8 v;
	326
	327	local_irq_save(flags);
328	v = __raw_readb(ep93xx_chip->data_reg);
329	if (val)
330	v \|= (1 << offset);
331	else
332	v &= ~(1 << offset);
333	__raw_writeb(v, ep93xx_chip->data_reg);
334	local_irq_restore(flags);
335	}
336
5d046af0 HS	337	static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
	338	unsigned offset, unsigned debounce)
	339	{
	340	int gpio = chip->base + offset;
	341	int irq = gpio_to_irq(gpio);
	342
	343	if (irq < 0)
	344	return -EINVAL;
	345
	346	ep93xx_gpio_int_debounce(irq, debounce ? true : false);
	347
	348	return 0;
	349	}
	350
b685004f RM	351	static void ep93xx_gpio_dbg_show(struct seq_file s, struct gpio_chip chip)
	352	{
	353	struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
	354	u8 data_reg, data_dir_reg;
f04989bb	355	int gpio, i;
b685004f RM	356
	357	data_reg = __raw_readb(ep93xx_chip->data_reg);
	358	data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
	359
f04989bb HS	360	gpio = ep93xx_chip->chip.base;
	361	for (i = 0; i < chip->ngpio; i++, gpio++) {
	362	int is_out = data_dir_reg & (1 << i);
778b548c	363	int irq = gpio_to_irq(gpio);
f04989bb	364
778b548c	365	seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n",
f04989bb HS	366	chip->label, i, gpio,
	367	gpiochip_is_requested(chip, i) ? : "",
	368	is_out ? "out" : "in ",
778b548c RM	369	(data_reg & (1<< i)) ? "hi" : "lo",
778b548c RM	370	(!is_out && irq>= 0) ? "(interrupt)" : "");
f04989bb	371	}
b685004f RM	372	}
	373
	374	#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
	375	{ \
	376	.chip = { \
	377	.label = name, \
	378	.direction_input = ep93xx_gpio_direction_input, \
	379	.direction_output = ep93xx_gpio_direction_output, \
	380	.get = ep93xx_gpio_get, \
	381	.set = ep93xx_gpio_set, \
	382	.dbg_show = ep93xx_gpio_dbg_show, \
	383	.base = base_gpio, \
	384	.ngpio = 8, \
	385	}, \
	386	.data_reg = EP93XX_GPIO_REG(dr), \
	387	.data_dir_reg = EP93XX_GPIO_REG(ddr), \
	388	}
	389
	390	static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
	391	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
	392	EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
7a1f3701	393	EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
b685004f RM	394	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
b685004f RM	395	EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
7a1f3701	396	EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
b685004f RM	397	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
	398	EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
	399	};
	400
	401	void __init ep93xx_gpio_init(void)
	402	{
	403	int i;
	404
fd015480 HS	405	/* Set Ports C, D, E, G, and H for GPIO use */
	406	ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS \|
	407	EP93XX_SYSCON_DEVCFG_GONK \|
	408	EP93XX_SYSCON_DEVCFG_EONIDE \|
	409	EP93XX_SYSCON_DEVCFG_GONIDE \|
	410	EP93XX_SYSCON_DEVCFG_HONIDE);
	411
5d046af0 HS	412	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
	413	struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
	414
	415	/*
	416	* Ports A, B, and F support input debouncing when
	417	* used as interrupts.
	418	*/
	419	if (!strcmp(chip->label, "A") \|\|
	420	!strcmp(chip->label, "B") \|\|
	421	!strcmp(chip->label, "F"))
	422	chip->set_debounce = ep93xx_gpio_set_debounce;
	423
	424	gpiochip_add(chip);
	425	}
b685004f	426	}