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258249ec RM |
1 | /* |
2 | * arch/arm/mach-ep93xx/soc.h | |
3 | * | |
4 | * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com> | |
5 | * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or (at | |
10 | * your option) any later version. | |
11 | */ | |
12 | ||
13 | #ifndef _EP93XX_SOC_H | |
14 | #define _EP93XX_SOC_H | |
15 | ||
16 | /* | |
17 | * EP93xx Physical Memory Map: | |
18 | * | |
19 | * The ASDO pin is sampled at system reset to select a synchronous or | |
20 | * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up) | |
21 | * the synchronous boot mode is selected. When ASDO is "0" (i.e | |
22 | * pulled-down) the asynchronous boot mode is selected. | |
23 | * | |
24 | * In synchronous boot mode nSDCE3 is decoded starting at physical address | |
25 | * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous | |
26 | * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3 | |
27 | * decoded at 0xf0000000. | |
28 | * | |
29 | * There is known errata for the EP93xx dealing with External Memory | |
30 | * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design | |
31 | * Guidelines" for more information. This document can be found at: | |
32 | * | |
33 | * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf | |
34 | */ | |
35 | ||
36 | #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */ | |
37 | #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */ | |
38 | #define EP93XX_CS1_PHYS_BASE 0x10000000 | |
39 | #define EP93XX_CS2_PHYS_BASE 0x20000000 | |
40 | #define EP93XX_CS3_PHYS_BASE 0x30000000 | |
41 | #define EP93XX_PCMCIA_PHYS_BASE 0x40000000 | |
42 | #define EP93XX_CS6_PHYS_BASE 0x60000000 | |
43 | #define EP93XX_CS7_PHYS_BASE 0x70000000 | |
44 | #define EP93XX_SDCE0_PHYS_BASE 0xc0000000 | |
45 | #define EP93XX_SDCE1_PHYS_BASE 0xd0000000 | |
46 | #define EP93XX_SDCE2_PHYS_BASE 0xe0000000 | |
47 | #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */ | |
48 | #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */ | |
49 | ||
a05baf33 RM |
50 | /* AHB peripherals */ |
51 | #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) | |
52 | ||
53 | #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000) | |
54 | #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) | |
55 | ||
56 | #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000) | |
57 | #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) | |
58 | ||
59 | #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000) | |
60 | #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) | |
61 | ||
62 | #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) | |
63 | ||
64 | #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) | |
65 | ||
66 | #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) | |
67 | ||
68 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) | |
69 | ||
70 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) | |
71 | ||
72 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) | |
73 | ||
74 | #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) | |
75 | ||
76 | /* APB peripherals */ | |
77 | #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) | |
78 | ||
79 | #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000) | |
80 | #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) | |
81 | ||
82 | #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) | |
83 | ||
84 | #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) | |
85 | #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) | |
86 | ||
87 | #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) | |
88 | #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) | |
89 | ||
90 | #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) | |
91 | ||
92 | #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000) | |
93 | #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) | |
94 | ||
95 | #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) | |
96 | #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) | |
97 | ||
98 | #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000) | |
99 | #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) | |
100 | ||
101 | #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000) | |
102 | #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) | |
103 | ||
104 | #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000) | |
105 | #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) | |
106 | ||
999c53fb RM |
107 | /* EP93xx System Controller software locked register write */ |
108 | void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); | |
109 | void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits); | |
110 | ||
111 | static inline void ep93xx_devcfg_set_bits(unsigned int bits) | |
112 | { | |
113 | ep93xx_devcfg_set_clear(bits, 0x00); | |
114 | } | |
115 | ||
116 | static inline void ep93xx_devcfg_clear_bits(unsigned int bits) | |
117 | { | |
118 | ep93xx_devcfg_set_clear(0x00, bits); | |
119 | } | |
120 | ||
258249ec | 121 | #endif /* _EP93XX_SOC_H */ |