Commit | Line | Data |
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ce9c00ee | 1 | /* |
a855039e | 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. |
b3ed3a17 | 3 | * http://www.samsung.com |
c8bef140 | 4 | * |
b3ed3a17 | 5 | * EXYNOS4 - Clock support |
c8bef140 CY |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
acd35616 | 15 | #include <linux/syscore_ops.h> |
c8bef140 CY |
16 | |
17 | #include <plat/cpu-freq.h> | |
18 | #include <plat/clock.h> | |
19 | #include <plat/cpu.h> | |
20 | #include <plat/pll.h> | |
21 | #include <plat/s5p-clock.h> | |
22 | #include <plat/clock-clksrc.h> | |
acd35616 | 23 | #include <plat/pm.h> |
c8bef140 CY |
24 | |
25 | #include <mach/map.h> | |
26 | #include <mach/regs-clock.h> | |
b0b6ff0b | 27 | #include <mach/sysmmu.h> |
c8bef140 | 28 | |
cc511b8d | 29 | #include "common.h" |
ce9c00ee | 30 | #include "clock-exynos4.h" |
cc511b8d | 31 | |
7cdf04d7 | 32 | #ifdef CONFIG_PM_SLEEP |
acd35616 | 33 | static struct sleep_save exynos4_clock_save[] = { |
a855039e KK |
34 | SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS), |
35 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS), | |
36 | SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS), | |
37 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS), | |
38 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP0), | |
39 | SAVE_ITEM(EXYNOS4_CLKSRC_TOP1), | |
40 | SAVE_ITEM(EXYNOS4_CLKSRC_CAM), | |
41 | SAVE_ITEM(EXYNOS4_CLKSRC_TV), | |
42 | SAVE_ITEM(EXYNOS4_CLKSRC_MFC), | |
43 | SAVE_ITEM(EXYNOS4_CLKSRC_G3D), | |
44 | SAVE_ITEM(EXYNOS4_CLKSRC_LCD0), | |
45 | SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO), | |
46 | SAVE_ITEM(EXYNOS4_CLKSRC_FSYS), | |
47 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0), | |
48 | SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1), | |
49 | SAVE_ITEM(EXYNOS4_CLKDIV_CAM), | |
50 | SAVE_ITEM(EXYNOS4_CLKDIV_TV), | |
51 | SAVE_ITEM(EXYNOS4_CLKDIV_MFC), | |
52 | SAVE_ITEM(EXYNOS4_CLKDIV_G3D), | |
53 | SAVE_ITEM(EXYNOS4_CLKDIV_LCD0), | |
54 | SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO), | |
55 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0), | |
56 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1), | |
57 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2), | |
58 | SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3), | |
59 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0), | |
60 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1), | |
61 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2), | |
62 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3), | |
63 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4), | |
64 | SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5), | |
65 | SAVE_ITEM(EXYNOS4_CLKDIV_TOP), | |
66 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP), | |
67 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM), | |
68 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV), | |
69 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0), | |
70 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO), | |
71 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS), | |
72 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0), | |
73 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1), | |
74 | SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO), | |
75 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM), | |
76 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM), | |
77 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV), | |
78 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC), | |
79 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D), | |
80 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0), | |
81 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS), | |
82 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS), | |
83 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL), | |
84 | SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK), | |
85 | SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC), | |
86 | SAVE_ITEM(EXYNOS4_CLKSRC_DMC), | |
87 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC0), | |
88 | SAVE_ITEM(EXYNOS4_CLKDIV_DMC1), | |
89 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC), | |
90 | SAVE_ITEM(EXYNOS4_CLKSRC_CPU), | |
91 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU), | |
92 | SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4), | |
93 | SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU), | |
94 | SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU), | |
acd35616 | 95 | }; |
7cdf04d7 | 96 | #endif |
acd35616 | 97 | |
a855039e | 98 | static struct clk exynos4_clk_sclk_hdmi27m = { |
c8bef140 | 99 | .name = "sclk_hdmi27m", |
c8bef140 CY |
100 | .rate = 27000000, |
101 | }; | |
102 | ||
a855039e | 103 | static struct clk exynos4_clk_sclk_hdmiphy = { |
b99380e1 | 104 | .name = "sclk_hdmiphy", |
b99380e1 JL |
105 | }; |
106 | ||
a855039e | 107 | static struct clk exynos4_clk_sclk_usbphy0 = { |
b99380e1 | 108 | .name = "sclk_usbphy0", |
b99380e1 JL |
109 | .rate = 27000000, |
110 | }; | |
111 | ||
a855039e | 112 | static struct clk exynos4_clk_sclk_usbphy1 = { |
b99380e1 | 113 | .name = "sclk_usbphy1", |
b99380e1 JL |
114 | }; |
115 | ||
bf856fbb BK |
116 | static struct clk dummy_apb_pclk = { |
117 | .name = "apb_pclk", | |
118 | .id = -1, | |
119 | }; | |
120 | ||
b3ed3a17 | 121 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
37e01729 | 122 | { |
a855039e | 123 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable); |
37e01729 JL |
124 | } |
125 | ||
b3ed3a17 | 126 | static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable) |
33f469d2 | 127 | { |
a855039e | 128 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable); |
33f469d2 JL |
129 | } |
130 | ||
b3ed3a17 | 131 | static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) |
33f469d2 | 132 | { |
a855039e | 133 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable); |
33f469d2 JL |
134 | } |
135 | ||
2bc02c0d | 136 | int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 137 | { |
a855039e | 138 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable); |
340ea1ef JL |
139 | } |
140 | ||
b3ed3a17 | 141 | static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) |
3297c2e6 | 142 | { |
a855039e | 143 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable); |
3297c2e6 JL |
144 | } |
145 | ||
b3ed3a17 | 146 | static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) |
33f469d2 | 147 | { |
a855039e | 148 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable); |
33f469d2 JL |
149 | } |
150 | ||
b0b6ff0b KC |
151 | static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) |
152 | { | |
a855039e | 153 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable); |
b0b6ff0b KC |
154 | } |
155 | ||
fbf05563 TS |
156 | static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) |
157 | { | |
a855039e | 158 | return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable); |
fbf05563 TS |
159 | } |
160 | ||
b3ed3a17 | 161 | static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) |
82260bf3 | 162 | { |
a855039e | 163 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable); |
82260bf3 JL |
164 | } |
165 | ||
b0b6ff0b KC |
166 | static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable) |
167 | { | |
a855039e | 168 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable); |
b0b6ff0b KC |
169 | } |
170 | ||
bca10b90 | 171 | int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable) |
82260bf3 | 172 | { |
a855039e | 173 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable); |
82260bf3 JL |
174 | } |
175 | ||
b3ed3a17 | 176 | static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) |
82260bf3 | 177 | { |
a855039e | 178 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable); |
82260bf3 JL |
179 | } |
180 | ||
2bc02c0d | 181 | int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) |
82260bf3 | 182 | { |
a855039e | 183 | return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable); |
82260bf3 JL |
184 | } |
185 | ||
2bc02c0d | 186 | int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) |
340ea1ef | 187 | { |
a855039e | 188 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable); |
340ea1ef JL |
189 | } |
190 | ||
b3ed3a17 | 191 | static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable) |
5a847b4a | 192 | { |
a855039e | 193 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable); |
5a847b4a JL |
194 | } |
195 | ||
b3ed3a17 | 196 | static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) |
82260bf3 | 197 | { |
a855039e | 198 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable); |
82260bf3 JL |
199 | } |
200 | ||
bca10b90 KC |
201 | int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable) |
202 | { | |
203 | return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable); | |
204 | } | |
205 | ||
fbf05563 TS |
206 | static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) |
207 | { | |
208 | return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); | |
209 | } | |
210 | ||
211 | static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) | |
212 | { | |
213 | return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); | |
214 | } | |
215 | ||
c8bef140 CY |
216 | /* Core list of CMU_CPU side */ |
217 | ||
a855039e | 218 | static struct clksrc_clk exynos4_clk_mout_apll = { |
c8bef140 CY |
219 | .clk = { |
220 | .name = "mout_apll", | |
c8bef140 | 221 | }, |
ce9c00ee | 222 | .sources = &clk_src_apll, |
a855039e | 223 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 }, |
3ff31020 JL |
224 | }; |
225 | ||
a855039e | 226 | static struct clksrc_clk exynos4_clk_sclk_apll = { |
3ff31020 JL |
227 | .clk = { |
228 | .name = "sclk_apll", | |
a855039e | 229 | .parent = &exynos4_clk_mout_apll.clk, |
3ff31020 | 230 | }, |
a855039e | 231 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 }, |
c8bef140 CY |
232 | }; |
233 | ||
a855039e | 234 | static struct clksrc_clk exynos4_clk_mout_epll = { |
c8bef140 CY |
235 | .clk = { |
236 | .name = "mout_epll", | |
c8bef140 | 237 | }, |
ce9c00ee | 238 | .sources = &clk_src_epll, |
a855039e | 239 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 }, |
c8bef140 CY |
240 | }; |
241 | ||
a855039e | 242 | struct clksrc_clk exynos4_clk_mout_mpll = { |
ce9c00ee | 243 | .clk = { |
c8bef140 | 244 | .name = "mout_mpll", |
c8bef140 | 245 | }, |
ce9c00ee | 246 | .sources = &clk_src_mpll, |
2bc02c0d KK |
247 | |
248 | /* reg_src will be added in each SoCs' clock */ | |
c8bef140 CY |
249 | }; |
250 | ||
a855039e KK |
251 | static struct clk *exynos4_clkset_moutcore_list[] = { |
252 | [0] = &exynos4_clk_mout_apll.clk, | |
253 | [1] = &exynos4_clk_mout_mpll.clk, | |
c8bef140 CY |
254 | }; |
255 | ||
a855039e KK |
256 | static struct clksrc_sources exynos4_clkset_moutcore = { |
257 | .sources = exynos4_clkset_moutcore_list, | |
258 | .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list), | |
c8bef140 CY |
259 | }; |
260 | ||
a855039e | 261 | static struct clksrc_clk exynos4_clk_moutcore = { |
c8bef140 CY |
262 | .clk = { |
263 | .name = "moutcore", | |
c8bef140 | 264 | }, |
a855039e KK |
265 | .sources = &exynos4_clkset_moutcore, |
266 | .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 }, | |
c8bef140 CY |
267 | }; |
268 | ||
a855039e | 269 | static struct clksrc_clk exynos4_clk_coreclk = { |
c8bef140 CY |
270 | .clk = { |
271 | .name = "core_clk", | |
a855039e | 272 | .parent = &exynos4_clk_moutcore.clk, |
c8bef140 | 273 | }, |
a855039e | 274 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 }, |
c8bef140 CY |
275 | }; |
276 | ||
a855039e | 277 | static struct clksrc_clk exynos4_clk_armclk = { |
c8bef140 CY |
278 | .clk = { |
279 | .name = "armclk", | |
a855039e | 280 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 CY |
281 | }, |
282 | }; | |
283 | ||
a855039e | 284 | static struct clksrc_clk exynos4_clk_aclk_corem0 = { |
c8bef140 CY |
285 | .clk = { |
286 | .name = "aclk_corem0", | |
a855039e | 287 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 288 | }, |
a855039e | 289 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
290 | }; |
291 | ||
a855039e | 292 | static struct clksrc_clk exynos4_clk_aclk_cores = { |
c8bef140 CY |
293 | .clk = { |
294 | .name = "aclk_cores", | |
a855039e | 295 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 296 | }, |
a855039e | 297 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 }, |
c8bef140 CY |
298 | }; |
299 | ||
a855039e | 300 | static struct clksrc_clk exynos4_clk_aclk_corem1 = { |
c8bef140 CY |
301 | .clk = { |
302 | .name = "aclk_corem1", | |
a855039e | 303 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 304 | }, |
a855039e | 305 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 }, |
c8bef140 CY |
306 | }; |
307 | ||
a855039e | 308 | static struct clksrc_clk exynos4_clk_periphclk = { |
c8bef140 CY |
309 | .clk = { |
310 | .name = "periphclk", | |
a855039e | 311 | .parent = &exynos4_clk_coreclk.clk, |
c8bef140 | 312 | }, |
a855039e | 313 | .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 }, |
c8bef140 CY |
314 | }; |
315 | ||
c8bef140 CY |
316 | /* Core list of CMU_CORE side */ |
317 | ||
a855039e KK |
318 | static struct clk *exynos4_clkset_corebus_list[] = { |
319 | [0] = &exynos4_clk_mout_mpll.clk, | |
320 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
321 | }; |
322 | ||
a855039e KK |
323 | struct clksrc_sources exynos4_clkset_mout_corebus = { |
324 | .sources = exynos4_clkset_corebus_list, | |
325 | .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list), | |
c8bef140 CY |
326 | }; |
327 | ||
a855039e | 328 | static struct clksrc_clk exynos4_clk_mout_corebus = { |
c8bef140 CY |
329 | .clk = { |
330 | .name = "mout_corebus", | |
c8bef140 | 331 | }, |
a855039e KK |
332 | .sources = &exynos4_clkset_mout_corebus, |
333 | .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 }, | |
c8bef140 CY |
334 | }; |
335 | ||
a855039e | 336 | static struct clksrc_clk exynos4_clk_sclk_dmc = { |
c8bef140 CY |
337 | .clk = { |
338 | .name = "sclk_dmc", | |
a855039e | 339 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 340 | }, |
a855039e | 341 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
c8bef140 CY |
342 | }; |
343 | ||
a855039e | 344 | static struct clksrc_clk exynos4_clk_aclk_cored = { |
c8bef140 CY |
345 | .clk = { |
346 | .name = "aclk_cored", | |
a855039e | 347 | .parent = &exynos4_clk_sclk_dmc.clk, |
c8bef140 | 348 | }, |
a855039e | 349 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
c8bef140 CY |
350 | }; |
351 | ||
a855039e | 352 | static struct clksrc_clk exynos4_clk_aclk_corep = { |
c8bef140 CY |
353 | .clk = { |
354 | .name = "aclk_corep", | |
a855039e | 355 | .parent = &exynos4_clk_aclk_cored.clk, |
c8bef140 | 356 | }, |
a855039e | 357 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
c8bef140 CY |
358 | }; |
359 | ||
a855039e | 360 | static struct clksrc_clk exynos4_clk_aclk_acp = { |
c8bef140 CY |
361 | .clk = { |
362 | .name = "aclk_acp", | |
a855039e | 363 | .parent = &exynos4_clk_mout_corebus.clk, |
c8bef140 | 364 | }, |
a855039e | 365 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
c8bef140 CY |
366 | }; |
367 | ||
a855039e | 368 | static struct clksrc_clk exynos4_clk_pclk_acp = { |
c8bef140 CY |
369 | .clk = { |
370 | .name = "pclk_acp", | |
a855039e | 371 | .parent = &exynos4_clk_aclk_acp.clk, |
c8bef140 | 372 | }, |
a855039e | 373 | .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
c8bef140 CY |
374 | }; |
375 | ||
376 | /* Core list of CMU_TOP side */ | |
377 | ||
a855039e KK |
378 | struct clk *exynos4_clkset_aclk_top_list[] = { |
379 | [0] = &exynos4_clk_mout_mpll.clk, | |
380 | [1] = &exynos4_clk_sclk_apll.clk, | |
c8bef140 CY |
381 | }; |
382 | ||
a855039e KK |
383 | static struct clksrc_sources exynos4_clkset_aclk = { |
384 | .sources = exynos4_clkset_aclk_top_list, | |
385 | .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list), | |
c8bef140 CY |
386 | }; |
387 | ||
a855039e | 388 | static struct clksrc_clk exynos4_clk_aclk_200 = { |
c8bef140 CY |
389 | .clk = { |
390 | .name = "aclk_200", | |
c8bef140 | 391 | }, |
a855039e KK |
392 | .sources = &exynos4_clkset_aclk, |
393 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 }, | |
394 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 }, | |
c8bef140 CY |
395 | }; |
396 | ||
a855039e | 397 | static struct clksrc_clk exynos4_clk_aclk_100 = { |
c8bef140 CY |
398 | .clk = { |
399 | .name = "aclk_100", | |
c8bef140 | 400 | }, |
a855039e KK |
401 | .sources = &exynos4_clkset_aclk, |
402 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 }, | |
403 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 }, | |
c8bef140 CY |
404 | }; |
405 | ||
a855039e | 406 | static struct clksrc_clk exynos4_clk_aclk_160 = { |
c8bef140 CY |
407 | .clk = { |
408 | .name = "aclk_160", | |
c8bef140 | 409 | }, |
a855039e KK |
410 | .sources = &exynos4_clkset_aclk, |
411 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 }, | |
412 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 }, | |
c8bef140 CY |
413 | }; |
414 | ||
a855039e | 415 | struct clksrc_clk exynos4_clk_aclk_133 = { |
c8bef140 CY |
416 | .clk = { |
417 | .name = "aclk_133", | |
c8bef140 | 418 | }, |
a855039e KK |
419 | .sources = &exynos4_clkset_aclk, |
420 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 }, | |
421 | .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 }, | |
c8bef140 CY |
422 | }; |
423 | ||
a855039e | 424 | static struct clk *exynos4_clkset_vpllsrc_list[] = { |
c8bef140 | 425 | [0] = &clk_fin_vpll, |
a855039e | 426 | [1] = &exynos4_clk_sclk_hdmi27m, |
c8bef140 CY |
427 | }; |
428 | ||
a855039e KK |
429 | static struct clksrc_sources exynos4_clkset_vpllsrc = { |
430 | .sources = exynos4_clkset_vpllsrc_list, | |
431 | .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list), | |
c8bef140 CY |
432 | }; |
433 | ||
a855039e | 434 | static struct clksrc_clk exynos4_clk_vpllsrc = { |
c8bef140 CY |
435 | .clk = { |
436 | .name = "vpll_src", | |
b3ed3a17 | 437 | .enable = exynos4_clksrc_mask_top_ctrl, |
37e01729 | 438 | .ctrlbit = (1 << 0), |
c8bef140 | 439 | }, |
a855039e KK |
440 | .sources = &exynos4_clkset_vpllsrc, |
441 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 }, | |
c8bef140 CY |
442 | }; |
443 | ||
a855039e KK |
444 | static struct clk *exynos4_clkset_sclk_vpll_list[] = { |
445 | [0] = &exynos4_clk_vpllsrc.clk, | |
c8bef140 CY |
446 | [1] = &clk_fout_vpll, |
447 | }; | |
448 | ||
a855039e KK |
449 | static struct clksrc_sources exynos4_clkset_sclk_vpll = { |
450 | .sources = exynos4_clkset_sclk_vpll_list, | |
451 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list), | |
c8bef140 CY |
452 | }; |
453 | ||
a855039e | 454 | static struct clksrc_clk exynos4_clk_sclk_vpll = { |
c8bef140 CY |
455 | .clk = { |
456 | .name = "sclk_vpll", | |
c8bef140 | 457 | }, |
a855039e KK |
458 | .sources = &exynos4_clkset_sclk_vpll, |
459 | .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 }, | |
c8bef140 CY |
460 | }; |
461 | ||
a855039e | 462 | static struct clk exynos4_init_clocks_off[] = { |
c8bef140 CY |
463 | { |
464 | .name = "timers", | |
a855039e | 465 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 466 | .enable = exynos4_clk_ip_peril_ctrl, |
c8bef140 | 467 | .ctrlbit = (1<<24), |
82260bf3 JL |
468 | }, { |
469 | .name = "csis", | |
badc4f2d | 470 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 471 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
472 | .ctrlbit = (1 << 4), |
473 | }, { | |
474 | .name = "csis", | |
badc4f2d | 475 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 476 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 477 | .ctrlbit = (1 << 5), |
853a0231 AB |
478 | }, { |
479 | .name = "jpeg", | |
480 | .id = 0, | |
481 | .enable = exynos4_clk_ip_cam_ctrl, | |
482 | .ctrlbit = (1 << 6), | |
82260bf3 JL |
483 | }, { |
484 | .name = "fimc", | |
badc4f2d | 485 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 486 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
487 | .ctrlbit = (1 << 0), |
488 | }, { | |
489 | .name = "fimc", | |
badc4f2d | 490 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 491 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
492 | .ctrlbit = (1 << 1), |
493 | }, { | |
494 | .name = "fimc", | |
badc4f2d | 495 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 496 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 JL |
497 | .ctrlbit = (1 << 2), |
498 | }, { | |
499 | .name = "fimc", | |
badc4f2d | 500 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 501 | .enable = exynos4_clk_ip_cam_ctrl, |
82260bf3 | 502 | .ctrlbit = (1 << 3), |
1f926c48 CK |
503 | }, { |
504 | .name = "tsi", | |
505 | .enable = exynos4_clk_ip_fsys_ctrl, | |
506 | .ctrlbit = (1 << 4), | |
340ea1ef JL |
507 | }, { |
508 | .name = "hsmmc", | |
8482c81c | 509 | .devname = "exynos4-sdhci.0", |
a855039e | 510 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 511 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
512 | .ctrlbit = (1 << 5), |
513 | }, { | |
514 | .name = "hsmmc", | |
8482c81c | 515 | .devname = "exynos4-sdhci.1", |
a855039e | 516 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 517 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
518 | .ctrlbit = (1 << 6), |
519 | }, { | |
520 | .name = "hsmmc", | |
8482c81c | 521 | .devname = "exynos4-sdhci.2", |
a855039e | 522 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 523 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
524 | .ctrlbit = (1 << 7), |
525 | }, { | |
526 | .name = "hsmmc", | |
8482c81c | 527 | .devname = "exynos4-sdhci.3", |
a855039e | 528 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 529 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef JL |
530 | .ctrlbit = (1 << 8), |
531 | }, { | |
badc4f2d | 532 | .name = "dwmmc", |
a855039e | 533 | .parent = &exynos4_clk_aclk_133.clk, |
b3ed3a17 | 534 | .enable = exynos4_clk_ip_fsys_ctrl, |
340ea1ef | 535 | .ctrlbit = (1 << 9), |
1f926c48 CK |
536 | }, { |
537 | .name = "onenand", | |
538 | .enable = exynos4_clk_ip_fsys_ctrl, | |
539 | .ctrlbit = (1 << 15), | |
540 | }, { | |
541 | .name = "nfcon", | |
542 | .enable = exynos4_clk_ip_fsys_ctrl, | |
543 | .ctrlbit = (1 << 16), | |
3055c6da | 544 | }, { |
fbf05563 TS |
545 | .name = "dac", |
546 | .devname = "s5p-sdo", | |
547 | .enable = exynos4_clk_ip_tv_ctrl, | |
548 | .ctrlbit = (1 << 2), | |
549 | }, { | |
550 | .name = "mixer", | |
551 | .devname = "s5p-mixer", | |
552 | .enable = exynos4_clk_ip_tv_ctrl, | |
553 | .ctrlbit = (1 << 1), | |
554 | }, { | |
555 | .name = "vp", | |
556 | .devname = "s5p-mixer", | |
557 | .enable = exynos4_clk_ip_tv_ctrl, | |
558 | .ctrlbit = (1 << 0), | |
559 | }, { | |
560 | .name = "hdmi", | |
561 | .devname = "exynos4-hdmi", | |
562 | .enable = exynos4_clk_ip_tv_ctrl, | |
563 | .ctrlbit = (1 << 3), | |
564 | }, { | |
565 | .name = "hdmiphy", | |
566 | .devname = "exynos4-hdmi", | |
567 | .enable = exynos4_clk_hdmiphy_ctrl, | |
568 | .ctrlbit = (1 << 0), | |
569 | }, { | |
570 | .name = "dacphy", | |
571 | .devname = "s5p-sdo", | |
572 | .enable = exynos4_clk_dac_ctrl, | |
573 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
574 | }, { |
575 | .name = "adc", | |
b3ed3a17 | 576 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 577 | .ctrlbit = (1 << 15), |
f9d7bcbc NKC |
578 | }, { |
579 | .name = "keypad", | |
f9d7bcbc NKC |
580 | .enable = exynos4_clk_ip_perir_ctrl, |
581 | .ctrlbit = (1 << 16), | |
cdff6e6f CY |
582 | }, { |
583 | .name = "rtc", | |
b3ed3a17 | 584 | .enable = exynos4_clk_ip_perir_ctrl, |
cdff6e6f | 585 | .ctrlbit = (1 << 15), |
82260bf3 JL |
586 | }, { |
587 | .name = "watchdog", | |
a855039e | 588 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 589 | .enable = exynos4_clk_ip_perir_ctrl, |
82260bf3 JL |
590 | .ctrlbit = (1 << 14), |
591 | }, { | |
592 | .name = "usbhost", | |
b3ed3a17 | 593 | .enable = exynos4_clk_ip_fsys_ctrl , |
82260bf3 JL |
594 | .ctrlbit = (1 << 12), |
595 | }, { | |
596 | .name = "otg", | |
b3ed3a17 | 597 | .enable = exynos4_clk_ip_fsys_ctrl, |
82260bf3 JL |
598 | .ctrlbit = (1 << 13), |
599 | }, { | |
600 | .name = "spi", | |
a5238e36 | 601 | .devname = "exynos4210-spi.0", |
b3ed3a17 | 602 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
603 | .ctrlbit = (1 << 16), |
604 | }, { | |
605 | .name = "spi", | |
a5238e36 | 606 | .devname = "exynos4210-spi.1", |
b3ed3a17 | 607 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
608 | .ctrlbit = (1 << 17), |
609 | }, { | |
610 | .name = "spi", | |
a5238e36 | 611 | .devname = "exynos4210-spi.2", |
b3ed3a17 | 612 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 613 | .ctrlbit = (1 << 18), |
2d27043f JB |
614 | }, { |
615 | .name = "iis", | |
badc4f2d | 616 | .devname = "samsung-i2s.1", |
b3ed3a17 | 617 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f JB |
618 | .ctrlbit = (1 << 20), |
619 | }, { | |
620 | .name = "iis", | |
badc4f2d | 621 | .devname = "samsung-i2s.2", |
b3ed3a17 | 622 | .enable = exynos4_clk_ip_peril_ctrl, |
2d27043f | 623 | .ctrlbit = (1 << 21), |
377acfbb CK |
624 | }, { |
625 | .name = "pcm", | |
626 | .devname = "samsung-pcm.1", | |
627 | .enable = exynos4_clk_ip_peril_ctrl, | |
628 | .ctrlbit = (1 << 22), | |
629 | }, { | |
630 | .name = "pcm", | |
631 | .devname = "samsung-pcm.2", | |
632 | .enable = exynos4_clk_ip_peril_ctrl, | |
633 | .ctrlbit = (1 << 23), | |
634 | }, { | |
635 | .name = "slimbus", | |
636 | .enable = exynos4_clk_ip_peril_ctrl, | |
637 | .ctrlbit = (1 << 25), | |
638 | }, { | |
639 | .name = "spdif", | |
640 | .devname = "samsung-spdif", | |
641 | .enable = exynos4_clk_ip_peril_ctrl, | |
642 | .ctrlbit = (1 << 26), | |
aa227557 JB |
643 | }, { |
644 | .name = "ac97", | |
af8a9f63 | 645 | .devname = "samsung-ac97", |
b3ed3a17 | 646 | .enable = exynos4_clk_ip_peril_ctrl, |
aa227557 | 647 | .ctrlbit = (1 << 27), |
0f75a96b KD |
648 | }, { |
649 | .name = "mfc", | |
650 | .devname = "s5p-mfc", | |
651 | .enable = exynos4_clk_ip_mfc_ctrl, | |
652 | .ctrlbit = (1 << 0), | |
82260bf3 JL |
653 | }, { |
654 | .name = "i2c", | |
badc4f2d | 655 | .devname = "s3c2440-i2c.0", |
a855039e | 656 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 657 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
658 | .ctrlbit = (1 << 6), |
659 | }, { | |
660 | .name = "i2c", | |
badc4f2d | 661 | .devname = "s3c2440-i2c.1", |
a855039e | 662 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 663 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
664 | .ctrlbit = (1 << 7), |
665 | }, { | |
666 | .name = "i2c", | |
badc4f2d | 667 | .devname = "s3c2440-i2c.2", |
a855039e | 668 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 669 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
670 | .ctrlbit = (1 << 8), |
671 | }, { | |
672 | .name = "i2c", | |
badc4f2d | 673 | .devname = "s3c2440-i2c.3", |
a855039e | 674 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 675 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
676 | .ctrlbit = (1 << 9), |
677 | }, { | |
678 | .name = "i2c", | |
badc4f2d | 679 | .devname = "s3c2440-i2c.4", |
a855039e | 680 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 681 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
682 | .ctrlbit = (1 << 10), |
683 | }, { | |
684 | .name = "i2c", | |
badc4f2d | 685 | .devname = "s3c2440-i2c.5", |
a855039e | 686 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 687 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
688 | .ctrlbit = (1 << 11), |
689 | }, { | |
690 | .name = "i2c", | |
badc4f2d | 691 | .devname = "s3c2440-i2c.6", |
a855039e | 692 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 693 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 JL |
694 | .ctrlbit = (1 << 12), |
695 | }, { | |
696 | .name = "i2c", | |
badc4f2d | 697 | .devname = "s3c2440-i2c.7", |
a855039e | 698 | .parent = &exynos4_clk_aclk_100.clk, |
b3ed3a17 | 699 | .enable = exynos4_clk_ip_peril_ctrl, |
82260bf3 | 700 | .ctrlbit = (1 << 13), |
c40e7e0d TS |
701 | }, { |
702 | .name = "i2c", | |
703 | .devname = "s3c2440-hdmiphy-i2c", | |
a855039e | 704 | .parent = &exynos4_clk_aclk_100.clk, |
c40e7e0d TS |
705 | .enable = exynos4_clk_ip_peril_ctrl, |
706 | .ctrlbit = (1 << 14), | |
b0b6ff0b | 707 | }, { |
bca10b90 KC |
708 | .name = SYSMMU_CLOCK_NAME, |
709 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), | |
710 | .enable = exynos4_clk_ip_mfc_ctrl, | |
711 | .ctrlbit = (1 << 1), | |
712 | }, { | |
713 | .name = SYSMMU_CLOCK_NAME, | |
714 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1), | |
715 | .enable = exynos4_clk_ip_mfc_ctrl, | |
716 | .ctrlbit = (1 << 2), | |
717 | }, { | |
718 | .name = SYSMMU_CLOCK_NAME, | |
719 | .devname = SYSMMU_CLOCK_DEVNAME(tv, 2), | |
720 | .enable = exynos4_clk_ip_tv_ctrl, | |
721 | .ctrlbit = (1 << 4), | |
722 | }, { | |
723 | .name = SYSMMU_CLOCK_NAME, | |
724 | .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3), | |
725 | .enable = exynos4_clk_ip_cam_ctrl, | |
726 | .ctrlbit = (1 << 11), | |
727 | }, { | |
728 | .name = SYSMMU_CLOCK_NAME, | |
729 | .devname = SYSMMU_CLOCK_DEVNAME(rot, 4), | |
b0b6ff0b | 730 | .enable = exynos4_clk_ip_image_ctrl, |
bca10b90 | 731 | .ctrlbit = (1 << 4), |
b0b6ff0b | 732 | }, { |
bca10b90 KC |
733 | .name = SYSMMU_CLOCK_NAME, |
734 | .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5), | |
b0b6ff0b KC |
735 | .enable = exynos4_clk_ip_cam_ctrl, |
736 | .ctrlbit = (1 << 7), | |
737 | }, { | |
bca10b90 KC |
738 | .name = SYSMMU_CLOCK_NAME, |
739 | .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6), | |
b0b6ff0b KC |
740 | .enable = exynos4_clk_ip_cam_ctrl, |
741 | .ctrlbit = (1 << 8), | |
742 | }, { | |
bca10b90 KC |
743 | .name = SYSMMU_CLOCK_NAME, |
744 | .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7), | |
b0b6ff0b KC |
745 | .enable = exynos4_clk_ip_cam_ctrl, |
746 | .ctrlbit = (1 << 9), | |
747 | }, { | |
bca10b90 KC |
748 | .name = SYSMMU_CLOCK_NAME, |
749 | .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8), | |
b0b6ff0b KC |
750 | .enable = exynos4_clk_ip_cam_ctrl, |
751 | .ctrlbit = (1 << 10), | |
752 | }, { | |
bca10b90 KC |
753 | .name = SYSMMU_CLOCK_NAME, |
754 | .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10), | |
b0b6ff0b KC |
755 | .enable = exynos4_clk_ip_lcd0_ctrl, |
756 | .ctrlbit = (1 << 4), | |
b0b6ff0b | 757 | } |
c8bef140 CY |
758 | }; |
759 | ||
a855039e | 760 | static struct clk exynos4_init_clocks_on[] = { |
5a847b4a JL |
761 | { |
762 | .name = "uart", | |
badc4f2d | 763 | .devname = "s5pv210-uart.0", |
b3ed3a17 | 764 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
765 | .ctrlbit = (1 << 0), |
766 | }, { | |
767 | .name = "uart", | |
badc4f2d | 768 | .devname = "s5pv210-uart.1", |
b3ed3a17 | 769 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
770 | .ctrlbit = (1 << 1), |
771 | }, { | |
772 | .name = "uart", | |
badc4f2d | 773 | .devname = "s5pv210-uart.2", |
b3ed3a17 | 774 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
775 | .ctrlbit = (1 << 2), |
776 | }, { | |
777 | .name = "uart", | |
badc4f2d | 778 | .devname = "s5pv210-uart.3", |
b3ed3a17 | 779 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
780 | .ctrlbit = (1 << 3), |
781 | }, { | |
782 | .name = "uart", | |
badc4f2d | 783 | .devname = "s5pv210-uart.4", |
b3ed3a17 | 784 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
785 | .ctrlbit = (1 << 4), |
786 | }, { | |
787 | .name = "uart", | |
badc4f2d | 788 | .devname = "s5pv210-uart.5", |
b3ed3a17 | 789 | .enable = exynos4_clk_ip_peril_ctrl, |
5a847b4a JL |
790 | .ctrlbit = (1 << 5), |
791 | } | |
c8bef140 CY |
792 | }; |
793 | ||
a855039e | 794 | static struct clk exynos4_clk_pdma0 = { |
66fdb29d TA |
795 | .name = "dma", |
796 | .devname = "dma-pl330.0", | |
797 | .enable = exynos4_clk_ip_fsys_ctrl, | |
798 | .ctrlbit = (1 << 0), | |
799 | }; | |
800 | ||
a855039e | 801 | static struct clk exynos4_clk_pdma1 = { |
66fdb29d TA |
802 | .name = "dma", |
803 | .devname = "dma-pl330.1", | |
804 | .enable = exynos4_clk_ip_fsys_ctrl, | |
805 | .ctrlbit = (1 << 1), | |
806 | }; | |
807 | ||
9ed76e03 BK |
808 | static struct clk exynos4_clk_mdma1 = { |
809 | .name = "dma", | |
810 | .devname = "dma-pl330.2", | |
811 | .enable = exynos4_clk_ip_image_ctrl, | |
812 | .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), | |
813 | }; | |
814 | ||
79025466 TB |
815 | static struct clk exynos4_clk_fimd0 = { |
816 | .name = "fimd", | |
817 | .devname = "exynos4-fb.0", | |
818 | .enable = exynos4_clk_ip_lcd0_ctrl, | |
819 | .ctrlbit = (1 << 0), | |
820 | }; | |
821 | ||
a855039e | 822 | struct clk *exynos4_clkset_group_list[] = { |
c8bef140 CY |
823 | [0] = &clk_ext_xtal_mux, |
824 | [1] = &clk_xusbxti, | |
a855039e KK |
825 | [2] = &exynos4_clk_sclk_hdmi27m, |
826 | [3] = &exynos4_clk_sclk_usbphy0, | |
827 | [4] = &exynos4_clk_sclk_usbphy1, | |
828 | [5] = &exynos4_clk_sclk_hdmiphy, | |
829 | [6] = &exynos4_clk_mout_mpll.clk, | |
830 | [7] = &exynos4_clk_mout_epll.clk, | |
831 | [8] = &exynos4_clk_sclk_vpll.clk, | |
c8bef140 CY |
832 | }; |
833 | ||
a855039e KK |
834 | struct clksrc_sources exynos4_clkset_group = { |
835 | .sources = exynos4_clkset_group_list, | |
836 | .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list), | |
c8bef140 CY |
837 | }; |
838 | ||
a855039e KK |
839 | static struct clk *exynos4_clkset_mout_g2d0_list[] = { |
840 | [0] = &exynos4_clk_mout_mpll.clk, | |
841 | [1] = &exynos4_clk_sclk_apll.clk, | |
06cba8d5 JL |
842 | }; |
843 | ||
8bf56466 | 844 | struct clksrc_sources exynos4_clkset_mout_g2d0 = { |
a855039e KK |
845 | .sources = exynos4_clkset_mout_g2d0_list, |
846 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list), | |
06cba8d5 JL |
847 | }; |
848 | ||
a855039e KK |
849 | static struct clk *exynos4_clkset_mout_g2d1_list[] = { |
850 | [0] = &exynos4_clk_mout_epll.clk, | |
851 | [1] = &exynos4_clk_sclk_vpll.clk, | |
06cba8d5 JL |
852 | }; |
853 | ||
8bf56466 | 854 | struct clksrc_sources exynos4_clkset_mout_g2d1 = { |
a855039e KK |
855 | .sources = exynos4_clkset_mout_g2d1_list, |
856 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list), | |
06cba8d5 JL |
857 | }; |
858 | ||
a855039e KK |
859 | static struct clk *exynos4_clkset_mout_mfc0_list[] = { |
860 | [0] = &exynos4_clk_mout_mpll.clk, | |
861 | [1] = &exynos4_clk_sclk_apll.clk, | |
0f75a96b KD |
862 | }; |
863 | ||
a855039e KK |
864 | static struct clksrc_sources exynos4_clkset_mout_mfc0 = { |
865 | .sources = exynos4_clkset_mout_mfc0_list, | |
866 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list), | |
0f75a96b KD |
867 | }; |
868 | ||
a855039e | 869 | static struct clksrc_clk exynos4_clk_mout_mfc0 = { |
0f75a96b KD |
870 | .clk = { |
871 | .name = "mout_mfc0", | |
872 | }, | |
a855039e KK |
873 | .sources = &exynos4_clkset_mout_mfc0, |
874 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 }, | |
0f75a96b KD |
875 | }; |
876 | ||
a855039e KK |
877 | static struct clk *exynos4_clkset_mout_mfc1_list[] = { |
878 | [0] = &exynos4_clk_mout_epll.clk, | |
879 | [1] = &exynos4_clk_sclk_vpll.clk, | |
0f75a96b KD |
880 | }; |
881 | ||
a855039e KK |
882 | static struct clksrc_sources exynos4_clkset_mout_mfc1 = { |
883 | .sources = exynos4_clkset_mout_mfc1_list, | |
884 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list), | |
0f75a96b KD |
885 | }; |
886 | ||
a855039e | 887 | static struct clksrc_clk exynos4_clk_mout_mfc1 = { |
0f75a96b KD |
888 | .clk = { |
889 | .name = "mout_mfc1", | |
890 | }, | |
a855039e KK |
891 | .sources = &exynos4_clkset_mout_mfc1, |
892 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 }, | |
0f75a96b KD |
893 | }; |
894 | ||
a855039e KK |
895 | static struct clk *exynos4_clkset_mout_mfc_list[] = { |
896 | [0] = &exynos4_clk_mout_mfc0.clk, | |
897 | [1] = &exynos4_clk_mout_mfc1.clk, | |
0f75a96b KD |
898 | }; |
899 | ||
a855039e KK |
900 | static struct clksrc_sources exynos4_clkset_mout_mfc = { |
901 | .sources = exynos4_clkset_mout_mfc_list, | |
902 | .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list), | |
0f75a96b KD |
903 | }; |
904 | ||
a855039e KK |
905 | static struct clk *exynos4_clkset_sclk_dac_list[] = { |
906 | [0] = &exynos4_clk_sclk_vpll.clk, | |
907 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
908 | }; |
909 | ||
a855039e KK |
910 | static struct clksrc_sources exynos4_clkset_sclk_dac = { |
911 | .sources = exynos4_clkset_sclk_dac_list, | |
912 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list), | |
fbf05563 TS |
913 | }; |
914 | ||
a855039e | 915 | static struct clksrc_clk exynos4_clk_sclk_dac = { |
fbf05563 TS |
916 | .clk = { |
917 | .name = "sclk_dac", | |
918 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
919 | .ctrlbit = (1 << 8), | |
920 | }, | |
a855039e KK |
921 | .sources = &exynos4_clkset_sclk_dac, |
922 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 }, | |
fbf05563 TS |
923 | }; |
924 | ||
a855039e | 925 | static struct clksrc_clk exynos4_clk_sclk_pixel = { |
fbf05563 TS |
926 | .clk = { |
927 | .name = "sclk_pixel", | |
a855039e | 928 | .parent = &exynos4_clk_sclk_vpll.clk, |
fbf05563 | 929 | }, |
a855039e | 930 | .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 }, |
fbf05563 TS |
931 | }; |
932 | ||
a855039e KK |
933 | static struct clk *exynos4_clkset_sclk_hdmi_list[] = { |
934 | [0] = &exynos4_clk_sclk_pixel.clk, | |
935 | [1] = &exynos4_clk_sclk_hdmiphy, | |
fbf05563 TS |
936 | }; |
937 | ||
a855039e KK |
938 | static struct clksrc_sources exynos4_clkset_sclk_hdmi = { |
939 | .sources = exynos4_clkset_sclk_hdmi_list, | |
940 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list), | |
fbf05563 TS |
941 | }; |
942 | ||
a855039e | 943 | static struct clksrc_clk exynos4_clk_sclk_hdmi = { |
fbf05563 TS |
944 | .clk = { |
945 | .name = "sclk_hdmi", | |
946 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
947 | .ctrlbit = (1 << 0), | |
948 | }, | |
a855039e KK |
949 | .sources = &exynos4_clkset_sclk_hdmi, |
950 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 }, | |
fbf05563 TS |
951 | }; |
952 | ||
a855039e KK |
953 | static struct clk *exynos4_clkset_sclk_mixer_list[] = { |
954 | [0] = &exynos4_clk_sclk_dac.clk, | |
955 | [1] = &exynos4_clk_sclk_hdmi.clk, | |
fbf05563 TS |
956 | }; |
957 | ||
a855039e KK |
958 | static struct clksrc_sources exynos4_clkset_sclk_mixer = { |
959 | .sources = exynos4_clkset_sclk_mixer_list, | |
960 | .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list), | |
fbf05563 TS |
961 | }; |
962 | ||
a855039e | 963 | static struct clksrc_clk exynos4_clk_sclk_mixer = { |
ce9c00ee | 964 | .clk = { |
fbf05563 TS |
965 | .name = "sclk_mixer", |
966 | .enable = exynos4_clksrc_mask_tv_ctrl, | |
967 | .ctrlbit = (1 << 4), | |
968 | }, | |
a855039e KK |
969 | .sources = &exynos4_clkset_sclk_mixer, |
970 | .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 }, | |
fbf05563 TS |
971 | }; |
972 | ||
a855039e KK |
973 | static struct clksrc_clk *exynos4_sclk_tv[] = { |
974 | &exynos4_clk_sclk_dac, | |
975 | &exynos4_clk_sclk_pixel, | |
976 | &exynos4_clk_sclk_hdmi, | |
977 | &exynos4_clk_sclk_mixer, | |
fbf05563 TS |
978 | }; |
979 | ||
a855039e | 980 | static struct clksrc_clk exynos4_clk_dout_mmc0 = { |
ce9c00ee | 981 | .clk = { |
340ea1ef | 982 | .name = "dout_mmc0", |
340ea1ef | 983 | }, |
a855039e KK |
984 | .sources = &exynos4_clkset_group, |
985 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 }, | |
986 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 }, | |
340ea1ef JL |
987 | }; |
988 | ||
a855039e | 989 | static struct clksrc_clk exynos4_clk_dout_mmc1 = { |
ce9c00ee | 990 | .clk = { |
340ea1ef | 991 | .name = "dout_mmc1", |
340ea1ef | 992 | }, |
a855039e KK |
993 | .sources = &exynos4_clkset_group, |
994 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 }, | |
995 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 }, | |
340ea1ef JL |
996 | }; |
997 | ||
a855039e | 998 | static struct clksrc_clk exynos4_clk_dout_mmc2 = { |
ce9c00ee | 999 | .clk = { |
340ea1ef | 1000 | .name = "dout_mmc2", |
340ea1ef | 1001 | }, |
a855039e KK |
1002 | .sources = &exynos4_clkset_group, |
1003 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 }, | |
1004 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1005 | }; |
1006 | ||
a855039e | 1007 | static struct clksrc_clk exynos4_clk_dout_mmc3 = { |
ce9c00ee | 1008 | .clk = { |
340ea1ef | 1009 | .name = "dout_mmc3", |
340ea1ef | 1010 | }, |
a855039e KK |
1011 | .sources = &exynos4_clkset_group, |
1012 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 }, | |
1013 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 }, | |
340ea1ef JL |
1014 | }; |
1015 | ||
a855039e | 1016 | static struct clksrc_clk exynos4_clk_dout_mmc4 = { |
340ea1ef JL |
1017 | .clk = { |
1018 | .name = "dout_mmc4", | |
340ea1ef | 1019 | }, |
a855039e KK |
1020 | .sources = &exynos4_clkset_group, |
1021 | .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 }, | |
1022 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 }, | |
340ea1ef JL |
1023 | }; |
1024 | ||
a855039e | 1025 | static struct clksrc_clk exynos4_clksrcs[] = { |
c8bef140 | 1026 | { |
ce9c00ee | 1027 | .clk = { |
c8bef140 | 1028 | .name = "sclk_pwm", |
b3ed3a17 | 1029 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
c8bef140 CY |
1030 | .ctrlbit = (1 << 24), |
1031 | }, | |
a855039e KK |
1032 | .sources = &exynos4_clkset_group, |
1033 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 }, | |
1034 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 }, | |
33f469d2 | 1035 | }, { |
ce9c00ee | 1036 | .clk = { |
33f469d2 | 1037 | .name = "sclk_csis", |
badc4f2d | 1038 | .devname = "s5p-mipi-csis.0", |
b3ed3a17 | 1039 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1040 | .ctrlbit = (1 << 24), |
1041 | }, | |
a855039e KK |
1042 | .sources = &exynos4_clkset_group, |
1043 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 }, | |
1044 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 }, | |
33f469d2 | 1045 | }, { |
ce9c00ee | 1046 | .clk = { |
33f469d2 | 1047 | .name = "sclk_csis", |
badc4f2d | 1048 | .devname = "s5p-mipi-csis.1", |
b3ed3a17 | 1049 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1050 | .ctrlbit = (1 << 28), |
1051 | }, | |
a855039e KK |
1052 | .sources = &exynos4_clkset_group, |
1053 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 }, | |
1054 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 }, | |
33f469d2 | 1055 | }, { |
ce9c00ee | 1056 | .clk = { |
00aaad22 | 1057 | .name = "sclk_cam0", |
b3ed3a17 | 1058 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1059 | .ctrlbit = (1 << 16), |
1060 | }, | |
a855039e KK |
1061 | .sources = &exynos4_clkset_group, |
1062 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 }, | |
1063 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 }, | |
33f469d2 | 1064 | }, { |
ce9c00ee | 1065 | .clk = { |
00aaad22 | 1066 | .name = "sclk_cam1", |
b3ed3a17 | 1067 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1068 | .ctrlbit = (1 << 20), |
1069 | }, | |
a855039e KK |
1070 | .sources = &exynos4_clkset_group, |
1071 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 }, | |
1072 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 }, | |
33f469d2 | 1073 | }, { |
ce9c00ee | 1074 | .clk = { |
33f469d2 | 1075 | .name = "sclk_fimc", |
badc4f2d | 1076 | .devname = "exynos4-fimc.0", |
b3ed3a17 | 1077 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1078 | .ctrlbit = (1 << 0), |
1079 | }, | |
a855039e KK |
1080 | .sources = &exynos4_clkset_group, |
1081 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 }, | |
1082 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 }, | |
33f469d2 | 1083 | }, { |
ce9c00ee | 1084 | .clk = { |
33f469d2 | 1085 | .name = "sclk_fimc", |
badc4f2d | 1086 | .devname = "exynos4-fimc.1", |
b3ed3a17 | 1087 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1088 | .ctrlbit = (1 << 4), |
1089 | }, | |
a855039e KK |
1090 | .sources = &exynos4_clkset_group, |
1091 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 }, | |
1092 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 }, | |
33f469d2 | 1093 | }, { |
ce9c00ee | 1094 | .clk = { |
33f469d2 | 1095 | .name = "sclk_fimc", |
badc4f2d | 1096 | .devname = "exynos4-fimc.2", |
b3ed3a17 | 1097 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1098 | .ctrlbit = (1 << 8), |
1099 | }, | |
a855039e KK |
1100 | .sources = &exynos4_clkset_group, |
1101 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 }, | |
1102 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 }, | |
33f469d2 | 1103 | }, { |
ce9c00ee | 1104 | .clk = { |
33f469d2 | 1105 | .name = "sclk_fimc", |
badc4f2d | 1106 | .devname = "exynos4-fimc.3", |
b3ed3a17 | 1107 | .enable = exynos4_clksrc_mask_cam_ctrl, |
33f469d2 JL |
1108 | .ctrlbit = (1 << 12), |
1109 | }, | |
a855039e KK |
1110 | .sources = &exynos4_clkset_group, |
1111 | .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 }, | |
1112 | .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 }, | |
33f469d2 | 1113 | }, { |
ce9c00ee | 1114 | .clk = { |
33f469d2 | 1115 | .name = "sclk_fimd", |
268a7ef2 | 1116 | .devname = "exynos4-fb.0", |
b3ed3a17 | 1117 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
33f469d2 JL |
1118 | .ctrlbit = (1 << 0), |
1119 | }, | |
a855039e KK |
1120 | .sources = &exynos4_clkset_group, |
1121 | .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 }, | |
1122 | .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 }, | |
0f75a96b | 1123 | }, { |
ce9c00ee | 1124 | .clk = { |
0f75a96b KD |
1125 | .name = "sclk_mfc", |
1126 | .devname = "s5p-mfc", | |
1127 | }, | |
a855039e KK |
1128 | .sources = &exynos4_clkset_mout_mfc, |
1129 | .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 }, | |
1130 | .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 }, | |
340ea1ef | 1131 | }, { |
ce9c00ee | 1132 | .clk = { |
badc4f2d | 1133 | .name = "sclk_dwmmc", |
a855039e | 1134 | .parent = &exynos4_clk_dout_mmc4.clk, |
b3ed3a17 | 1135 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
340ea1ef JL |
1136 | .ctrlbit = (1 << 16), |
1137 | }, | |
a855039e | 1138 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 }, |
340ea1ef | 1139 | } |
c8bef140 CY |
1140 | }; |
1141 | ||
a855039e | 1142 | static struct clksrc_clk exynos4_clk_sclk_uart0 = { |
0cfb26e1 TA |
1143 | .clk = { |
1144 | .name = "uclk1", | |
1145 | .devname = "exynos4210-uart.0", | |
1146 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1147 | .ctrlbit = (1 << 0), | |
1148 | }, | |
a855039e KK |
1149 | .sources = &exynos4_clkset_group, |
1150 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 }, | |
1151 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 }, | |
0cfb26e1 TA |
1152 | }; |
1153 | ||
a855039e | 1154 | static struct clksrc_clk exynos4_clk_sclk_uart1 = { |
ce9c00ee | 1155 | .clk = { |
0cfb26e1 TA |
1156 | .name = "uclk1", |
1157 | .devname = "exynos4210-uart.1", | |
1158 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1159 | .ctrlbit = (1 << 4), | |
1160 | }, | |
a855039e KK |
1161 | .sources = &exynos4_clkset_group, |
1162 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 }, | |
1163 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 }, | |
0cfb26e1 TA |
1164 | }; |
1165 | ||
a855039e | 1166 | static struct clksrc_clk exynos4_clk_sclk_uart2 = { |
ce9c00ee | 1167 | .clk = { |
0cfb26e1 TA |
1168 | .name = "uclk1", |
1169 | .devname = "exynos4210-uart.2", | |
1170 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1171 | .ctrlbit = (1 << 8), | |
1172 | }, | |
a855039e KK |
1173 | .sources = &exynos4_clkset_group, |
1174 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 }, | |
1175 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 }, | |
0cfb26e1 TA |
1176 | }; |
1177 | ||
a855039e | 1178 | static struct clksrc_clk exynos4_clk_sclk_uart3 = { |
ce9c00ee | 1179 | .clk = { |
0cfb26e1 TA |
1180 | .name = "uclk1", |
1181 | .devname = "exynos4210-uart.3", | |
1182 | .enable = exynos4_clksrc_mask_peril0_ctrl, | |
1183 | .ctrlbit = (1 << 12), | |
1184 | }, | |
a855039e KK |
1185 | .sources = &exynos4_clkset_group, |
1186 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 }, | |
1187 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 }, | |
0cfb26e1 TA |
1188 | }; |
1189 | ||
a855039e | 1190 | static struct clksrc_clk exynos4_clk_sclk_mmc0 = { |
ce9c00ee | 1191 | .clk = { |
a361d10a | 1192 | .name = "sclk_mmc", |
8482c81c | 1193 | .devname = "exynos4-sdhci.0", |
a855039e | 1194 | .parent = &exynos4_clk_dout_mmc0.clk, |
a361d10a RS |
1195 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1196 | .ctrlbit = (1 << 0), | |
1197 | }, | |
a855039e | 1198 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 }, |
a361d10a RS |
1199 | }; |
1200 | ||
a855039e | 1201 | static struct clksrc_clk exynos4_clk_sclk_mmc1 = { |
ce9c00ee | 1202 | .clk = { |
a361d10a | 1203 | .name = "sclk_mmc", |
8482c81c | 1204 | .devname = "exynos4-sdhci.1", |
a855039e | 1205 | .parent = &exynos4_clk_dout_mmc1.clk, |
a361d10a RS |
1206 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1207 | .ctrlbit = (1 << 4), | |
1208 | }, | |
a855039e | 1209 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 }, |
a361d10a RS |
1210 | }; |
1211 | ||
a855039e | 1212 | static struct clksrc_clk exynos4_clk_sclk_mmc2 = { |
ce9c00ee | 1213 | .clk = { |
a361d10a | 1214 | .name = "sclk_mmc", |
8482c81c | 1215 | .devname = "exynos4-sdhci.2", |
a855039e | 1216 | .parent = &exynos4_clk_dout_mmc2.clk, |
a361d10a RS |
1217 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1218 | .ctrlbit = (1 << 8), | |
1219 | }, | |
a855039e | 1220 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 }, |
a361d10a RS |
1221 | }; |
1222 | ||
a855039e | 1223 | static struct clksrc_clk exynos4_clk_sclk_mmc3 = { |
ce9c00ee | 1224 | .clk = { |
a361d10a | 1225 | .name = "sclk_mmc", |
8482c81c | 1226 | .devname = "exynos4-sdhci.3", |
a855039e | 1227 | .parent = &exynos4_clk_dout_mmc3.clk, |
a361d10a RS |
1228 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1229 | .ctrlbit = (1 << 12), | |
1230 | }, | |
a855039e | 1231 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
a361d10a RS |
1232 | }; |
1233 | ||
46fda15c TA |
1234 | static struct clksrc_clk exynos4_clk_mdout_spi0 = { |
1235 | .clk = { | |
1236 | .name = "mdout_spi", | |
1237 | .devname = "exynos4210-spi.0", | |
1238 | }, | |
1239 | .sources = &exynos4_clkset_group, | |
1240 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | |
1241 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | |
1242 | }; | |
1243 | ||
1244 | static struct clksrc_clk exynos4_clk_mdout_spi1 = { | |
1245 | .clk = { | |
1246 | .name = "mdout_spi", | |
1247 | .devname = "exynos4210-spi.1", | |
1248 | }, | |
1249 | .sources = &exynos4_clkset_group, | |
1250 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | |
1251 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | |
1252 | }; | |
1253 | ||
1254 | static struct clksrc_clk exynos4_clk_mdout_spi2 = { | |
1255 | .clk = { | |
1256 | .name = "mdout_spi", | |
1257 | .devname = "exynos4210-spi.2", | |
1258 | }, | |
1259 | .sources = &exynos4_clkset_group, | |
1260 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | |
1261 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | |
1262 | }; | |
1263 | ||
a855039e | 1264 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { |
ce9c00ee | 1265 | .clk = { |
74ac23a3 | 1266 | .name = "sclk_spi", |
a5238e36 | 1267 | .devname = "exynos4210-spi.0", |
46fda15c | 1268 | .parent = &exynos4_clk_mdout_spi0.clk, |
74ac23a3 | 1269 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1270 | .ctrlbit = (1 << 16), |
74ac23a3 | 1271 | }, |
46fda15c | 1272 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, |
74ac23a3 PV |
1273 | }; |
1274 | ||
a855039e | 1275 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { |
ce9c00ee | 1276 | .clk = { |
74ac23a3 | 1277 | .name = "sclk_spi", |
a5238e36 | 1278 | .devname = "exynos4210-spi.1", |
46fda15c | 1279 | .parent = &exynos4_clk_mdout_spi1.clk, |
74ac23a3 | 1280 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1281 | .ctrlbit = (1 << 20), |
74ac23a3 | 1282 | }, |
46fda15c | 1283 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, |
74ac23a3 PV |
1284 | }; |
1285 | ||
a855039e | 1286 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { |
ce9c00ee | 1287 | .clk = { |
74ac23a3 | 1288 | .name = "sclk_spi", |
a5238e36 | 1289 | .devname = "exynos4210-spi.2", |
46fda15c | 1290 | .parent = &exynos4_clk_mdout_spi2.clk, |
74ac23a3 | 1291 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
ce9c00ee | 1292 | .ctrlbit = (1 << 24), |
74ac23a3 | 1293 | }, |
46fda15c | 1294 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, |
74ac23a3 PV |
1295 | }; |
1296 | ||
c8bef140 | 1297 | /* Clock initialization code */ |
a855039e KK |
1298 | static struct clksrc_clk *exynos4_sysclks[] = { |
1299 | &exynos4_clk_mout_apll, | |
1300 | &exynos4_clk_sclk_apll, | |
1301 | &exynos4_clk_mout_epll, | |
1302 | &exynos4_clk_mout_mpll, | |
1303 | &exynos4_clk_moutcore, | |
1304 | &exynos4_clk_coreclk, | |
1305 | &exynos4_clk_armclk, | |
1306 | &exynos4_clk_aclk_corem0, | |
1307 | &exynos4_clk_aclk_cores, | |
1308 | &exynos4_clk_aclk_corem1, | |
1309 | &exynos4_clk_periphclk, | |
1310 | &exynos4_clk_mout_corebus, | |
1311 | &exynos4_clk_sclk_dmc, | |
1312 | &exynos4_clk_aclk_cored, | |
1313 | &exynos4_clk_aclk_corep, | |
1314 | &exynos4_clk_aclk_acp, | |
1315 | &exynos4_clk_pclk_acp, | |
1316 | &exynos4_clk_vpllsrc, | |
1317 | &exynos4_clk_sclk_vpll, | |
1318 | &exynos4_clk_aclk_200, | |
1319 | &exynos4_clk_aclk_100, | |
1320 | &exynos4_clk_aclk_160, | |
1321 | &exynos4_clk_aclk_133, | |
1322 | &exynos4_clk_dout_mmc0, | |
1323 | &exynos4_clk_dout_mmc1, | |
1324 | &exynos4_clk_dout_mmc2, | |
1325 | &exynos4_clk_dout_mmc3, | |
1326 | &exynos4_clk_dout_mmc4, | |
1327 | &exynos4_clk_mout_mfc0, | |
1328 | &exynos4_clk_mout_mfc1, | |
1329 | }; | |
1330 | ||
1331 | static struct clk *exynos4_clk_cdev[] = { | |
1332 | &exynos4_clk_pdma0, | |
1333 | &exynos4_clk_pdma1, | |
9ed76e03 | 1334 | &exynos4_clk_mdma1, |
79025466 | 1335 | &exynos4_clk_fimd0, |
a855039e KK |
1336 | }; |
1337 | ||
1338 | static struct clksrc_clk *exynos4_clksrc_cdev[] = { | |
1339 | &exynos4_clk_sclk_uart0, | |
1340 | &exynos4_clk_sclk_uart1, | |
1341 | &exynos4_clk_sclk_uart2, | |
1342 | &exynos4_clk_sclk_uart3, | |
1343 | &exynos4_clk_sclk_mmc0, | |
1344 | &exynos4_clk_sclk_mmc1, | |
1345 | &exynos4_clk_sclk_mmc2, | |
1346 | &exynos4_clk_sclk_mmc3, | |
1347 | &exynos4_clk_sclk_spi0, | |
1348 | &exynos4_clk_sclk_spi1, | |
1349 | &exynos4_clk_sclk_spi2, | |
46fda15c TA |
1350 | &exynos4_clk_mdout_spi0, |
1351 | &exynos4_clk_mdout_spi1, | |
1352 | &exynos4_clk_mdout_spi2, | |
0cfb26e1 TA |
1353 | }; |
1354 | ||
1355 | static struct clk_lookup exynos4_clk_lookup[] = { | |
a855039e KK |
1356 | CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), |
1357 | CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), | |
1358 | CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), | |
1359 | CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), | |
8482c81c TA |
1360 | CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), |
1361 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), | |
1362 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), | |
1363 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), | |
79025466 | 1364 | CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), |
a855039e KK |
1365 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
1366 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | |
8f7b1321 | 1367 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), |
a5238e36 TA |
1368 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), |
1369 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), | |
1370 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), | |
0cfb26e1 TA |
1371 | }; |
1372 | ||
877d1b57 JL |
1373 | static int xtal_rate; |
1374 | ||
b3ed3a17 | 1375 | static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) |
877d1b57 | 1376 | { |
2bc02c0d | 1377 | if (soc_is_exynos4210()) |
a855039e | 1378 | return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1379 | pll_4508); |
b88b1cc7 | 1380 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
a855039e | 1381 | return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0)); |
2bc02c0d KK |
1382 | else |
1383 | return 0; | |
877d1b57 JL |
1384 | } |
1385 | ||
b3ed3a17 KK |
1386 | static struct clk_ops exynos4_fout_apll_ops = { |
1387 | .get_rate = exynos4_fout_apll_get_rate, | |
877d1b57 JL |
1388 | }; |
1389 | ||
a855039e | 1390 | static u32 exynos4_vpll_div[][8] = { |
fbf05563 TS |
1391 | { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, |
1392 | { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, | |
1393 | }; | |
1394 | ||
1395 | static unsigned long exynos4_vpll_get_rate(struct clk *clk) | |
1396 | { | |
1397 | return clk->rate; | |
1398 | } | |
1399 | ||
1400 | static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) | |
1401 | { | |
1402 | unsigned int vpll_con0, vpll_con1 = 0; | |
1403 | unsigned int i; | |
1404 | ||
1405 | /* Return if nothing changed */ | |
1406 | if (clk->rate == rate) | |
1407 | return 0; | |
1408 | ||
a855039e | 1409 | vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0); |
fbf05563 TS |
1410 | vpll_con0 &= ~(0x1 << 27 | \ |
1411 | PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ | |
1412 | PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ | |
1413 | PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); | |
1414 | ||
a855039e | 1415 | vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1); |
fbf05563 TS |
1416 | vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ |
1417 | PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ | |
1418 | PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); | |
1419 | ||
a855039e KK |
1420 | for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) { |
1421 | if (exynos4_vpll_div[i][0] == rate) { | |
1422 | vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT; | |
1423 | vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT; | |
1424 | vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT; | |
1425 | vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT; | |
1426 | vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT; | |
1427 | vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT; | |
1428 | vpll_con0 |= exynos4_vpll_div[i][7] << 27; | |
fbf05563 TS |
1429 | break; |
1430 | } | |
1431 | } | |
1432 | ||
a855039e | 1433 | if (i == ARRAY_SIZE(exynos4_vpll_div)) { |
fbf05563 TS |
1434 | printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", |
1435 | __func__); | |
1436 | return -EINVAL; | |
1437 | } | |
1438 | ||
a855039e KK |
1439 | __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0); |
1440 | __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1); | |
fbf05563 TS |
1441 | |
1442 | /* Wait for VPLL lock */ | |
a855039e | 1443 | while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) |
fbf05563 TS |
1444 | continue; |
1445 | ||
1446 | clk->rate = rate; | |
1447 | return 0; | |
1448 | } | |
1449 | ||
1450 | static struct clk_ops exynos4_vpll_ops = { | |
1451 | .get_rate = exynos4_vpll_get_rate, | |
1452 | .set_rate = exynos4_vpll_set_rate, | |
1453 | }; | |
1454 | ||
b3ed3a17 | 1455 | void __init_or_cpufreq exynos4_setup_clocks(void) |
c8bef140 CY |
1456 | { |
1457 | struct clk *xtal_clk; | |
2bc02c0d KK |
1458 | unsigned long apll = 0; |
1459 | unsigned long mpll = 0; | |
1460 | unsigned long epll = 0; | |
1461 | unsigned long vpll = 0; | |
c8bef140 CY |
1462 | unsigned long vpllsrc; |
1463 | unsigned long xtal; | |
1464 | unsigned long armclk; | |
c8bef140 | 1465 | unsigned long sclk_dmc; |
228ef987 JL |
1466 | unsigned long aclk_200; |
1467 | unsigned long aclk_100; | |
1468 | unsigned long aclk_160; | |
1469 | unsigned long aclk_133; | |
c8bef140 CY |
1470 | unsigned int ptr; |
1471 | ||
1472 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | |
1473 | ||
1474 | xtal_clk = clk_get(NULL, "xtal"); | |
1475 | BUG_ON(IS_ERR(xtal_clk)); | |
1476 | ||
1477 | xtal = clk_get_rate(xtal_clk); | |
877d1b57 JL |
1478 | |
1479 | xtal_rate = xtal; | |
1480 | ||
c8bef140 CY |
1481 | clk_put(xtal_clk); |
1482 | ||
1483 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | |
1484 | ||
2bc02c0d | 1485 | if (soc_is_exynos4210()) { |
a855039e | 1486 | apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0), |
2bc02c0d | 1487 | pll_4508); |
a855039e | 1488 | mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0), |
2bc02c0d | 1489 | pll_4508); |
a855039e KK |
1490 | epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), |
1491 | __raw_readl(EXYNOS4_EPLL_CON1), pll_4600); | |
2bc02c0d | 1492 | |
a855039e KK |
1493 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); |
1494 | vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1495 | __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c); | |
b88b1cc7 | 1496 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { |
a855039e KK |
1497 | apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0)); |
1498 | mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0)); | |
1499 | epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0), | |
1500 | __raw_readl(EXYNOS4_EPLL_CON1)); | |
1501 | ||
1502 | vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk); | |
1503 | vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0), | |
1504 | __raw_readl(EXYNOS4_VPLL_CON1)); | |
2bc02c0d KK |
1505 | } else { |
1506 | /* nothing */ | |
1507 | } | |
c8bef140 | 1508 | |
b3ed3a17 | 1509 | clk_fout_apll.ops = &exynos4_fout_apll_ops; |
c8bef140 CY |
1510 | clk_fout_mpll.rate = mpll; |
1511 | clk_fout_epll.rate = epll; | |
fbf05563 | 1512 | clk_fout_vpll.ops = &exynos4_vpll_ops; |
c8bef140 CY |
1513 | clk_fout_vpll.rate = vpll; |
1514 | ||
b3ed3a17 | 1515 | printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
c8bef140 CY |
1516 | apll, mpll, epll, vpll); |
1517 | ||
a855039e KK |
1518 | armclk = clk_get_rate(&exynos4_clk_armclk.clk); |
1519 | sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk); | |
a6aa7a55 | 1520 | |
a855039e KK |
1521 | aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk); |
1522 | aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk); | |
1523 | aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk); | |
1524 | aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk); | |
228ef987 | 1525 | |
b3ed3a17 | 1526 | printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" |
228ef987 JL |
1527 | "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", |
1528 | armclk, sclk_dmc, aclk_200, | |
1529 | aclk_100, aclk_160, aclk_133); | |
c8bef140 CY |
1530 | |
1531 | clk_f.rate = armclk; | |
1532 | clk_h.rate = sclk_dmc; | |
228ef987 | 1533 | clk_p.rate = aclk_100; |
c8bef140 | 1534 | |
a855039e KK |
1535 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++) |
1536 | s3c_set_clksrc(&exynos4_clksrcs[ptr], true); | |
c8bef140 CY |
1537 | } |
1538 | ||
a855039e KK |
1539 | static struct clk *exynos4_clks[] __initdata = { |
1540 | &exynos4_clk_sclk_hdmi27m, | |
1541 | &exynos4_clk_sclk_hdmiphy, | |
1542 | &exynos4_clk_sclk_usbphy0, | |
1543 | &exynos4_clk_sclk_usbphy1, | |
c8bef140 CY |
1544 | }; |
1545 | ||
acd35616 JC |
1546 | #ifdef CONFIG_PM_SLEEP |
1547 | static int exynos4_clock_suspend(void) | |
1548 | { | |
1549 | s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | static void exynos4_clock_resume(void) | |
1554 | { | |
1555 | s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); | |
1556 | } | |
1557 | ||
1558 | #else | |
1559 | #define exynos4_clock_suspend NULL | |
1560 | #define exynos4_clock_resume NULL | |
1561 | #endif | |
1562 | ||
e745e06f | 1563 | static struct syscore_ops exynos4_clock_syscore_ops = { |
acd35616 JC |
1564 | .suspend = exynos4_clock_suspend, |
1565 | .resume = exynos4_clock_resume, | |
1566 | }; | |
1567 | ||
b3ed3a17 | 1568 | void __init exynos4_register_clocks(void) |
c8bef140 | 1569 | { |
c8bef140 CY |
1570 | int ptr; |
1571 | ||
a855039e | 1572 | s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks)); |
c8bef140 | 1573 | |
a855039e KK |
1574 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++) |
1575 | s3c_register_clksrc(exynos4_sysclks[ptr], 1); | |
c8bef140 | 1576 | |
a855039e KK |
1577 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++) |
1578 | s3c_register_clksrc(exynos4_sclk_tv[ptr], 1); | |
fbf05563 | 1579 | |
a855039e KK |
1580 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++) |
1581 | s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1); | |
0cfb26e1 | 1582 | |
a855039e KK |
1583 | s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs)); |
1584 | s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on)); | |
c8bef140 | 1585 | |
a855039e KK |
1586 | s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev)); |
1587 | for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++) | |
1588 | s3c_disable_clocks(exynos4_clk_cdev[ptr], 1); | |
66fdb29d | 1589 | |
a855039e KK |
1590 | s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); |
1591 | s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off)); | |
0cfb26e1 | 1592 | clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup)); |
c8bef140 | 1593 | |
acd35616 | 1594 | register_syscore_ops(&exynos4_clock_syscore_ops); |
bf856fbb BK |
1595 | s3c24xx_register_clock(&dummy_apb_pclk); |
1596 | ||
c8bef140 CY |
1597 | s3c_pwmclk_init(); |
1598 | } |