[deliverable/linux.git] / arch / arm / mach-exynos / clock-exynos4212.c

/*
 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4212 - Clock support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>

#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>

#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/sysmmu.h>

#include "common.h"
#include "clock-exynos4.h"

#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = {
	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
};
#endif

static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
}

static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
}

static struct clk *clk_src_mpll_user_list[] = {
	[0] = &clk_fin_mpll,
	[1] = &exynos4_clk_mout_mpll.clk,
};

static struct clksrc_sources clk_src_mpll_user = {
	.sources	= clk_src_mpll_user_list,
	.nr_sources	= ARRAY_SIZE(clk_src_mpll_user_list),
};

static struct clksrc_clk clk_mout_mpll_user = {
	.clk = {
		.name		= "mout_mpll_user",
	},
	.sources	= &clk_src_mpll_user,
	.reg_src	= { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};

static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
	.clk	= {
		.name		= "mout_g2d0",
	},
	.sources = &exynos4_clkset_mout_g2d0,
	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
};

static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
	.clk	= {
		.name		= "mout_g2d1",
	},
	.sources = &exynos4_clkset_mout_g2d1,
	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
};

static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
	[0] = &exynos4x12_clk_mout_g2d0.clk,
	[1] = &exynos4x12_clk_mout_g2d1.clk,
};

static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
	.sources	= exynos4x12_clkset_mout_g2d_list,
	.nr_sources	= ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
};

static struct clksrc_clk *sysclks[] = {
	&clk_mout_mpll_user,
};

static struct clksrc_clk clksrcs[] = {
	{
		.clk	= {
			.name		= "sclk_fimg2d",
		},
		.sources = &exynos4x12_clkset_mout_g2d,
		.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
		.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
	},
};

static struct clk init_clocks_off[] = {
	{
		.name		= SYSMMU_CLOCK_NAME,
		.devname	= SYSMMU_CLOCK_DEVNAME(2d, 14),
		.enable		= exynos4_clk_ip_dmc_ctrl,
		.ctrlbit	= (1 << 24),
	}, {
		.name		= SYSMMU_CLOCK_NAME,
		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
		.enable		= exynos4212_clk_ip_isp0_ctrl,
		.ctrlbit	= (7 << 8),
	}, {
		.name		= SYSMMU_CLOCK_NAME2,
		.devname	= SYSMMU_CLOCK_DEVNAME(isp, 9),
		.enable		= exynos4212_clk_ip_isp1_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "flite",
		.devname	= "exynos-fimc-lite.0",
		.enable		= exynos4212_clk_ip_isp0_ctrl,
		.ctrlbit	= (1 << 4),
	}, {
		.name		= "flite",
		.devname	= "exynos-fimc-lite.1",
		.enable		= exynos4212_clk_ip_isp0_ctrl,
		.ctrlbit	= (1 << 3),
	}, {
		.name		= "fimg2d",
		.enable		= exynos4_clk_ip_dmc_ctrl,
		.ctrlbit	= (1 << 23),
	},
};

#ifdef CONFIG_PM_SLEEP
static int exynos4212_clock_suspend(void)
{
	s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));

	return 0;
}

static void exynos4212_clock_resume(void)
{
	s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
}

#else
#define exynos4212_clock_suspend NULL
#define exynos4212_clock_resume NULL
#endif

static struct syscore_ops exynos4212_clock_syscore_ops = {
	.suspend	= exynos4212_clock_suspend,
	.resume		= exynos4212_clock_resume,
};

void __init exynos4212_register_clocks(void)
{
	int ptr;

	/* usbphy1 is removed */
	exynos4_clkset_group_list[4] = NULL;

	/* mout_mpll_user is used */
	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;

	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
	exynos4_clk_mout_mpll.reg_src.shift = 12;
	exynos4_clk_mout_mpll.reg_src.size = 1;

	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
		s3c_register_clksrc(sysclks[ptr], 1);

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	register_syscore_ops(&exynos4212_clock_syscore_ops);
}
Commit	Line	Data
2bc02c0d	1	/*
a855039e	2	* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
2bc02c0d KK	3	* http://www.samsung.com
	4	*
	5	* EXYNOS4212 - Clock support
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/err.h>
	14	#include <linux/clk.h>
	15	#include <linux/io.h>
acd35616	16	#include <linux/syscore_ops.h>
2bc02c0d KK	17
	18	#include <plat/cpu-freq.h>
	19	#include <plat/clock.h>
	20	#include <plat/cpu.h>
	21	#include <plat/pll.h>
	22	#include <plat/s5p-clock.h>
	23	#include <plat/clock-clksrc.h>
acd35616	24	#include <plat/pm.h>
2bc02c0d KK	25
	26	#include <mach/hardware.h>
	27	#include <mach/map.h>
	28	#include <mach/regs-clock.h>
bca10b90	29	#include <mach/sysmmu.h>
2bc02c0d	30
cc511b8d	31	#include "common.h"
ce9c00ee	32	#include "clock-exynos4.h"
cc511b8d	33
7cdf04d7	34	#ifdef CONFIG_PM_SLEEP
acd35616	35	static struct sleep_save exynos4212_clock_save[] = {
a855039e KK	36	SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
	37	SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
	38	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
	39	SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
acd35616	40	};
7cdf04d7	41	#endif
acd35616	42
bca10b90 KC	43	static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
	44	{
	45	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
	46	}
	47
	48	static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
	49	{
	50	return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
	51	}
	52
2bc02c0d KK	53	static struct clk *clk_src_mpll_user_list[] = {
2bc02c0d KK	54	[0] = &clk_fin_mpll,
a855039e	55	[1] = &exynos4_clk_mout_mpll.clk,
2bc02c0d KK	56	};
	57
	58	static struct clksrc_sources clk_src_mpll_user = {
	59	.sources = clk_src_mpll_user_list,
	60	.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
	61	};
	62
	63	static struct clksrc_clk clk_mout_mpll_user = {
	64	.clk = {
	65	.name = "mout_mpll_user",
	66	},
	67	.sources = &clk_src_mpll_user,
a855039e	68	.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
2bc02c0d KK	69	};
2bc02c0d KK	70
6c6c185b SK	71	static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
	72	.clk = {
	73	.name = "mout_g2d0",
	74	},
	75	.sources = &exynos4_clkset_mout_g2d0,
	76	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
	77	};
	78
	79	static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
	80	.clk = {
	81	.name = "mout_g2d1",
	82	},
	83	.sources = &exynos4_clkset_mout_g2d1,
	84	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
	85	};
	86
	87	static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
	88	[0] = &exynos4x12_clk_mout_g2d0.clk,
	89	[1] = &exynos4x12_clk_mout_g2d1.clk,
	90	};
	91
	92	static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
	93	.sources = exynos4x12_clkset_mout_g2d_list,
	94	.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
	95	};
	96
2bc02c0d KK	97	static struct clksrc_clk *sysclks[] = {
	98	&clk_mout_mpll_user,
	99	};
	100
	101	static struct clksrc_clk clksrcs[] = {
6c6c185b SK	102	{
	103	.clk = {
	104	.name = "sclk_fimg2d",
	105	},
	106	.sources = &exynos4x12_clkset_mout_g2d,
	107	.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
	108	.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
	109	},
2bc02c0d KK	110	};
	111
	112	static struct clk init_clocks_off[] = {
bca10b90 KC	113	{
	114	.name = SYSMMU_CLOCK_NAME,
	115	.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
	116	.enable = exynos4_clk_ip_dmc_ctrl,
	117	.ctrlbit = (1 << 24),
	118	}, {
	119	.name = SYSMMU_CLOCK_NAME,
	120	.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
	121	.enable = exynos4212_clk_ip_isp0_ctrl,
	122	.ctrlbit = (7 << 8),
	123	}, {
	124	.name = SYSMMU_CLOCK_NAME2,
	125	.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
	126	.enable = exynos4212_clk_ip_isp1_ctrl,
	127	.ctrlbit = (1 << 4),
06050e55 SN	128	}, {
	129	.name = "flite",
	130	.devname = "exynos-fimc-lite.0",
	131	.enable = exynos4212_clk_ip_isp0_ctrl,
	132	.ctrlbit = (1 << 4),
	133	}, {
	134	.name = "flite",
	135	.devname = "exynos-fimc-lite.1",
	136	.enable = exynos4212_clk_ip_isp0_ctrl,
	137	.ctrlbit = (1 << 3),
6c6c185b SK	138	}, {
	139	.name = "fimg2d",
	140	.enable = exynos4_clk_ip_dmc_ctrl,
	141	.ctrlbit = (1 << 23),
	142	},
2bc02c0d KK	143	};
2bc02c0d KK	144
acd35616 JC	145	#ifdef CONFIG_PM_SLEEP
	146	static int exynos4212_clock_suspend(void)
	147	{
	148	s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
	149
	150	return 0;
	151	}
	152
	153	static void exynos4212_clock_resume(void)
	154	{
	155	s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
	156	}
	157
	158	#else
	159	#define exynos4212_clock_suspend NULL
	160	#define exynos4212_clock_resume NULL
	161	#endif
	162
e745e06f	163	static struct syscore_ops exynos4212_clock_syscore_ops = {
acd35616 JC	164	.suspend = exynos4212_clock_suspend,
	165	.resume = exynos4212_clock_resume,
	166	};
	167
2bc02c0d KK	168	void __init exynos4212_register_clocks(void)
	169	{
	170	int ptr;
	171
	172	/* usbphy1 is removed */
a855039e	173	exynos4_clkset_group_list[4] = NULL;
2bc02c0d KK	174
2bc02c0d KK	175	/* mout_mpll_user is used */
a855039e KK	176	exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
a855039e KK	177	exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
2bc02c0d	178
a855039e KK	179	exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
	180	exynos4_clk_mout_mpll.reg_src.shift = 12;
	181	exynos4_clk_mout_mpll.reg_src.size = 1;
2bc02c0d KK	182
	183	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
	184	s3c_register_clksrc(sysclks[ptr], 1);
	185
	186	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
	187
	188	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
	189	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
acd35616 JC	190
acd35616 JC	191	register_syscore_ops(&exynos4212_clock_syscore_ops);
2bc02c0d	192	}