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cc511b8d KK |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * Common Codes for EXYNOS | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
7affca35 | 16 | #include <linux/device.h> |
cc511b8d KK |
17 | #include <linux/gpio.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/serial_core.h> | |
237c78be AB |
20 | #include <linux/of.h> |
21 | #include <linux/of_irq.h> | |
1e60bc0b TA |
22 | #include <linux/export.h> |
23 | #include <linux/irqdomain.h> | |
e873a47c | 24 | #include <linux/of_address.h> |
cc511b8d KK |
25 | |
26 | #include <asm/proc-fns.h> | |
40ba95fd | 27 | #include <asm/exception.h> |
cc511b8d KK |
28 | #include <asm/hardware/cache-l2x0.h> |
29 | #include <asm/hardware/gic.h> | |
30 | #include <asm/mach/map.h> | |
31 | #include <asm/mach/irq.h> | |
b756a50f | 32 | #include <asm/cacheflush.h> |
cc511b8d KK |
33 | |
34 | #include <mach/regs-irq.h> | |
35 | #include <mach/regs-pmu.h> | |
36 | #include <mach/regs-gpio.h> | |
b756a50f | 37 | #include <mach/pmu.h> |
cc511b8d KK |
38 | |
39 | #include <plat/cpu.h> | |
40 | #include <plat/clock.h> | |
41 | #include <plat/devs.h> | |
42 | #include <plat/pm.h> | |
cc511b8d KK |
43 | #include <plat/sdhci.h> |
44 | #include <plat/gpio-cfg.h> | |
45 | #include <plat/adc-core.h> | |
46 | #include <plat/fb-core.h> | |
47 | #include <plat/fimc-core.h> | |
48 | #include <plat/iic-core.h> | |
49 | #include <plat/tv-core.h> | |
308b3afb | 50 | #include <plat/spi-core.h> |
cc511b8d KK |
51 | #include <plat/regs-serial.h> |
52 | ||
53 | #include "common.h" | |
6cdeddcc ADK |
54 | #define L2_AUX_VAL 0x7C470001 |
55 | #define L2_AUX_MASK 0xC200ffff | |
cc511b8d | 56 | |
cc511b8d KK |
57 | static const char name_exynos4210[] = "EXYNOS4210"; |
58 | static const char name_exynos4212[] = "EXYNOS4212"; | |
59 | static const char name_exynos4412[] = "EXYNOS4412"; | |
94c7ca71 | 60 | static const char name_exynos5250[] = "EXYNOS5250"; |
cc511b8d | 61 | |
906c789c | 62 | static void exynos4_map_io(void); |
94c7ca71 | 63 | static void exynos5_map_io(void); |
906c789c | 64 | static void exynos4_init_clocks(int xtal); |
94c7ca71 | 65 | static void exynos5_init_clocks(int xtal); |
55b6ef7a | 66 | static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
906c789c | 67 | static int exynos_init(void); |
cc511b8d KK |
68 | |
69 | static struct cpu_table cpu_ids[] __initdata = { | |
70 | { | |
71 | .idcode = EXYNOS4210_CPU_ID, | |
72 | .idmask = EXYNOS4_CPU_MASK, | |
73 | .map_io = exynos4_map_io, | |
74 | .init_clocks = exynos4_init_clocks, | |
55b6ef7a | 75 | .init_uarts = exynos4_init_uarts, |
cc511b8d KK |
76 | .init = exynos_init, |
77 | .name = name_exynos4210, | |
78 | }, { | |
79 | .idcode = EXYNOS4212_CPU_ID, | |
80 | .idmask = EXYNOS4_CPU_MASK, | |
81 | .map_io = exynos4_map_io, | |
82 | .init_clocks = exynos4_init_clocks, | |
55b6ef7a | 83 | .init_uarts = exynos4_init_uarts, |
cc511b8d KK |
84 | .init = exynos_init, |
85 | .name = name_exynos4212, | |
86 | }, { | |
87 | .idcode = EXYNOS4412_CPU_ID, | |
88 | .idmask = EXYNOS4_CPU_MASK, | |
89 | .map_io = exynos4_map_io, | |
90 | .init_clocks = exynos4_init_clocks, | |
55b6ef7a | 91 | .init_uarts = exynos4_init_uarts, |
cc511b8d KK |
92 | .init = exynos_init, |
93 | .name = name_exynos4412, | |
94c7ca71 KK |
94 | }, { |
95 | .idcode = EXYNOS5250_SOC_ID, | |
96 | .idmask = EXYNOS5_SOC_MASK, | |
97 | .map_io = exynos5_map_io, | |
98 | .init_clocks = exynos5_init_clocks, | |
94c7ca71 KK |
99 | .init = exynos_init, |
100 | .name = name_exynos5250, | |
cc511b8d KK |
101 | }, |
102 | }; | |
103 | ||
104 | /* Initial IO mappings */ | |
105 | ||
106 | static struct map_desc exynos_iodesc[] __initdata = { | |
107 | { | |
108 | .virtual = (unsigned long)S5P_VA_CHIPID, | |
94c7ca71 | 109 | .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID), |
cc511b8d KK |
110 | .length = SZ_4K, |
111 | .type = MT_DEVICE, | |
94c7ca71 KK |
112 | }, |
113 | }; | |
114 | ||
115 | static struct map_desc exynos4_iodesc[] __initdata = { | |
116 | { | |
cc511b8d KK |
117 | .virtual = (unsigned long)S3C_VA_SYS, |
118 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON), | |
119 | .length = SZ_64K, | |
120 | .type = MT_DEVICE, | |
121 | }, { | |
122 | .virtual = (unsigned long)S3C_VA_TIMER, | |
123 | .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER), | |
124 | .length = SZ_16K, | |
125 | .type = MT_DEVICE, | |
126 | }, { | |
127 | .virtual = (unsigned long)S3C_VA_WATCHDOG, | |
128 | .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG), | |
129 | .length = SZ_4K, | |
130 | .type = MT_DEVICE, | |
131 | }, { | |
132 | .virtual = (unsigned long)S5P_VA_SROMC, | |
133 | .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC), | |
134 | .length = SZ_4K, | |
135 | .type = MT_DEVICE, | |
136 | }, { | |
137 | .virtual = (unsigned long)S5P_VA_SYSTIMER, | |
138 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), | |
139 | .length = SZ_4K, | |
140 | .type = MT_DEVICE, | |
141 | }, { | |
142 | .virtual = (unsigned long)S5P_VA_PMU, | |
143 | .pfn = __phys_to_pfn(EXYNOS4_PA_PMU), | |
144 | .length = SZ_64K, | |
145 | .type = MT_DEVICE, | |
146 | }, { | |
147 | .virtual = (unsigned long)S5P_VA_COMBINER_BASE, | |
148 | .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER), | |
149 | .length = SZ_4K, | |
150 | .type = MT_DEVICE, | |
151 | }, { | |
152 | .virtual = (unsigned long)S5P_VA_GIC_CPU, | |
153 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU), | |
154 | .length = SZ_64K, | |
155 | .type = MT_DEVICE, | |
156 | }, { | |
157 | .virtual = (unsigned long)S5P_VA_GIC_DIST, | |
158 | .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST), | |
159 | .length = SZ_64K, | |
160 | .type = MT_DEVICE, | |
161 | }, { | |
162 | .virtual = (unsigned long)S3C_VA_UART, | |
163 | .pfn = __phys_to_pfn(EXYNOS4_PA_UART), | |
164 | .length = SZ_512K, | |
165 | .type = MT_DEVICE, | |
94c7ca71 | 166 | }, { |
cc511b8d KK |
167 | .virtual = (unsigned long)S5P_VA_CMU, |
168 | .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), | |
169 | .length = SZ_128K, | |
170 | .type = MT_DEVICE, | |
171 | }, { | |
172 | .virtual = (unsigned long)S5P_VA_COREPERI_BASE, | |
173 | .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI), | |
174 | .length = SZ_8K, | |
175 | .type = MT_DEVICE, | |
176 | }, { | |
177 | .virtual = (unsigned long)S5P_VA_L2CC, | |
178 | .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC), | |
179 | .length = SZ_4K, | |
180 | .type = MT_DEVICE, | |
cc511b8d KK |
181 | }, { |
182 | .virtual = (unsigned long)S5P_VA_DMC0, | |
183 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), | |
2bde0b08 MH |
184 | .length = SZ_64K, |
185 | .type = MT_DEVICE, | |
186 | }, { | |
187 | .virtual = (unsigned long)S5P_VA_DMC1, | |
188 | .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), | |
189 | .length = SZ_64K, | |
cc511b8d | 190 | .type = MT_DEVICE, |
cc511b8d KK |
191 | }, { |
192 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, | |
193 | .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY), | |
194 | .length = SZ_4K, | |
195 | .type = MT_DEVICE, | |
196 | }, | |
197 | }; | |
198 | ||
199 | static struct map_desc exynos4_iodesc0[] __initdata = { | |
200 | { | |
201 | .virtual = (unsigned long)S5P_VA_SYSRAM, | |
202 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), | |
203 | .length = SZ_4K, | |
204 | .type = MT_DEVICE, | |
205 | }, | |
206 | }; | |
207 | ||
208 | static struct map_desc exynos4_iodesc1[] __initdata = { | |
209 | { | |
210 | .virtual = (unsigned long)S5P_VA_SYSRAM, | |
211 | .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), | |
212 | .length = SZ_4K, | |
213 | .type = MT_DEVICE, | |
214 | }, | |
215 | }; | |
216 | ||
94c7ca71 KK |
217 | static struct map_desc exynos5_iodesc[] __initdata = { |
218 | { | |
219 | .virtual = (unsigned long)S3C_VA_SYS, | |
220 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON), | |
221 | .length = SZ_64K, | |
222 | .type = MT_DEVICE, | |
223 | }, { | |
224 | .virtual = (unsigned long)S3C_VA_TIMER, | |
225 | .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER), | |
226 | .length = SZ_16K, | |
227 | .type = MT_DEVICE, | |
228 | }, { | |
229 | .virtual = (unsigned long)S3C_VA_WATCHDOG, | |
230 | .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG), | |
231 | .length = SZ_4K, | |
232 | .type = MT_DEVICE, | |
233 | }, { | |
234 | .virtual = (unsigned long)S5P_VA_SROMC, | |
235 | .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), | |
236 | .length = SZ_4K, | |
237 | .type = MT_DEVICE, | |
238 | }, { | |
239 | .virtual = (unsigned long)S5P_VA_SYSTIMER, | |
240 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), | |
241 | .length = SZ_4K, | |
242 | .type = MT_DEVICE, | |
243 | }, { | |
244 | .virtual = (unsigned long)S5P_VA_SYSRAM, | |
245 | .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), | |
246 | .length = SZ_4K, | |
247 | .type = MT_DEVICE, | |
248 | }, { | |
249 | .virtual = (unsigned long)S5P_VA_CMU, | |
250 | .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), | |
251 | .length = 144 * SZ_1K, | |
252 | .type = MT_DEVICE, | |
253 | }, { | |
254 | .virtual = (unsigned long)S5P_VA_PMU, | |
255 | .pfn = __phys_to_pfn(EXYNOS5_PA_PMU), | |
256 | .length = SZ_64K, | |
257 | .type = MT_DEVICE, | |
94c7ca71 KK |
258 | }, { |
259 | .virtual = (unsigned long)S3C_VA_UART, | |
260 | .pfn = __phys_to_pfn(EXYNOS5_PA_UART), | |
261 | .length = SZ_512K, | |
262 | .type = MT_DEVICE, | |
94c7ca71 KK |
263 | }, |
264 | }; | |
265 | ||
9eb48595 | 266 | void exynos4_restart(char mode, const char *cmd) |
cc511b8d KK |
267 | { |
268 | __raw_writel(0x1, S5P_SWRESET); | |
269 | } | |
270 | ||
94c7ca71 KK |
271 | void exynos5_restart(char mode, const char *cmd) |
272 | { | |
273 | __raw_writel(0x1, EXYNOS_SWRESET); | |
274 | } | |
275 | ||
bb13fabc SG |
276 | void __init exynos_init_late(void) |
277 | { | |
278 | exynos_pm_late_initcall(); | |
279 | } | |
280 | ||
cc511b8d KK |
281 | /* |
282 | * exynos_map_io | |
283 | * | |
284 | * register the standard cpu IO areas | |
285 | */ | |
286 | ||
287 | void __init exynos_init_io(struct map_desc *mach_desc, int size) | |
288 | { | |
289 | /* initialize the io descriptors we need for initialization */ | |
290 | iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); | |
291 | if (mach_desc) | |
292 | iotable_init(mach_desc, size); | |
293 | ||
294 | /* detect cpu id and rev. */ | |
295 | s5p_init_cpu(S5P_VA_CHIPID); | |
296 | ||
297 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); | |
298 | } | |
299 | ||
906c789c | 300 | static void __init exynos4_map_io(void) |
cc511b8d KK |
301 | { |
302 | iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); | |
303 | ||
304 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) | |
305 | iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); | |
306 | else | |
307 | iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); | |
308 | ||
309 | /* initialize device information early */ | |
310 | exynos4_default_sdhci0(); | |
311 | exynos4_default_sdhci1(); | |
312 | exynos4_default_sdhci2(); | |
313 | exynos4_default_sdhci3(); | |
314 | ||
315 | s3c_adc_setname("samsung-adc-v3"); | |
316 | ||
317 | s3c_fimc_setname(0, "exynos4-fimc"); | |
318 | s3c_fimc_setname(1, "exynos4-fimc"); | |
319 | s3c_fimc_setname(2, "exynos4-fimc"); | |
320 | s3c_fimc_setname(3, "exynos4-fimc"); | |
321 | ||
8482c81c TA |
322 | s3c_sdhci_setname(0, "exynos4-sdhci"); |
323 | s3c_sdhci_setname(1, "exynos4-sdhci"); | |
324 | s3c_sdhci_setname(2, "exynos4-sdhci"); | |
325 | s3c_sdhci_setname(3, "exynos4-sdhci"); | |
326 | ||
cc511b8d KK |
327 | /* The I2C bus controllers are directly compatible with s3c2440 */ |
328 | s3c_i2c0_setname("s3c2440-i2c"); | |
329 | s3c_i2c1_setname("s3c2440-i2c"); | |
330 | s3c_i2c2_setname("s3c2440-i2c"); | |
331 | ||
332 | s5p_fb_setname(0, "exynos4-fb"); | |
333 | s5p_hdmi_setname("exynos4-hdmi"); | |
308b3afb HS |
334 | |
335 | s3c64xx_spi_setname("exynos4210-spi"); | |
cc511b8d KK |
336 | } |
337 | ||
94c7ca71 KK |
338 | static void __init exynos5_map_io(void) |
339 | { | |
340 | iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); | |
341 | ||
bb19a751 KK |
342 | s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0); |
343 | s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1; | |
344 | s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; | |
345 | s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; | |
346 | ||
8482c81c TA |
347 | s3c_sdhci_setname(0, "exynos4-sdhci"); |
348 | s3c_sdhci_setname(1, "exynos4-sdhci"); | |
349 | s3c_sdhci_setname(2, "exynos4-sdhci"); | |
350 | s3c_sdhci_setname(3, "exynos4-sdhci"); | |
351 | ||
94c7ca71 KK |
352 | /* The I2C bus controllers are directly compatible with s3c2440 */ |
353 | s3c_i2c0_setname("s3c2440-i2c"); | |
354 | s3c_i2c1_setname("s3c2440-i2c"); | |
355 | s3c_i2c2_setname("s3c2440-i2c"); | |
308b3afb HS |
356 | |
357 | s3c64xx_spi_setname("exynos4210-spi"); | |
94c7ca71 KK |
358 | } |
359 | ||
906c789c | 360 | static void __init exynos4_init_clocks(int xtal) |
cc511b8d KK |
361 | { |
362 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | |
363 | ||
364 | s3c24xx_register_baseclocks(xtal); | |
365 | s5p_register_clocks(xtal); | |
366 | ||
367 | if (soc_is_exynos4210()) | |
368 | exynos4210_register_clocks(); | |
369 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | |
370 | exynos4212_register_clocks(); | |
371 | ||
372 | exynos4_register_clocks(); | |
373 | exynos4_setup_clocks(); | |
374 | } | |
375 | ||
94c7ca71 KK |
376 | static void __init exynos5_init_clocks(int xtal) |
377 | { | |
378 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | |
379 | ||
380 | s3c24xx_register_baseclocks(xtal); | |
381 | s5p_register_clocks(xtal); | |
382 | ||
383 | exynos5_register_clocks(); | |
384 | exynos5_setup_clocks(); | |
385 | } | |
386 | ||
cc511b8d KK |
387 | #define COMBINER_ENABLE_SET 0x0 |
388 | #define COMBINER_ENABLE_CLEAR 0x4 | |
389 | #define COMBINER_INT_STATUS 0xC | |
390 | ||
391 | static DEFINE_SPINLOCK(irq_controller_lock); | |
392 | ||
393 | struct combiner_chip_data { | |
394 | unsigned int irq_offset; | |
395 | unsigned int irq_mask; | |
396 | void __iomem *base; | |
397 | }; | |
398 | ||
1e60bc0b | 399 | static struct irq_domain *combiner_irq_domain; |
cc511b8d KK |
400 | static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; |
401 | ||
402 | static inline void __iomem *combiner_base(struct irq_data *data) | |
403 | { | |
404 | struct combiner_chip_data *combiner_data = | |
405 | irq_data_get_irq_chip_data(data); | |
406 | ||
407 | return combiner_data->base; | |
408 | } | |
409 | ||
410 | static void combiner_mask_irq(struct irq_data *data) | |
411 | { | |
1e60bc0b | 412 | u32 mask = 1 << (data->hwirq % 32); |
cc511b8d KK |
413 | |
414 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR); | |
415 | } | |
416 | ||
417 | static void combiner_unmask_irq(struct irq_data *data) | |
418 | { | |
1e60bc0b | 419 | u32 mask = 1 << (data->hwirq % 32); |
cc511b8d KK |
420 | |
421 | __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET); | |
422 | } | |
423 | ||
424 | static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |
425 | { | |
426 | struct combiner_chip_data *chip_data = irq_get_handler_data(irq); | |
427 | struct irq_chip *chip = irq_get_chip(irq); | |
428 | unsigned int cascade_irq, combiner_irq; | |
429 | unsigned long status; | |
430 | ||
431 | chained_irq_enter(chip, desc); | |
432 | ||
433 | spin_lock(&irq_controller_lock); | |
434 | status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); | |
435 | spin_unlock(&irq_controller_lock); | |
436 | status &= chip_data->irq_mask; | |
437 | ||
438 | if (status == 0) | |
439 | goto out; | |
440 | ||
441 | combiner_irq = __ffs(status); | |
442 | ||
443 | cascade_irq = combiner_irq + (chip_data->irq_offset & ~31); | |
444 | if (unlikely(cascade_irq >= NR_IRQS)) | |
445 | do_bad_IRQ(cascade_irq, desc); | |
446 | else | |
447 | generic_handle_irq(cascade_irq); | |
448 | ||
449 | out: | |
450 | chained_irq_exit(chip, desc); | |
451 | } | |
452 | ||
453 | static struct irq_chip combiner_chip = { | |
454 | .name = "COMBINER", | |
455 | .irq_mask = combiner_mask_irq, | |
456 | .irq_unmask = combiner_unmask_irq, | |
457 | }; | |
458 | ||
459 | static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) | |
460 | { | |
bb19a751 KK |
461 | unsigned int max_nr; |
462 | ||
463 | if (soc_is_exynos5250()) | |
464 | max_nr = EXYNOS5_MAX_COMBINER_NR; | |
465 | else | |
466 | max_nr = EXYNOS4_MAX_COMBINER_NR; | |
467 | ||
468 | if (combiner_nr >= max_nr) | |
cc511b8d KK |
469 | BUG(); |
470 | if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) | |
471 | BUG(); | |
472 | irq_set_chained_handler(irq, combiner_handle_cascade_irq); | |
473 | } | |
474 | ||
1e60bc0b TA |
475 | static void __init combiner_init_one(unsigned int combiner_nr, |
476 | void __iomem *base) | |
cc511b8d | 477 | { |
cc511b8d | 478 | combiner_data[combiner_nr].base = base; |
1e60bc0b TA |
479 | combiner_data[combiner_nr].irq_offset = irq_find_mapping( |
480 | combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER); | |
cc511b8d KK |
481 | combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3); |
482 | ||
483 | /* Disable all interrupts */ | |
cc511b8d KK |
484 | __raw_writel(combiner_data[combiner_nr].irq_mask, |
485 | base + COMBINER_ENABLE_CLEAR); | |
1e60bc0b | 486 | } |
cc511b8d | 487 | |
e873a47c TA |
488 | #ifdef CONFIG_OF |
489 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
490 | struct device_node *controller, | |
491 | const u32 *intspec, unsigned int intsize, | |
492 | unsigned long *out_hwirq, | |
493 | unsigned int *out_type) | |
494 | { | |
495 | if (d->of_node != controller) | |
496 | return -EINVAL; | |
497 | ||
498 | if (intsize < 2) | |
499 | return -EINVAL; | |
500 | ||
501 | *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1]; | |
502 | *out_type = 0; | |
503 | ||
504 | return 0; | |
505 | } | |
506 | #else | |
507 | static int combiner_irq_domain_xlate(struct irq_domain *d, | |
508 | struct device_node *controller, | |
509 | const u32 *intspec, unsigned int intsize, | |
510 | unsigned long *out_hwirq, | |
511 | unsigned int *out_type) | |
512 | { | |
513 | return -EINVAL; | |
514 | } | |
515 | #endif | |
516 | ||
1e60bc0b TA |
517 | static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq, |
518 | irq_hw_number_t hw) | |
519 | { | |
520 | irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq); | |
521 | irq_set_chip_data(irq, &combiner_data[hw >> 3]); | |
522 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
523 | ||
524 | return 0; | |
525 | } | |
cc511b8d | 526 | |
1e60bc0b | 527 | static struct irq_domain_ops combiner_irq_domain_ops = { |
e873a47c | 528 | .xlate = combiner_irq_domain_xlate, |
1e60bc0b TA |
529 | .map = combiner_irq_domain_map, |
530 | }; | |
531 | ||
2a2b0e20 SK |
532 | static void __init combiner_init(void __iomem *combiner_base, |
533 | struct device_node *np) | |
1e60bc0b | 534 | { |
e873a47c | 535 | int i, irq, irq_base; |
1e60bc0b TA |
536 | unsigned int max_nr, nr_irq; |
537 | ||
e873a47c TA |
538 | if (np) { |
539 | if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { | |
540 | pr_warning("%s: number of combiners not specified, " | |
541 | "setting default as %d.\n", | |
542 | __func__, EXYNOS4_MAX_COMBINER_NR); | |
543 | max_nr = EXYNOS4_MAX_COMBINER_NR; | |
544 | } | |
545 | } else { | |
546 | max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR : | |
547 | EXYNOS4_MAX_COMBINER_NR; | |
548 | } | |
1e60bc0b TA |
549 | nr_irq = max_nr * MAX_IRQ_IN_COMBINER; |
550 | ||
551 | irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); | |
552 | if (IS_ERR_VALUE(irq_base)) { | |
553 | irq_base = COMBINER_IRQ(0, 0); | |
554 | pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base); | |
555 | } | |
556 | ||
557 | combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0, | |
558 | &combiner_irq_domain_ops, &combiner_data); | |
559 | if (WARN_ON(!combiner_irq_domain)) { | |
560 | pr_warning("%s: irq domain init failed\n", __func__); | |
561 | return; | |
562 | } | |
563 | ||
564 | for (i = 0; i < max_nr; i++) { | |
565 | combiner_init_one(i, combiner_base + (i >> 2) * 0x10); | |
820f3dd7 AB |
566 | irq = IRQ_SPI(i); |
567 | #ifdef CONFIG_OF | |
568 | if (np) | |
569 | irq = irq_of_parse_and_map(np, i); | |
570 | #endif | |
e873a47c | 571 | combiner_cascade_irq(i, irq); |
cc511b8d KK |
572 | } |
573 | } | |
574 | ||
237c78be | 575 | #ifdef CONFIG_OF |
e873a47c TA |
576 | int __init combiner_of_init(struct device_node *np, struct device_node *parent) |
577 | { | |
578 | void __iomem *combiner_base; | |
579 | ||
580 | combiner_base = of_iomap(np, 0); | |
581 | if (!combiner_base) { | |
582 | pr_err("%s: failed to map combiner registers\n", __func__); | |
583 | return -ENXIO; | |
584 | } | |
585 | ||
586 | combiner_init(combiner_base, np); | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
237c78be AB |
591 | static const struct of_device_id exynos4_dt_irq_match[] = { |
592 | { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, | |
e873a47c TA |
593 | { .compatible = "samsung,exynos4210-combiner", |
594 | .data = combiner_of_init, }, | |
237c78be AB |
595 | {}, |
596 | }; | |
597 | #endif | |
cc511b8d KK |
598 | |
599 | void __init exynos4_init_irq(void) | |
600 | { | |
40ba95fd | 601 | unsigned int gic_bank_offset; |
cc511b8d KK |
602 | |
603 | gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000; | |
604 | ||
237c78be | 605 | if (!of_have_populated_dt()) |
75294957 | 606 | gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL); |
237c78be AB |
607 | #ifdef CONFIG_OF |
608 | else | |
609 | of_irq_init(exynos4_dt_irq_match); | |
610 | #endif | |
cc511b8d | 611 | |
e873a47c TA |
612 | if (!of_have_populated_dt()) |
613 | combiner_init(S5P_VA_COMBINER_BASE, NULL); | |
cc511b8d KK |
614 | |
615 | /* | |
616 | * The parameters of s5p_init_irq() are for VIC init. | |
617 | * Theses parameters should be NULL and 0 because EXYNOS4 | |
618 | * uses GIC instead of VIC. | |
619 | */ | |
620 | s5p_init_irq(NULL, 0); | |
621 | } | |
622 | ||
94c7ca71 KK |
623 | void __init exynos5_init_irq(void) |
624 | { | |
6fff5a11 | 625 | #ifdef CONFIG_OF |
5699b0ca | 626 | of_irq_init(exynos4_dt_irq_match); |
6fff5a11 | 627 | #endif |
cc511b8d KK |
628 | /* |
629 | * The parameters of s5p_init_irq() are for VIC init. | |
630 | * Theses parameters should be NULL and 0 because EXYNOS4 | |
631 | * uses GIC instead of VIC. | |
632 | */ | |
633 | s5p_init_irq(NULL, 0); | |
634 | } | |
635 | ||
9ee6af9c TA |
636 | struct bus_type exynos_subsys = { |
637 | .name = "exynos-core", | |
638 | .dev_name = "exynos-core", | |
94c7ca71 KK |
639 | }; |
640 | ||
7affca35 | 641 | static struct device exynos4_dev = { |
9ee6af9c | 642 | .bus = &exynos_subsys, |
94c7ca71 KK |
643 | }; |
644 | ||
645 | static int __init exynos_core_init(void) | |
cc511b8d | 646 | { |
9ee6af9c | 647 | return subsys_system_register(&exynos_subsys, NULL); |
cc511b8d | 648 | } |
94c7ca71 | 649 | core_initcall(exynos_core_init); |
cc511b8d KK |
650 | |
651 | #ifdef CONFIG_CACHE_L2X0 | |
652 | static int __init exynos4_l2x0_cache_init(void) | |
653 | { | |
e1b1994e IH |
654 | int ret; |
655 | ||
94c7ca71 KK |
656 | if (soc_is_exynos5250()) |
657 | return 0; | |
658 | ||
6cdeddcc ADK |
659 | ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); |
660 | if (!ret) { | |
661 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); | |
662 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | |
663 | return 0; | |
664 | } | |
cc511b8d | 665 | |
b756a50f ADK |
666 | if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { |
667 | l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; | |
668 | /* TAG, Data Latency Control: 2 cycles */ | |
669 | l2x0_saved_regs.tag_latency = 0x110; | |
cc511b8d | 670 | |
b756a50f ADK |
671 | if (soc_is_exynos4212() || soc_is_exynos4412()) |
672 | l2x0_saved_regs.data_latency = 0x120; | |
673 | else | |
674 | l2x0_saved_regs.data_latency = 0x110; | |
675 | ||
676 | l2x0_saved_regs.prefetch_ctrl = 0x30000007; | |
677 | l2x0_saved_regs.pwr_ctrl = | |
678 | (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); | |
cc511b8d | 679 | |
b756a50f | 680 | l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); |
cc511b8d | 681 | |
b756a50f ADK |
682 | __raw_writel(l2x0_saved_regs.tag_latency, |
683 | S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); | |
684 | __raw_writel(l2x0_saved_regs.data_latency, | |
685 | S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); | |
cc511b8d | 686 | |
b756a50f ADK |
687 | /* L2X0 Prefetch Control */ |
688 | __raw_writel(l2x0_saved_regs.prefetch_ctrl, | |
689 | S5P_VA_L2CC + L2X0_PREFETCH_CTRL); | |
690 | ||
691 | /* L2X0 Power Control */ | |
692 | __raw_writel(l2x0_saved_regs.pwr_ctrl, | |
693 | S5P_VA_L2CC + L2X0_POWER_CTRL); | |
694 | ||
695 | clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); | |
696 | clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); | |
697 | } | |
cc511b8d | 698 | |
6cdeddcc | 699 | l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); |
cc511b8d KK |
700 | return 0; |
701 | } | |
cc511b8d KK |
702 | early_initcall(exynos4_l2x0_cache_init); |
703 | #endif | |
704 | ||
906c789c | 705 | static int __init exynos_init(void) |
cc511b8d KK |
706 | { |
707 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); | |
94c7ca71 | 708 | |
9ee6af9c | 709 | return device_register(&exynos4_dev); |
cc511b8d KK |
710 | } |
711 | ||
cc511b8d KK |
712 | /* uart registration process */ |
713 | ||
55b6ef7a | 714 | static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
cc511b8d KK |
715 | { |
716 | struct s3c2410_uartcfg *tcfg = cfg; | |
717 | u32 ucnt; | |
718 | ||
237c78be AB |
719 | for (ucnt = 0; ucnt < no; ucnt++, tcfg++) |
720 | tcfg->has_fracval = 1; | |
cc511b8d | 721 | |
55b6ef7a | 722 | s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no); |
cc511b8d KK |
723 | } |
724 | ||
330c90a5 EK |
725 | static void __iomem *exynos_eint_base; |
726 | ||
cc511b8d KK |
727 | static DEFINE_SPINLOCK(eint_lock); |
728 | ||
729 | static unsigned int eint0_15_data[16]; | |
730 | ||
330c90a5 | 731 | static inline int exynos4_irq_to_gpio(unsigned int irq) |
cc511b8d | 732 | { |
330c90a5 EK |
733 | if (irq < IRQ_EINT(0)) |
734 | return -EINVAL; | |
cc511b8d | 735 | |
330c90a5 EK |
736 | irq -= IRQ_EINT(0); |
737 | if (irq < 8) | |
738 | return EXYNOS4_GPX0(irq); | |
739 | ||
740 | irq -= 8; | |
741 | if (irq < 8) | |
742 | return EXYNOS4_GPX1(irq); | |
743 | ||
744 | irq -= 8; | |
745 | if (irq < 8) | |
746 | return EXYNOS4_GPX2(irq); | |
747 | ||
748 | irq -= 8; | |
749 | if (irq < 8) | |
750 | return EXYNOS4_GPX3(irq); | |
751 | ||
752 | return -EINVAL; | |
753 | } | |
754 | ||
755 | static inline int exynos5_irq_to_gpio(unsigned int irq) | |
756 | { | |
757 | if (irq < IRQ_EINT(0)) | |
758 | return -EINVAL; | |
759 | ||
760 | irq -= IRQ_EINT(0); | |
761 | if (irq < 8) | |
762 | return EXYNOS5_GPX0(irq); | |
763 | ||
764 | irq -= 8; | |
765 | if (irq < 8) | |
766 | return EXYNOS5_GPX1(irq); | |
767 | ||
768 | irq -= 8; | |
769 | if (irq < 8) | |
770 | return EXYNOS5_GPX2(irq); | |
cc511b8d | 771 | |
330c90a5 EK |
772 | irq -= 8; |
773 | if (irq < 8) | |
774 | return EXYNOS5_GPX3(irq); | |
775 | ||
776 | return -EINVAL; | |
cc511b8d KK |
777 | } |
778 | ||
bb19a751 KK |
779 | static unsigned int exynos4_eint0_15_src_int[16] = { |
780 | EXYNOS4_IRQ_EINT0, | |
781 | EXYNOS4_IRQ_EINT1, | |
782 | EXYNOS4_IRQ_EINT2, | |
783 | EXYNOS4_IRQ_EINT3, | |
784 | EXYNOS4_IRQ_EINT4, | |
785 | EXYNOS4_IRQ_EINT5, | |
786 | EXYNOS4_IRQ_EINT6, | |
787 | EXYNOS4_IRQ_EINT7, | |
788 | EXYNOS4_IRQ_EINT8, | |
789 | EXYNOS4_IRQ_EINT9, | |
790 | EXYNOS4_IRQ_EINT10, | |
791 | EXYNOS4_IRQ_EINT11, | |
792 | EXYNOS4_IRQ_EINT12, | |
793 | EXYNOS4_IRQ_EINT13, | |
794 | EXYNOS4_IRQ_EINT14, | |
795 | EXYNOS4_IRQ_EINT15, | |
796 | }; | |
cc511b8d | 797 | |
bb19a751 KK |
798 | static unsigned int exynos5_eint0_15_src_int[16] = { |
799 | EXYNOS5_IRQ_EINT0, | |
800 | EXYNOS5_IRQ_EINT1, | |
801 | EXYNOS5_IRQ_EINT2, | |
802 | EXYNOS5_IRQ_EINT3, | |
803 | EXYNOS5_IRQ_EINT4, | |
804 | EXYNOS5_IRQ_EINT5, | |
805 | EXYNOS5_IRQ_EINT6, | |
806 | EXYNOS5_IRQ_EINT7, | |
807 | EXYNOS5_IRQ_EINT8, | |
808 | EXYNOS5_IRQ_EINT9, | |
809 | EXYNOS5_IRQ_EINT10, | |
810 | EXYNOS5_IRQ_EINT11, | |
811 | EXYNOS5_IRQ_EINT12, | |
812 | EXYNOS5_IRQ_EINT13, | |
813 | EXYNOS5_IRQ_EINT14, | |
814 | EXYNOS5_IRQ_EINT15, | |
815 | }; | |
330c90a5 | 816 | static inline void exynos_irq_eint_mask(struct irq_data *data) |
cc511b8d KK |
817 | { |
818 | u32 mask; | |
819 | ||
820 | spin_lock(&eint_lock); | |
330c90a5 EK |
821 | mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); |
822 | mask |= EINT_OFFSET_BIT(data->irq); | |
823 | __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); | |
cc511b8d KK |
824 | spin_unlock(&eint_lock); |
825 | } | |
826 | ||
330c90a5 | 827 | static void exynos_irq_eint_unmask(struct irq_data *data) |
cc511b8d KK |
828 | { |
829 | u32 mask; | |
830 | ||
831 | spin_lock(&eint_lock); | |
330c90a5 EK |
832 | mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq)); |
833 | mask &= ~(EINT_OFFSET_BIT(data->irq)); | |
834 | __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq)); | |
cc511b8d KK |
835 | spin_unlock(&eint_lock); |
836 | } | |
837 | ||
330c90a5 | 838 | static inline void exynos_irq_eint_ack(struct irq_data *data) |
cc511b8d | 839 | { |
330c90a5 EK |
840 | __raw_writel(EINT_OFFSET_BIT(data->irq), |
841 | EINT_PEND(exynos_eint_base, data->irq)); | |
cc511b8d KK |
842 | } |
843 | ||
330c90a5 | 844 | static void exynos_irq_eint_maskack(struct irq_data *data) |
cc511b8d | 845 | { |
330c90a5 EK |
846 | exynos_irq_eint_mask(data); |
847 | exynos_irq_eint_ack(data); | |
cc511b8d KK |
848 | } |
849 | ||
330c90a5 | 850 | static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type) |
cc511b8d KK |
851 | { |
852 | int offs = EINT_OFFSET(data->irq); | |
853 | int shift; | |
854 | u32 ctrl, mask; | |
855 | u32 newvalue = 0; | |
856 | ||
857 | switch (type) { | |
858 | case IRQ_TYPE_EDGE_RISING: | |
859 | newvalue = S5P_IRQ_TYPE_EDGE_RISING; | |
860 | break; | |
861 | ||
862 | case IRQ_TYPE_EDGE_FALLING: | |
863 | newvalue = S5P_IRQ_TYPE_EDGE_FALLING; | |
864 | break; | |
865 | ||
866 | case IRQ_TYPE_EDGE_BOTH: | |
867 | newvalue = S5P_IRQ_TYPE_EDGE_BOTH; | |
868 | break; | |
869 | ||
870 | case IRQ_TYPE_LEVEL_LOW: | |
871 | newvalue = S5P_IRQ_TYPE_LEVEL_LOW; | |
872 | break; | |
873 | ||
874 | case IRQ_TYPE_LEVEL_HIGH: | |
875 | newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; | |
876 | break; | |
877 | ||
878 | default: | |
879 | printk(KERN_ERR "No such irq type %d", type); | |
880 | return -EINVAL; | |
881 | } | |
882 | ||
883 | shift = (offs & 0x7) * 4; | |
884 | mask = 0x7 << shift; | |
885 | ||
886 | spin_lock(&eint_lock); | |
330c90a5 | 887 | ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq)); |
cc511b8d KK |
888 | ctrl &= ~mask; |
889 | ctrl |= newvalue << shift; | |
330c90a5 | 890 | __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq)); |
cc511b8d KK |
891 | spin_unlock(&eint_lock); |
892 | ||
330c90a5 EK |
893 | if (soc_is_exynos5250()) |
894 | s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); | |
895 | else | |
896 | s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf)); | |
cc511b8d KK |
897 | |
898 | return 0; | |
899 | } | |
900 | ||
330c90a5 EK |
901 | static struct irq_chip exynos_irq_eint = { |
902 | .name = "exynos-eint", | |
903 | .irq_mask = exynos_irq_eint_mask, | |
904 | .irq_unmask = exynos_irq_eint_unmask, | |
905 | .irq_mask_ack = exynos_irq_eint_maskack, | |
906 | .irq_ack = exynos_irq_eint_ack, | |
907 | .irq_set_type = exynos_irq_eint_set_type, | |
cc511b8d KK |
908 | #ifdef CONFIG_PM |
909 | .irq_set_wake = s3c_irqext_wake, | |
910 | #endif | |
911 | }; | |
912 | ||
913 | /* | |
914 | * exynos4_irq_demux_eint | |
915 | * | |
916 | * This function demuxes the IRQ from from EINTs 16 to 31. | |
917 | * It is designed to be inlined into the specific handler | |
918 | * s5p_irq_demux_eintX_Y. | |
919 | * | |
920 | * Each EINT pend/mask registers handle eight of them. | |
921 | */ | |
330c90a5 | 922 | static inline void exynos_irq_demux_eint(unsigned int start) |
cc511b8d KK |
923 | { |
924 | unsigned int irq; | |
925 | ||
330c90a5 EK |
926 | u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start)); |
927 | u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start)); | |
cc511b8d KK |
928 | |
929 | status &= ~mask; | |
930 | status &= 0xff; | |
931 | ||
932 | while (status) { | |
933 | irq = fls(status) - 1; | |
934 | generic_handle_irq(irq + start); | |
935 | status &= ~(1 << irq); | |
936 | } | |
937 | } | |
938 | ||
330c90a5 | 939 | static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) |
cc511b8d KK |
940 | { |
941 | struct irq_chip *chip = irq_get_chip(irq); | |
942 | chained_irq_enter(chip, desc); | |
330c90a5 EK |
943 | exynos_irq_demux_eint(IRQ_EINT(16)); |
944 | exynos_irq_demux_eint(IRQ_EINT(24)); | |
cc511b8d KK |
945 | chained_irq_exit(chip, desc); |
946 | } | |
947 | ||
bb19a751 | 948 | static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
cc511b8d KK |
949 | { |
950 | u32 *irq_data = irq_get_handler_data(irq); | |
951 | struct irq_chip *chip = irq_get_chip(irq); | |
952 | ||
953 | chained_irq_enter(chip, desc); | |
954 | chip->irq_mask(&desc->irq_data); | |
955 | ||
956 | if (chip->irq_ack) | |
957 | chip->irq_ack(&desc->irq_data); | |
958 | ||
959 | generic_handle_irq(*irq_data); | |
960 | ||
961 | chip->irq_unmask(&desc->irq_data); | |
962 | chained_irq_exit(chip, desc); | |
963 | } | |
964 | ||
330c90a5 | 965 | static int __init exynos_init_irq_eint(void) |
cc511b8d KK |
966 | { |
967 | int irq; | |
968 | ||
fef05c29 TA |
969 | #ifdef CONFIG_PINCTRL_SAMSUNG |
970 | /* | |
971 | * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf | |
972 | * functionality along with support for external gpio and wakeup | |
973 | * interrupts. If the samsung pinctrl driver is enabled and includes | |
974 | * the wakeup interrupt support, then the setting up external wakeup | |
975 | * interrupts here can be skipped. This check here is temporary to | |
976 | * allow exynos4 platforms that do not use Samsung pinctrl driver to | |
977 | * co-exist with platforms that do. When all of the Samsung Exynos4 | |
978 | * platforms switch over to using the pinctrl driver, the wakeup | |
979 | * interrupt support code here can be completely removed. | |
980 | */ | |
981 | struct device_node *pctrl_np, *wkup_np; | |
982 | const char *pctrl_compat = "samsung,pinctrl-exynos4210"; | |
983 | const char *wkup_compat = "samsung,exynos4210-wakeup-eint"; | |
984 | ||
985 | for_each_compatible_node(pctrl_np, NULL, pctrl_compat) { | |
986 | if (of_device_is_available(pctrl_np)) { | |
987 | wkup_np = of_find_compatible_node(pctrl_np, NULL, | |
988 | wkup_compat); | |
989 | if (wkup_np) | |
990 | return -ENODEV; | |
991 | } | |
992 | } | |
993 | #endif | |
994 | ||
94c7ca71 | 995 | if (soc_is_exynos5250()) |
330c90a5 EK |
996 | exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K); |
997 | else | |
998 | exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K); | |
999 | ||
1000 | if (exynos_eint_base == NULL) { | |
1001 | pr_err("unable to ioremap for EINT base address\n"); | |
1002 | return -ENOMEM; | |
1003 | } | |
94c7ca71 | 1004 | |
cc511b8d | 1005 | for (irq = 0 ; irq <= 31 ; irq++) { |
330c90a5 | 1006 | irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint, |
cc511b8d KK |
1007 | handle_level_irq); |
1008 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); | |
1009 | } | |
1010 | ||
330c90a5 | 1011 | irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31); |
cc511b8d KK |
1012 | |
1013 | for (irq = 0 ; irq <= 15 ; irq++) { | |
1014 | eint0_15_data[irq] = IRQ_EINT(irq); | |
1015 | ||
bb19a751 KK |
1016 | if (soc_is_exynos5250()) { |
1017 | irq_set_handler_data(exynos5_eint0_15_src_int[irq], | |
1018 | &eint0_15_data[irq]); | |
1019 | irq_set_chained_handler(exynos5_eint0_15_src_int[irq], | |
1020 | exynos_irq_eint0_15); | |
1021 | } else { | |
1022 | irq_set_handler_data(exynos4_eint0_15_src_int[irq], | |
1023 | &eint0_15_data[irq]); | |
1024 | irq_set_chained_handler(exynos4_eint0_15_src_int[irq], | |
1025 | exynos_irq_eint0_15); | |
1026 | } | |
cc511b8d KK |
1027 | } |
1028 | ||
1029 | return 0; | |
1030 | } | |
330c90a5 | 1031 | arch_initcall(exynos_init_irq_eint); |