[deliverable/linux.git] / arch / arm / mach-exynos / common.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Common Codes for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <clocksource/samsung_pwm.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>

#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/cacheflush.h>

#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>

#include "common.h"
#define L2_AUX_VAL 0x7C470001
#define L2_AUX_MASK 0xC200ffff

static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";

static void exynos4_map_io(void);
static void exynos5_map_io(void);
static int exynos_init(void);

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= EXYNOS4210_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4210,
	}, {
		.idcode		= EXYNOS4212_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4212,
	}, {
		.idcode		= EXYNOS4412_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4412,
	}, {
		.idcode		= EXYNOS5250_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5_map_io,
		.init		= exynos_init,
		.name		= name_exynos5250,
	}, {
		.idcode		= EXYNOS5420_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5_map_io,
		.init		= exynos_init,
		.name		= name_exynos5420,
	}, {
		.idcode		= EXYNOS5440_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.init		= exynos_init,
		.name		= name_exynos5440,
	},
};

/* Initial IO mappings */

static struct map_desc exynos4_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_L2CC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC0,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC1,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc1[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4210_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4x12_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5250_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
		.length		= 144 * SZ_1K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	},
};

void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
	__raw_writel(0x1, S5P_SWRESET);
}

void exynos5_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	u32 val;
	void __iomem *addr;

	val = 0x1;
	addr = EXYNOS_SWRESET;

	if (of_machine_is_compatible("samsung,exynos5440")) {
		u32 status;
		np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");

		addr = of_iomap(np, 0) + 0xbc;
		status = __raw_readl(addr);

		addr = of_iomap(np, 0) + 0xcc;
		val = __raw_readl(addr);

		val = (val & 0xffff0000) | (status & 0xffff);
	}

	__raw_writel(val, addr);
}

void __init exynos_init_late(void)
{
	if (of_machine_is_compatible("samsung,exynos5440"))
		/* to be supported later */
		return;

	exynos_pm_late_initcall();
}

static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
					int depth, void *data)
{
	struct map_desc iodesc;
	__be32 *reg;
	unsigned long len;

	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
		!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
		return 0;

	reg = of_get_flat_dt_prop(node, "reg", &len);
	if (reg == NULL || len != (sizeof(unsigned long) * 2))
		return 0;

	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	iodesc.length = be32_to_cpu(reg[1]) - 1;
	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	iodesc.type = MT_DEVICE;
	iotable_init(&iodesc, 1);
	return 1;
}

/*
 * exynos_map_io
 *
 * register the standard cpu IO areas
 */

void __init exynos_init_io(void)
{
	debug_ll_io_init();

	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);

	/* detect cpu id and rev. */
	s5p_init_cpu(S5P_VA_CHIPID);

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

static void __init exynos4_map_io(void)
{
	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
		iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	else
		iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));

	if (soc_is_exynos4210())
		iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	if (soc_is_exynos4212() || soc_is_exynos4412())
		iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
}

static void __init exynos5_map_io(void)
{
	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));

	if (soc_is_exynos5250())
		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}

void __init exynos_init_time(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
}

struct bus_type exynos_subsys = {
	.name		= "exynos-core",
	.dev_name	= "exynos-core",
};

static struct device exynos4_dev = {
	.bus	= &exynos_subsys,
};

static int __init exynos_core_init(void)
{
	return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);

static int __init exynos4_l2x0_cache_init(void)
{
	int ret;

	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
	if (ret)
		return ret;

	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
	return 0;
}
early_initcall(exynos4_l2x0_cache_init);

static int __init exynos_init(void)
{
	printk(KERN_INFO "EXYNOS: Initializing architecture\n");

	return device_register(&exynos4_dev);
}
Commit	Line	Data
cc511b8d KK	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Common Codes for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
68a433f1	13	#include <linux/bitops.h>
cc511b8d KK	14	#include <linux/interrupt.h>
cc511b8d KK	15	#include <linux/irq.h>
a900e5d9	16	#include <linux/irqchip.h>
cc511b8d	17	#include <linux/io.h>
7affca35	18	#include <linux/device.h>
cc511b8d	19	#include <linux/gpio.h>
68a433f1	20	#include <clocksource/samsung_pwm.h>
cc511b8d KK	21	#include <linux/sched.h>
cc511b8d KK	22	#include <linux/serial_core.h>
237c78be	23	#include <linux/of.h>
5b7897db	24	#include <linux/of_fdt.h>
237c78be	25	#include <linux/of_irq.h>
1e60bc0b TA	26	#include <linux/export.h>
1e60bc0b TA	27	#include <linux/irqdomain.h>
e873a47c	28	#include <linux/of_address.h>
6923ae4b TA	29	#include <linux/clocksource.h>
6923ae4b TA	30	#include <linux/clk-provider.h>
520f7bd7	31	#include <linux/irqchip/arm-gic.h>
de88cbb7	32	#include <linux/irqchip/chained_irq.h>
cc511b8d KK	33
cc511b8d KK	34	#include <asm/proc-fns.h>
40ba95fd	35	#include <asm/exception.h>
cc511b8d	36	#include <asm/hardware/cache-l2x0.h>
cc511b8d KK	37	#include <asm/mach/map.h>
cc511b8d KK	38	#include <asm/mach/irq.h>
b756a50f	39	#include <asm/cacheflush.h>
cc511b8d KK	40
	41	#include <mach/regs-irq.h>
	42	#include <mach/regs-pmu.h>
cc511b8d KK	43
cc511b8d KK	44	#include <plat/cpu.h>
cc511b8d	45	#include <plat/pm.h>
cc511b8d KK	46	#include <plat/regs-serial.h>
	47
	48	#include "common.h"
6cdeddcc ADK	49	#define L2_AUX_VAL 0x7C470001
6cdeddcc ADK	50	#define L2_AUX_MASK 0xC200ffff
cc511b8d	51
cc511b8d KK	52	static const char name_exynos4210[] = "EXYNOS4210";
	53	static const char name_exynos4212[] = "EXYNOS4212";
	54	static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71	55	static const char name_exynos5250[] = "EXYNOS5250";
191d754f	56	static const char name_exynos5420[] = "EXYNOS5420";
2edb36c4	57	static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d	58
906c789c	59	static void exynos4_map_io(void);
94c7ca71	60	static void exynos5_map_io(void);
906c789c	61	static int exynos_init(void);
cc511b8d KK	62
	63	static struct cpu_table cpu_ids[] __initdata = {
	64	{
	65	.idcode = EXYNOS4210_CPU_ID,
	66	.idmask = EXYNOS4_CPU_MASK,
	67	.map_io = exynos4_map_io,
cc511b8d KK	68	.init = exynos_init,
	69	.name = name_exynos4210,
	70	}, {
	71	.idcode = EXYNOS4212_CPU_ID,
	72	.idmask = EXYNOS4_CPU_MASK,
	73	.map_io = exynos4_map_io,
cc511b8d KK	74	.init = exynos_init,
	75	.name = name_exynos4212,
	76	}, {
	77	.idcode = EXYNOS4412_CPU_ID,
	78	.idmask = EXYNOS4_CPU_MASK,
	79	.map_io = exynos4_map_io,
cc511b8d KK	80	.init = exynos_init,
cc511b8d KK	81	.name = name_exynos4412,
94c7ca71 KK	82	}, {
	83	.idcode = EXYNOS5250_SOC_ID,
	84	.idmask = EXYNOS5_SOC_MASK,
	85	.map_io = exynos5_map_io,
94c7ca71 KK	86	.init = exynos_init,
94c7ca71 KK	87	.name = name_exynos5250,
191d754f CK	88	}, {
	89	.idcode = EXYNOS5420_SOC_ID,
	90	.idmask = EXYNOS5_SOC_MASK,
	91	.map_io = exynos5_map_io,
	92	.init = exynos_init,
	93	.name = name_exynos5420,
2edb36c4 KK	94	}, {
	95	.idcode = EXYNOS5440_SOC_ID,
	96	.idmask = EXYNOS5_SOC_MASK,
2edb36c4 KK	97	.init = exynos_init,
2edb36c4 KK	98	.name = name_exynos5440,
cc511b8d KK	99	},
	100	};
	101
	102	/* Initial IO mappings */
	103
94c7ca71 KK	104	static struct map_desc exynos4_iodesc[] __initdata = {
94c7ca71 KK	105	{
cc511b8d KK	106	.virtual = (unsigned long)S3C_VA_SYS,
	107	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
	108	.length = SZ_64K,
	109	.type = MT_DEVICE,
	110	}, {
	111	.virtual = (unsigned long)S3C_VA_TIMER,
	112	.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
	113	.length = SZ_16K,
	114	.type = MT_DEVICE,
	115	}, {
	116	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	117	.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
	118	.length = SZ_4K,
	119	.type = MT_DEVICE,
	120	}, {
	121	.virtual = (unsigned long)S5P_VA_SROMC,
	122	.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
	123	.length = SZ_4K,
	124	.type = MT_DEVICE,
	125	}, {
	126	.virtual = (unsigned long)S5P_VA_SYSTIMER,
	127	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
	128	.length = SZ_4K,
	129	.type = MT_DEVICE,
	130	}, {
	131	.virtual = (unsigned long)S5P_VA_PMU,
	132	.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
	133	.length = SZ_64K,
	134	.type = MT_DEVICE,
	135	}, {
	136	.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
	137	.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
	138	.length = SZ_4K,
	139	.type = MT_DEVICE,
	140	}, {
	141	.virtual = (unsigned long)S5P_VA_GIC_CPU,
	142	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
	143	.length = SZ_64K,
	144	.type = MT_DEVICE,
	145	}, {
	146	.virtual = (unsigned long)S5P_VA_GIC_DIST,
	147	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
	148	.length = SZ_64K,
	149	.type = MT_DEVICE,
94c7ca71	150	}, {
cc511b8d KK	151	.virtual = (unsigned long)S5P_VA_CMU,
	152	.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
	153	.length = SZ_128K,
	154	.type = MT_DEVICE,
	155	}, {
	156	.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
	157	.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
	158	.length = SZ_8K,
	159	.type = MT_DEVICE,
	160	}, {
	161	.virtual = (unsigned long)S5P_VA_L2CC,
	162	.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
	163	.length = SZ_4K,
	164	.type = MT_DEVICE,
cc511b8d KK	165	}, {
	166	.virtual = (unsigned long)S5P_VA_DMC0,
	167	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08 MH	168	.length = SZ_64K,
	169	.type = MT_DEVICE,
	170	}, {
	171	.virtual = (unsigned long)S5P_VA_DMC1,
	172	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
	173	.length = SZ_64K,
cc511b8d	174	.type = MT_DEVICE,
cc511b8d KK	175	}, {
	176	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
	177	.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
	178	.length = SZ_4K,
	179	.type = MT_DEVICE,
	180	},
	181	};
	182
	183	static struct map_desc exynos4_iodesc0[] __initdata = {
	184	{
	185	.virtual = (unsigned long)S5P_VA_SYSRAM,
	186	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
	187	.length = SZ_4K,
	188	.type = MT_DEVICE,
	189	},
	190	};
	191
	192	static struct map_desc exynos4_iodesc1[] __initdata = {
	193	{
	194	.virtual = (unsigned long)S5P_VA_SYSRAM,
	195	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
	196	.length = SZ_4K,
	197	.type = MT_DEVICE,
	198	},
	199	};
	200
41de8986 TF	201	static struct map_desc exynos4210_iodesc[] __initdata = {
	202	{
	203	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	204	.pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
	205	.length = SZ_4K,
	206	.type = MT_DEVICE,
	207	},
	208	};
	209
	210	static struct map_desc exynos4x12_iodesc[] __initdata = {
	211	{
	212	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	213	.pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
	214	.length = SZ_4K,
	215	.type = MT_DEVICE,
	216	},
	217	};
	218
	219	static struct map_desc exynos5250_iodesc[] __initdata = {
	220	{
	221	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	222	.pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
	223	.length = SZ_4K,
	224	.type = MT_DEVICE,
	225	},
	226	};
	227
94c7ca71 KK	228	static struct map_desc exynos5_iodesc[] __initdata = {
	229	{
	230	.virtual = (unsigned long)S3C_VA_SYS,
	231	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
	232	.length = SZ_64K,
	233	.type = MT_DEVICE,
	234	}, {
	235	.virtual = (unsigned long)S3C_VA_TIMER,
	236	.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
	237	.length = SZ_16K,
	238	.type = MT_DEVICE,
	239	}, {
	240	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	241	.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
	242	.length = SZ_4K,
	243	.type = MT_DEVICE,
	244	}, {
	245	.virtual = (unsigned long)S5P_VA_SROMC,
	246	.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
	247	.length = SZ_4K,
	248	.type = MT_DEVICE,
94c7ca71 KK	249	}, {
	250	.virtual = (unsigned long)S5P_VA_SYSRAM,
	251	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
	252	.length = SZ_4K,
	253	.type = MT_DEVICE,
	254	}, {
	255	.virtual = (unsigned long)S5P_VA_CMU,
	256	.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
	257	.length = 144 * SZ_1K,
	258	.type = MT_DEVICE,
	259	}, {
	260	.virtual = (unsigned long)S5P_VA_PMU,
	261	.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
	262	.length = SZ_64K,
	263	.type = MT_DEVICE,
2edb36c4 KK	264	},
	265	};
	266
7b6d864b	267	void exynos4_restart(enum reboot_mode mode, const char *cmd)
cc511b8d KK	268	{
	269	__raw_writel(0x1, S5P_SWRESET);
	270	}
	271
7b6d864b	272	void exynos5_restart(enum reboot_mode mode, const char *cmd)
94c7ca71	273	{
60db7e5f	274	struct device_node *np;
2edb36c4 KK	275	u32 val;
	276	void __iomem *addr;
	277
eff4e7c7 CK	278	val = 0x1;
	279	addr = EXYNOS_SWRESET;
	280
	281	if (of_machine_is_compatible("samsung,exynos5440")) {
1ba830c9	282	u32 status;
60db7e5f	283	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
1ba830c9 JL	284
	285	addr = of_iomap(np, 0) + 0xbc;
	286	status = __raw_readl(addr);
	287
60db7e5f	288	addr = of_iomap(np, 0) + 0xcc;
1ba830c9 JL	289	val = __raw_readl(addr);
	290
	291	val = (val & 0xffff0000) \| (status & 0xffff);
2edb36c4 KK	292	}
	293
	294	__raw_writel(val, addr);
94c7ca71 KK	295	}
94c7ca71 KK	296
bb13fabc SG	297	void __init exynos_init_late(void)
bb13fabc SG	298	{
2edb36c4 KK	299	if (of_machine_is_compatible("samsung,exynos5440"))
	300	/* to be supported later */
	301	return;
	302
bb13fabc SG	303	exynos_pm_late_initcall();
	304	}
	305
564d06b1	306	static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
f5f83c71 TA	307	int depth, void *data)
	308	{
	309	struct map_desc iodesc;
	310	__be32 *reg;
	311	unsigned long len;
	312
	313	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
	314	!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
	315	return 0;
	316
	317	reg = of_get_flat_dt_prop(node, "reg", &len);
	318	if (reg == NULL \|\| len != (sizeof(unsigned long) * 2))
	319	return 0;
	320
	321	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	322	iodesc.length = be32_to_cpu(reg[1]) - 1;
	323	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	324	iodesc.type = MT_DEVICE;
	325	iotable_init(&iodesc, 1);
	326	return 1;
	327	}
f5f83c71	328
cc511b8d KK	329	/*
	330	* exynos_map_io
	331	*
	332	* register the standard cpu IO areas
	333	*/
	334
0e2238ec	335	void __init exynos_init_io(void)
cc511b8d	336	{
9c1fcdcc DA	337	debug_ll_io_init();
9c1fcdcc DA	338
04fae596	339	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
2edb36c4	340
cc511b8d KK	341	/* detect cpu id and rev. */
	342	s5p_init_cpu(S5P_VA_CHIPID);
	343
	344	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
	345	}
	346
906c789c	347	static void __init exynos4_map_io(void)
cc511b8d KK	348	{
	349	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
	350
	351	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
	352	iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	353	else
	354	iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
	355
41de8986 TF	356	if (soc_is_exynos4210())
	357	iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	358	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	359	iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
cc511b8d KK	360	}
cc511b8d KK	361
94c7ca71 KK	362	static void __init exynos5_map_io(void)
	363	{
	364	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
41de8986 TF	365
	366	if (soc_is_exynos5250())
	367	iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
94c7ca71 KK	368	}
94c7ca71 KK	369
6923ae4b	370	void __init exynos_init_time(void)
94c7ca71	371	{
3c70348c TF	372	of_clk_init(NULL);
3c70348c TF	373	clocksource_of_init();
94c7ca71 KK	374	}
94c7ca71 KK	375
9ee6af9c TA	376	struct bus_type exynos_subsys = {
	377	.name = "exynos-core",
	378	.dev_name = "exynos-core",
94c7ca71 KK	379	};
94c7ca71 KK	380
7affca35	381	static struct device exynos4_dev = {
9ee6af9c	382	.bus = &exynos_subsys,
94c7ca71 KK	383	};
	384
	385	static int __init exynos_core_init(void)
cc511b8d	386	{
9ee6af9c	387	return subsys_system_register(&exynos_subsys, NULL);
cc511b8d	388	}
94c7ca71	389	core_initcall(exynos_core_init);
cc511b8d	390
cc511b8d KK	391	static int __init exynos4_l2x0_cache_init(void)
cc511b8d KK	392	{
e1b1994e IH	393	int ret;
e1b1994e IH	394
6cdeddcc	395	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
87107d89 AB	396	if (ret)
87107d89 AB	397	return ret;
cc511b8d	398
87107d89 AB	399	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
87107d89 AB	400	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
cc511b8d KK	401	return 0;
cc511b8d KK	402	}
cc511b8d	403	early_initcall(exynos4_l2x0_cache_init);
cc511b8d	404
906c789c	405	static int __init exynos_init(void)
cc511b8d KK	406	{
cc511b8d KK	407	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71	408
9ee6af9c	409	return device_register(&exynos4_dev);
cc511b8d	410	}