[deliverable/linux.git] / arch / arm / mach-exynos / common.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Common Codes for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <clocksource/samsung_pwm.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/clocksource.h>
#include <linux/clk-provider.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>

#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/cacheflush.h>

#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
#include <mach/regs-gpio.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/regs-serial.h>

#include "common.h"
#define L2_AUX_VAL 0x7C470001
#define L2_AUX_MASK 0xC200ffff

static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
static const char name_exynos5440[] = "EXYNOS5440";

static void exynos4_map_io(void);
static void exynos5_map_io(void);
static void exynos5440_map_io(void);
static int exynos_init(void);

unsigned long xxti_f = 0, xusbxti_f = 0;

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= EXYNOS4210_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4210,
	}, {
		.idcode		= EXYNOS4212_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4212,
	}, {
		.idcode		= EXYNOS4412_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init		= exynos_init,
		.name		= name_exynos4412,
	}, {
		.idcode		= EXYNOS5250_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5_map_io,
		.init		= exynos_init,
		.name		= name_exynos5250,
	}, {
		.idcode		= EXYNOS5440_SOC_ID,
		.idmask		= EXYNOS5_SOC_MASK,
		.map_io		= exynos5440_map_io,
		.init		= exynos_init,
		.name		= name_exynos5440,
	},
};

/* Initial IO mappings */

static struct map_desc exynos_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_CHIPID,
		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_UART,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
		.length		= SZ_512K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_L2CC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC0,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC1,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc1[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4210_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4x12_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5250_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
		.length		= 144 * SZ_1K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_UART,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),
		.length		= SZ_512K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5440_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_UART,
		.pfn		= __phys_to_pfn(EXYNOS5440_PA_UART0),
		.length		= SZ_512K,
		.type		= MT_DEVICE,
	},
};

void exynos4_restart(char mode, const char *cmd)
{
	__raw_writel(0x1, S5P_SWRESET);
}

void exynos5_restart(char mode, const char *cmd)
{
	struct device_node *np;
	u32 val;
	void __iomem *addr;

	if (of_machine_is_compatible("samsung,exynos5250")) {
		val = 0x1;
		addr = EXYNOS_SWRESET;
	} else if (of_machine_is_compatible("samsung,exynos5440")) {
		u32 status;
		np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");

		addr = of_iomap(np, 0) + 0xbc;
		status = __raw_readl(addr);

		addr = of_iomap(np, 0) + 0xcc;
		val = __raw_readl(addr);

		val = (val & 0xffff0000) | (status & 0xffff);
	} else {
		pr_err("%s: cannot support non-DT\n", __func__);
		return;
	}

	__raw_writel(val, addr);
}

void __init exynos_init_late(void)
{
	if (of_machine_is_compatible("samsung,exynos5440"))
		/* to be supported later */
		return;

	exynos_pm_late_initcall();
}

int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
					int depth, void *data)
{
	struct map_desc iodesc;
	__be32 *reg;
	unsigned long len;

	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
		!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
		return 0;

	reg = of_get_flat_dt_prop(node, "reg", &len);
	if (reg == NULL || len != (sizeof(unsigned long) * 2))
		return 0;

	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	iodesc.length = be32_to_cpu(reg[1]) - 1;
	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	iodesc.type = MT_DEVICE;
	iotable_init(&iodesc, 1);
	return 1;
}

/*
 * exynos_map_io
 *
 * register the standard cpu IO areas
 */

void __init exynos_init_io(struct map_desc *mach_desc, int size)
{
	debug_ll_io_init();

	if (initial_boot_params)
		of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
	else
		iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));

	if (mach_desc)
		iotable_init(mach_desc, size);

	/* detect cpu id and rev. */
	s5p_init_cpu(S5P_VA_CHIPID);

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

static void __init exynos4_map_io(void)
{
	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
		iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	else
		iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));

	if (soc_is_exynos4210())
		iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	if (soc_is_exynos4212() || soc_is_exynos4412())
		iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
}

static void __init exynos5_map_io(void)
{
	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));

	if (soc_is_exynos5250())
		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}

static void __init exynos5440_map_io(void)
{
	iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}

void __init exynos_init_time(void)
{
	of_clk_init(NULL);
	clocksource_of_init();
}

void __init exynos4_init_irq(void)
{
	irqchip_init();
}

void __init exynos5_init_irq(void)
{
	irqchip_init();
}

struct bus_type exynos_subsys = {
	.name		= "exynos-core",
	.dev_name	= "exynos-core",
};

static struct device exynos4_dev = {
	.bus	= &exynos_subsys,
};

static int __init exynos_core_init(void)
{
	return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);

#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
	int ret;

	if (soc_is_exynos5250() || soc_is_exynos5440())
		return 0;

	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
	if (!ret) {
		l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
		clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
		return 0;
	}

	if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
		l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
		/* TAG, Data Latency Control: 2 cycles */
		l2x0_saved_regs.tag_latency = 0x110;

		if (soc_is_exynos4212() || soc_is_exynos4412())
			l2x0_saved_regs.data_latency = 0x120;
		else
			l2x0_saved_regs.data_latency = 0x110;

		l2x0_saved_regs.prefetch_ctrl = 0x30000007;
		l2x0_saved_regs.pwr_ctrl =
			(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);

		l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);

		__raw_writel(l2x0_saved_regs.tag_latency,
				S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
		__raw_writel(l2x0_saved_regs.data_latency,
				S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);

		/* L2X0 Prefetch Control */
		__raw_writel(l2x0_saved_regs.prefetch_ctrl,
				S5P_VA_L2CC + L2X0_PREFETCH_CTRL);

		/* L2X0 Power Control */
		__raw_writel(l2x0_saved_regs.pwr_ctrl,
				S5P_VA_L2CC + L2X0_POWER_CTRL);

		clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
		clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
	}

	l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
	return 0;
}
early_initcall(exynos4_l2x0_cache_init);
#endif

static int __init exynos_init(void)
{
	printk(KERN_INFO "EXYNOS: Initializing architecture\n");

	return device_register(&exynos4_dev);
}
Commit	Line	Data
cc511b8d KK	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Common Codes for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
68a433f1	13	#include <linux/bitops.h>
cc511b8d KK	14	#include <linux/interrupt.h>
cc511b8d KK	15	#include <linux/irq.h>
a900e5d9	16	#include <linux/irqchip.h>
cc511b8d	17	#include <linux/io.h>
7affca35	18	#include <linux/device.h>
cc511b8d	19	#include <linux/gpio.h>
68a433f1	20	#include <clocksource/samsung_pwm.h>
cc511b8d KK	21	#include <linux/sched.h>
cc511b8d KK	22	#include <linux/serial_core.h>
237c78be	23	#include <linux/of.h>
5b7897db	24	#include <linux/of_fdt.h>
237c78be	25	#include <linux/of_irq.h>
1e60bc0b TA	26	#include <linux/export.h>
1e60bc0b TA	27	#include <linux/irqdomain.h>
e873a47c	28	#include <linux/of_address.h>
6923ae4b TA	29	#include <linux/clocksource.h>
6923ae4b TA	30	#include <linux/clk-provider.h>
520f7bd7	31	#include <linux/irqchip/arm-gic.h>
de88cbb7	32	#include <linux/irqchip/chained_irq.h>
cc511b8d KK	33
cc511b8d KK	34	#include <asm/proc-fns.h>
40ba95fd	35	#include <asm/exception.h>
cc511b8d	36	#include <asm/hardware/cache-l2x0.h>
cc511b8d KK	37	#include <asm/mach/map.h>
cc511b8d KK	38	#include <asm/mach/irq.h>
b756a50f	39	#include <asm/cacheflush.h>
cc511b8d KK	40
	41	#include <mach/regs-irq.h>
	42	#include <mach/regs-pmu.h>
	43	#include <mach/regs-gpio.h>
	44
	45	#include <plat/cpu.h>
cc511b8d	46	#include <plat/pm.h>
cc511b8d KK	47	#include <plat/regs-serial.h>
	48
	49	#include "common.h"
6cdeddcc ADK	50	#define L2_AUX_VAL 0x7C470001
6cdeddcc ADK	51	#define L2_AUX_MASK 0xC200ffff
cc511b8d	52
cc511b8d KK	53	static const char name_exynos4210[] = "EXYNOS4210";
	54	static const char name_exynos4212[] = "EXYNOS4212";
	55	static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71	56	static const char name_exynos5250[] = "EXYNOS5250";
2edb36c4	57	static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d	58
906c789c	59	static void exynos4_map_io(void);
94c7ca71	60	static void exynos5_map_io(void);
2edb36c4	61	static void exynos5440_map_io(void);
906c789c	62	static int exynos_init(void);
cc511b8d	63
92744274 TA	64	unsigned long xxti_f = 0, xusbxti_f = 0;
92744274 TA	65
cc511b8d KK	66	static struct cpu_table cpu_ids[] __initdata = {
	67	{
	68	.idcode = EXYNOS4210_CPU_ID,
	69	.idmask = EXYNOS4_CPU_MASK,
	70	.map_io = exynos4_map_io,
cc511b8d KK	71	.init = exynos_init,
	72	.name = name_exynos4210,
	73	}, {
	74	.idcode = EXYNOS4212_CPU_ID,
	75	.idmask = EXYNOS4_CPU_MASK,
	76	.map_io = exynos4_map_io,
cc511b8d KK	77	.init = exynos_init,
	78	.name = name_exynos4212,
	79	}, {
	80	.idcode = EXYNOS4412_CPU_ID,
	81	.idmask = EXYNOS4_CPU_MASK,
	82	.map_io = exynos4_map_io,
cc511b8d KK	83	.init = exynos_init,
cc511b8d KK	84	.name = name_exynos4412,
94c7ca71 KK	85	}, {
	86	.idcode = EXYNOS5250_SOC_ID,
	87	.idmask = EXYNOS5_SOC_MASK,
	88	.map_io = exynos5_map_io,
94c7ca71 KK	89	.init = exynos_init,
94c7ca71 KK	90	.name = name_exynos5250,
2edb36c4 KK	91	}, {
	92	.idcode = EXYNOS5440_SOC_ID,
	93	.idmask = EXYNOS5_SOC_MASK,
	94	.map_io = exynos5440_map_io,
	95	.init = exynos_init,
	96	.name = name_exynos5440,
cc511b8d KK	97	},
	98	};
	99
	100	/* Initial IO mappings */
	101
	102	static struct map_desc exynos_iodesc[] __initdata = {
	103	{
	104	.virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71	105	.pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d KK	106	.length = SZ_4K,
cc511b8d KK	107	.type = MT_DEVICE,
94c7ca71 KK	108	},
	109	};
	110
	111	static struct map_desc exynos4_iodesc[] __initdata = {
	112	{
cc511b8d KK	113	.virtual = (unsigned long)S3C_VA_SYS,
	114	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
	115	.length = SZ_64K,
	116	.type = MT_DEVICE,
	117	}, {
	118	.virtual = (unsigned long)S3C_VA_TIMER,
	119	.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
	120	.length = SZ_16K,
	121	.type = MT_DEVICE,
	122	}, {
	123	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	124	.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
	125	.length = SZ_4K,
	126	.type = MT_DEVICE,
	127	}, {
	128	.virtual = (unsigned long)S5P_VA_SROMC,
	129	.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
	130	.length = SZ_4K,
	131	.type = MT_DEVICE,
	132	}, {
	133	.virtual = (unsigned long)S5P_VA_SYSTIMER,
	134	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
	135	.length = SZ_4K,
	136	.type = MT_DEVICE,
	137	}, {
	138	.virtual = (unsigned long)S5P_VA_PMU,
	139	.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
	140	.length = SZ_64K,
	141	.type = MT_DEVICE,
	142	}, {
	143	.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
	144	.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
	145	.length = SZ_4K,
	146	.type = MT_DEVICE,
	147	}, {
	148	.virtual = (unsigned long)S5P_VA_GIC_CPU,
	149	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
	150	.length = SZ_64K,
	151	.type = MT_DEVICE,
	152	}, {
	153	.virtual = (unsigned long)S5P_VA_GIC_DIST,
	154	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
	155	.length = SZ_64K,
	156	.type = MT_DEVICE,
	157	}, {
	158	.virtual = (unsigned long)S3C_VA_UART,
	159	.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
	160	.length = SZ_512K,
	161	.type = MT_DEVICE,
94c7ca71	162	}, {
cc511b8d KK	163	.virtual = (unsigned long)S5P_VA_CMU,
	164	.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
	165	.length = SZ_128K,
	166	.type = MT_DEVICE,
	167	}, {
	168	.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
	169	.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
	170	.length = SZ_8K,
	171	.type = MT_DEVICE,
	172	}, {
	173	.virtual = (unsigned long)S5P_VA_L2CC,
	174	.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
	175	.length = SZ_4K,
	176	.type = MT_DEVICE,
cc511b8d KK	177	}, {
	178	.virtual = (unsigned long)S5P_VA_DMC0,
	179	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08 MH	180	.length = SZ_64K,
	181	.type = MT_DEVICE,
	182	}, {
	183	.virtual = (unsigned long)S5P_VA_DMC1,
	184	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
	185	.length = SZ_64K,
cc511b8d	186	.type = MT_DEVICE,
cc511b8d KK	187	}, {
	188	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
	189	.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
	190	.length = SZ_4K,
	191	.type = MT_DEVICE,
	192	},
	193	};
	194
	195	static struct map_desc exynos4_iodesc0[] __initdata = {
	196	{
	197	.virtual = (unsigned long)S5P_VA_SYSRAM,
	198	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
	199	.length = SZ_4K,
	200	.type = MT_DEVICE,
	201	},
	202	};
	203
	204	static struct map_desc exynos4_iodesc1[] __initdata = {
	205	{
	206	.virtual = (unsigned long)S5P_VA_SYSRAM,
	207	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
	208	.length = SZ_4K,
	209	.type = MT_DEVICE,
	210	},
	211	};
	212
41de8986 TF	213	static struct map_desc exynos4210_iodesc[] __initdata = {
	214	{
	215	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	216	.pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
	217	.length = SZ_4K,
	218	.type = MT_DEVICE,
	219	},
	220	};
	221
	222	static struct map_desc exynos4x12_iodesc[] __initdata = {
	223	{
	224	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	225	.pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
	226	.length = SZ_4K,
	227	.type = MT_DEVICE,
	228	},
	229	};
	230
	231	static struct map_desc exynos5250_iodesc[] __initdata = {
	232	{
	233	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	234	.pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
	235	.length = SZ_4K,
	236	.type = MT_DEVICE,
	237	},
	238	};
	239
94c7ca71 KK	240	static struct map_desc exynos5_iodesc[] __initdata = {
	241	{
	242	.virtual = (unsigned long)S3C_VA_SYS,
	243	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
	244	.length = SZ_64K,
	245	.type = MT_DEVICE,
	246	}, {
	247	.virtual = (unsigned long)S3C_VA_TIMER,
	248	.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
	249	.length = SZ_16K,
	250	.type = MT_DEVICE,
	251	}, {
	252	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	253	.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
	254	.length = SZ_4K,
	255	.type = MT_DEVICE,
	256	}, {
	257	.virtual = (unsigned long)S5P_VA_SROMC,
	258	.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
	259	.length = SZ_4K,
	260	.type = MT_DEVICE,
94c7ca71 KK	261	}, {
	262	.virtual = (unsigned long)S5P_VA_SYSRAM,
	263	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
	264	.length = SZ_4K,
	265	.type = MT_DEVICE,
	266	}, {
	267	.virtual = (unsigned long)S5P_VA_CMU,
	268	.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
	269	.length = 144 * SZ_1K,
	270	.type = MT_DEVICE,
	271	}, {
	272	.virtual = (unsigned long)S5P_VA_PMU,
	273	.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
	274	.length = SZ_64K,
	275	.type = MT_DEVICE,
94c7ca71 KK	276	}, {
	277	.virtual = (unsigned long)S3C_VA_UART,
	278	.pfn = __phys_to_pfn(EXYNOS5_PA_UART),
	279	.length = SZ_512K,
	280	.type = MT_DEVICE,
94c7ca71 KK	281	},
	282	};
	283
2edb36c4 KK	284	static struct map_desc exynos5440_iodesc0[] __initdata = {
	285	{
	286	.virtual = (unsigned long)S3C_VA_UART,
	287	.pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
	288	.length = SZ_512K,
	289	.type = MT_DEVICE,
	290	},
	291	};
	292
9eb48595	293	void exynos4_restart(char mode, const char *cmd)
cc511b8d KK	294	{
	295	__raw_writel(0x1, S5P_SWRESET);
	296	}
	297
94c7ca71 KK	298	void exynos5_restart(char mode, const char *cmd)
94c7ca71 KK	299	{
60db7e5f	300	struct device_node *np;
2edb36c4 KK	301	u32 val;
	302	void __iomem *addr;
	303
	304	if (of_machine_is_compatible("samsung,exynos5250")) {
	305	val = 0x1;
	306	addr = EXYNOS_SWRESET;
	307	} else if (of_machine_is_compatible("samsung,exynos5440")) {
1ba830c9	308	u32 status;
60db7e5f	309	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
1ba830c9 JL	310
	311	addr = of_iomap(np, 0) + 0xbc;
	312	status = __raw_readl(addr);
	313
60db7e5f	314	addr = of_iomap(np, 0) + 0xcc;
1ba830c9 JL	315	val = __raw_readl(addr);
	316
	317	val = (val & 0xffff0000) \| (status & 0xffff);
2edb36c4 KK	318	} else {
	319	pr_err("%s: cannot support non-DT\n", __func__);
	320	return;
	321	}
	322
	323	__raw_writel(val, addr);
94c7ca71 KK	324	}
94c7ca71 KK	325
bb13fabc SG	326	void __init exynos_init_late(void)
bb13fabc SG	327	{
2edb36c4 KK	328	if (of_machine_is_compatible("samsung,exynos5440"))
	329	/* to be supported later */
	330	return;
	331
bb13fabc SG	332	exynos_pm_late_initcall();
	333	}
	334
f5f83c71 TA	335	int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
	336	int depth, void *data)
	337	{
	338	struct map_desc iodesc;
	339	__be32 *reg;
	340	unsigned long len;
	341
	342	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
	343	!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
	344	return 0;
	345
	346	reg = of_get_flat_dt_prop(node, "reg", &len);
	347	if (reg == NULL \|\| len != (sizeof(unsigned long) * 2))
	348	return 0;
	349
	350	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	351	iodesc.length = be32_to_cpu(reg[1]) - 1;
	352	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	353	iodesc.type = MT_DEVICE;
	354	iotable_init(&iodesc, 1);
	355	return 1;
	356	}
f5f83c71	357
cc511b8d KK	358	/*
	359	* exynos_map_io
	360	*
	361	* register the standard cpu IO areas
	362	*/
	363
	364	void __init exynos_init_io(struct map_desc *mach_desc, int size)
	365	{
9c1fcdcc DA	366	debug_ll_io_init();
9c1fcdcc DA	367
f5f83c71 TA	368	if (initial_boot_params)
	369	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
	370	else
f5f83c71	371	iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
2edb36c4	372
cc511b8d KK	373	if (mach_desc)
	374	iotable_init(mach_desc, size);
	375
	376	/* detect cpu id and rev. */
	377	s5p_init_cpu(S5P_VA_CHIPID);
	378
	379	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
	380	}
	381
906c789c	382	static void __init exynos4_map_io(void)
cc511b8d KK	383	{
	384	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
	385
	386	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
	387	iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	388	else
	389	iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
	390
41de8986 TF	391	if (soc_is_exynos4210())
	392	iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	393	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	394	iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
cc511b8d KK	395	}
cc511b8d KK	396
94c7ca71 KK	397	static void __init exynos5_map_io(void)
	398	{
	399	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
41de8986 TF	400
	401	if (soc_is_exynos5250())
	402	iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
94c7ca71 KK	403	}
94c7ca71 KK	404
2edb36c4 KK	405	static void __init exynos5440_map_io(void)
	406	{
	407	iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
	408	}
	409
6923ae4b	410	void __init exynos_init_time(void)
94c7ca71	411	{
3c70348c TF	412	of_clk_init(NULL);
3c70348c TF	413	clocksource_of_init();
94c7ca71 KK	414	}
94c7ca71 KK	415
cc511b8d KK	416	void __init exynos4_init_irq(void)
cc511b8d KK	417	{
d243997f	418	irqchip_init();
cc511b8d KK	419	}
cc511b8d KK	420
94c7ca71 KK	421	void __init exynos5_init_irq(void)
94c7ca71 KK	422	{
0529e315	423	irqchip_init();
cc511b8d KK	424	}
cc511b8d KK	425
9ee6af9c TA	426	struct bus_type exynos_subsys = {
	427	.name = "exynos-core",
	428	.dev_name = "exynos-core",
94c7ca71 KK	429	};
94c7ca71 KK	430
7affca35	431	static struct device exynos4_dev = {
9ee6af9c	432	.bus = &exynos_subsys,
94c7ca71 KK	433	};
	434
	435	static int __init exynos_core_init(void)
cc511b8d	436	{
9ee6af9c	437	return subsys_system_register(&exynos_subsys, NULL);
cc511b8d	438	}
94c7ca71	439	core_initcall(exynos_core_init);
cc511b8d KK	440
	441	#ifdef CONFIG_CACHE_L2X0
	442	static int __init exynos4_l2x0_cache_init(void)
	443	{
e1b1994e IH	444	int ret;
e1b1994e IH	445
2edb36c4	446	if (soc_is_exynos5250() \|\| soc_is_exynos5440())
94c7ca71 KK	447	return 0;
94c7ca71 KK	448
6cdeddcc ADK	449	ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
	450	if (!ret) {
	451	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
	452	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
	453	return 0;
	454	}
cc511b8d	455
b756a50f ADK	456	if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
	457	l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
	458	/* TAG, Data Latency Control: 2 cycles */
	459	l2x0_saved_regs.tag_latency = 0x110;
cc511b8d	460
b756a50f ADK	461	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	462	l2x0_saved_regs.data_latency = 0x120;
	463	else
	464	l2x0_saved_regs.data_latency = 0x110;
	465
	466	l2x0_saved_regs.prefetch_ctrl = 0x30000007;
	467	l2x0_saved_regs.pwr_ctrl =
	468	(L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN);
cc511b8d	469
b756a50f	470	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d	471
b756a50f ADK	472	__raw_writel(l2x0_saved_regs.tag_latency,
	473	S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
	474	__raw_writel(l2x0_saved_regs.data_latency,
	475	S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d	476
b756a50f ADK	477	/* L2X0 Prefetch Control */
	478	__raw_writel(l2x0_saved_regs.prefetch_ctrl,
	479	S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
	480
	481	/* L2X0 Power Control */
	482	__raw_writel(l2x0_saved_regs.pwr_ctrl,
	483	S5P_VA_L2CC + L2X0_POWER_CTRL);
	484
	485	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
	486	clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
	487	}
cc511b8d	488
6cdeddcc	489	l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d KK	490	return 0;
cc511b8d KK	491	}
cc511b8d KK	492	early_initcall(exynos4_l2x0_cache_init);
	493	#endif
	494
906c789c	495	static int __init exynos_init(void)
cc511b8d KK	496	{
cc511b8d KK	497	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71	498
9ee6af9c	499	return device_register(&exynos4_dev);
cc511b8d	500	}