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ARM: EXYNOS: Add irq_domain support for interrupt combiner
[deliverable/linux.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
7affca35 16#include <linux/device.h>
cc511b8d
KK		 17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
237c78be
AB		 20#include <linux/of.h>
21#include <linux/of_irq.h>
1e60bc0b
TA		 22#include <linux/export.h>
23#include <linux/irqdomain.h>
cc511b8d
KK		 24
25#include <asm/proc-fns.h>
40ba95fd 26#include <asm/exception.h>
cc511b8d
KK		 27#include <asm/hardware/cache-l2x0.h>
28#include <asm/hardware/gic.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
b756a50f 31#include <asm/cacheflush.h>
cc511b8d
KK		 32
33#include <mach/regs-irq.h>
34#include <mach/regs-pmu.h>
35#include <mach/regs-gpio.h>
b756a50f 36#include <mach/pmu.h>
cc511b8d
KK		 37
38#include <plat/cpu.h>
39#include <plat/clock.h>
40#include <plat/devs.h>
41#include <plat/pm.h>
cc511b8d
KK		 42#include <plat/sdhci.h>
43#include <plat/gpio-cfg.h>
44#include <plat/adc-core.h>
45#include <plat/fb-core.h>
46#include <plat/fimc-core.h>
47#include <plat/iic-core.h>
48#include <plat/tv-core.h>
49#include <plat/regs-serial.h>
50
51#include "common.h"
6cdeddcc
ADK		 52#define L2_AUX_VAL 0x7C470001
53#define L2_AUX_MASK 0xC200ffff
cc511b8d 54
cc511b8d
KK		 55static const char name_exynos4210[] = "EXYNOS4210";
56static const char name_exynos4212[] = "EXYNOS4212";
57static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 58static const char name_exynos5250[] = "EXYNOS5250";
cc511b8d 59
906c789c 60static void exynos4_map_io(void);
94c7ca71 61static void exynos5_map_io(void);
906c789c 62static void exynos4_init_clocks(int xtal);
94c7ca71 63static void exynos5_init_clocks(int xtal);
920f4880 64static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 65static int exynos_init(void);
cc511b8d
KK		 66
67static struct cpu_table cpu_ids[] __initdata = {
68 {
69 .idcode = EXYNOS4210_CPU_ID,
70 .idmask = EXYNOS4_CPU_MASK,
71 .map_io = exynos4_map_io,
72 .init_clocks = exynos4_init_clocks,
920f4880 73 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 74 .init = exynos_init,
75 .name = name_exynos4210,
76 }, {
77 .idcode = EXYNOS4212_CPU_ID,
78 .idmask = EXYNOS4_CPU_MASK,
79 .map_io = exynos4_map_io,
80 .init_clocks = exynos4_init_clocks,
920f4880 81 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 82 .init = exynos_init,
83 .name = name_exynos4212,
84 }, {
85 .idcode = EXYNOS4412_CPU_ID,
86 .idmask = EXYNOS4_CPU_MASK,
87 .map_io = exynos4_map_io,
88 .init_clocks = exynos4_init_clocks,
920f4880 89 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 90 .init = exynos_init,
91 .name = name_exynos4412,
94c7ca71
KK		 92 }, {
93 .idcode = EXYNOS5250_SOC_ID,
94 .idmask = EXYNOS5_SOC_MASK,
95 .map_io = exynos5_map_io,
96 .init_clocks = exynos5_init_clocks,
97 .init_uarts = exynos_init_uarts,
98 .init = exynos_init,
99 .name = name_exynos5250,
cc511b8d
KK		 100 },
101};
102
103/* Initial IO mappings */
104
105static struct map_desc exynos_iodesc[] __initdata = {
106 {
107 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 108 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 109 .length = SZ_4K,
110 .type = MT_DEVICE,
94c7ca71
KK		 111 },
112};
113
114static struct map_desc exynos4_iodesc[] __initdata = {
115 {
cc511b8d
KK		 116 .virtual = (unsigned long)S3C_VA_SYS,
117 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
118 .length = SZ_64K,
119 .type = MT_DEVICE,
120 }, {
121 .virtual = (unsigned long)S3C_VA_TIMER,
122 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
123 .length = SZ_16K,
124 .type = MT_DEVICE,
125 }, {
126 .virtual = (unsigned long)S3C_VA_WATCHDOG,
127 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
128 .length = SZ_4K,
129 .type = MT_DEVICE,
130 }, {
131 .virtual = (unsigned long)S5P_VA_SROMC,
132 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
133 .length = SZ_4K,
134 .type = MT_DEVICE,
135 }, {
136 .virtual = (unsigned long)S5P_VA_SYSTIMER,
137 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
138 .length = SZ_4K,
139 .type = MT_DEVICE,
140 }, {
141 .virtual = (unsigned long)S5P_VA_PMU,
142 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
143 .length = SZ_64K,
144 .type = MT_DEVICE,
145 }, {
146 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
147 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
148 .length = SZ_4K,
149 .type = MT_DEVICE,
150 }, {
151 .virtual = (unsigned long)S5P_VA_GIC_CPU,
152 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
153 .length = SZ_64K,
154 .type = MT_DEVICE,
155 }, {
156 .virtual = (unsigned long)S5P_VA_GIC_DIST,
157 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
158 .length = SZ_64K,
159 .type = MT_DEVICE,
160 }, {
161 .virtual = (unsigned long)S3C_VA_UART,
162 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
163 .length = SZ_512K,
164 .type = MT_DEVICE,
94c7ca71 165 }, {
cc511b8d
KK		 166 .virtual = (unsigned long)S5P_VA_CMU,
167 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
168 .length = SZ_128K,
169 .type = MT_DEVICE,
170 }, {
171 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
172 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
173 .length = SZ_8K,
174 .type = MT_DEVICE,
175 }, {
176 .virtual = (unsigned long)S5P_VA_L2CC,
177 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
178 .length = SZ_4K,
179 .type = MT_DEVICE,
cc511b8d
KK		 180 }, {
181 .virtual = (unsigned long)S5P_VA_DMC0,
182 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 183 .length = SZ_64K,
184 .type = MT_DEVICE,
185 }, {
186 .virtual = (unsigned long)S5P_VA_DMC1,
187 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
188 .length = SZ_64K,
cc511b8d 189 .type = MT_DEVICE,
cc511b8d
KK		 190 }, {
191 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
192 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
193 .length = SZ_4K,
194 .type = MT_DEVICE,
195 },
196};
197
198static struct map_desc exynos4_iodesc0[] __initdata = {
199 {
200 .virtual = (unsigned long)S5P_VA_SYSRAM,
201 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
202 .length = SZ_4K,
203 .type = MT_DEVICE,
204 },
205};
206
207static struct map_desc exynos4_iodesc1[] __initdata = {
208 {
209 .virtual = (unsigned long)S5P_VA_SYSRAM,
210 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
211 .length = SZ_4K,
212 .type = MT_DEVICE,
213 },
214};
215
94c7ca71
KK		 216static struct map_desc exynos5_iodesc[] __initdata = {
217 {
218 .virtual = (unsigned long)S3C_VA_SYS,
219 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
220 .length = SZ_64K,
221 .type = MT_DEVICE,
222 }, {
223 .virtual = (unsigned long)S3C_VA_TIMER,
224 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
225 .length = SZ_16K,
226 .type = MT_DEVICE,
227 }, {
228 .virtual = (unsigned long)S3C_VA_WATCHDOG,
229 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
230 .length = SZ_4K,
231 .type = MT_DEVICE,
232 }, {
233 .virtual = (unsigned long)S5P_VA_SROMC,
234 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
235 .length = SZ_4K,
236 .type = MT_DEVICE,
237 }, {
238 .virtual = (unsigned long)S5P_VA_SYSTIMER,
239 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
240 .length = SZ_4K,
241 .type = MT_DEVICE,
242 }, {
243 .virtual = (unsigned long)S5P_VA_SYSRAM,
244 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
245 .length = SZ_4K,
246 .type = MT_DEVICE,
247 }, {
248 .virtual = (unsigned long)S5P_VA_CMU,
249 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
250 .length = 144 * SZ_1K,
251 .type = MT_DEVICE,
252 }, {
253 .virtual = (unsigned long)S5P_VA_PMU,
254 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
255 .length = SZ_64K,
256 .type = MT_DEVICE,
257 }, {
258 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
259 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
260 .length = SZ_4K,
261 .type = MT_DEVICE,
262 }, {
263 .virtual = (unsigned long)S3C_VA_UART,
264 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
265 .length = SZ_512K,
266 .type = MT_DEVICE,
267 }, {
268 .virtual = (unsigned long)S5P_VA_GIC_CPU,
269 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
c9ce7dbd 270 .length = SZ_8K,
94c7ca71
KK		 271 .type = MT_DEVICE,
272 }, {
273 .virtual = (unsigned long)S5P_VA_GIC_DIST,
274 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
c9ce7dbd 275 .length = SZ_4K,
94c7ca71
KK		 276 .type = MT_DEVICE,
277 },
278};
279
9eb48595 280void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 281{
282 __raw_writel(0x1, S5P_SWRESET);
283}
284
94c7ca71
KK		 285void exynos5_restart(char mode, const char *cmd)
286{
287 __raw_writel(0x1, EXYNOS_SWRESET);
288}
289
cc511b8d
KK		 290/*
291 * exynos_map_io
292 *
293 * register the standard cpu IO areas
294 */
295
296void __init exynos_init_io(struct map_desc *mach_desc, int size)
297{
298 /* initialize the io descriptors we need for initialization */
299 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
300 if (mach_desc)
301 iotable_init(mach_desc, size);
302
303 /* detect cpu id and rev. */
304 s5p_init_cpu(S5P_VA_CHIPID);
305
306 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
307}
308
906c789c 309static void __init exynos4_map_io(void)
cc511b8d
KK		 310{
311 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
312
313 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
314 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
315 else
316 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
317
318 /* initialize device information early */
319 exynos4_default_sdhci0();
320 exynos4_default_sdhci1();
321 exynos4_default_sdhci2();
322 exynos4_default_sdhci3();
323
324 s3c_adc_setname("samsung-adc-v3");
325
326 s3c_fimc_setname(0, "exynos4-fimc");
327 s3c_fimc_setname(1, "exynos4-fimc");
328 s3c_fimc_setname(2, "exynos4-fimc");
329 s3c_fimc_setname(3, "exynos4-fimc");
330
8482c81c
TA		 331 s3c_sdhci_setname(0, "exynos4-sdhci");
332 s3c_sdhci_setname(1, "exynos4-sdhci");
333 s3c_sdhci_setname(2, "exynos4-sdhci");
334 s3c_sdhci_setname(3, "exynos4-sdhci");
335
cc511b8d
KK		 336 /* The I2C bus controllers are directly compatible with s3c2440 */
337 s3c_i2c0_setname("s3c2440-i2c");
338 s3c_i2c1_setname("s3c2440-i2c");
339 s3c_i2c2_setname("s3c2440-i2c");
340
341 s5p_fb_setname(0, "exynos4-fb");
342 s5p_hdmi_setname("exynos4-hdmi");
343}
344
94c7ca71
KK		 345static void __init exynos5_map_io(void)
346{
347 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
348
bb19a751
KK		 349 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
350 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
351 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
352 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
353
8482c81c
TA		 354 s3c_sdhci_setname(0, "exynos4-sdhci");
355 s3c_sdhci_setname(1, "exynos4-sdhci");
356 s3c_sdhci_setname(2, "exynos4-sdhci");
357 s3c_sdhci_setname(3, "exynos4-sdhci");
358
94c7ca71
KK		 359 /* The I2C bus controllers are directly compatible with s3c2440 */
360 s3c_i2c0_setname("s3c2440-i2c");
361 s3c_i2c1_setname("s3c2440-i2c");
362 s3c_i2c2_setname("s3c2440-i2c");
363}
364
906c789c 365static void __init exynos4_init_clocks(int xtal)
cc511b8d
KK		 366{
367 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
368
369 s3c24xx_register_baseclocks(xtal);
370 s5p_register_clocks(xtal);
371
372 if (soc_is_exynos4210())
373 exynos4210_register_clocks();
374 else if (soc_is_exynos4212() || soc_is_exynos4412())
375 exynos4212_register_clocks();
376
377 exynos4_register_clocks();
378 exynos4_setup_clocks();
379}
380
94c7ca71
KK		 381static void __init exynos5_init_clocks(int xtal)
382{
383 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
384
385 s3c24xx_register_baseclocks(xtal);
386 s5p_register_clocks(xtal);
387
388 exynos5_register_clocks();
389 exynos5_setup_clocks();
390}
391
cc511b8d
KK		 392#define COMBINER_ENABLE_SET 0x0
393#define COMBINER_ENABLE_CLEAR 0x4
394#define COMBINER_INT_STATUS 0xC
395
396static DEFINE_SPINLOCK(irq_controller_lock);
397
398struct combiner_chip_data {
399 unsigned int irq_offset;
400 unsigned int irq_mask;
401 void __iomem *base;
402};
403
1e60bc0b 404static struct irq_domain *combiner_irq_domain;
cc511b8d
KK		 405static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
406
407static inline void __iomem *combiner_base(struct irq_data *data)
408{
409 struct combiner_chip_data *combiner_data =
410 irq_data_get_irq_chip_data(data);
411
412 return combiner_data->base;
413}
414
415static void combiner_mask_irq(struct irq_data *data)
416{
1e60bc0b 417 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 418
419 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
420}
421
422static void combiner_unmask_irq(struct irq_data *data)
423{
1e60bc0b 424 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 425
426 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
427}
428
429static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
430{
431 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
432 struct irq_chip *chip = irq_get_chip(irq);
433 unsigned int cascade_irq, combiner_irq;
434 unsigned long status;
435
436 chained_irq_enter(chip, desc);
437
438 spin_lock(&irq_controller_lock);
439 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
440 spin_unlock(&irq_controller_lock);
441 status &= chip_data->irq_mask;
442
443 if (status == 0)
444 goto out;
445
446 combiner_irq = __ffs(status);
447
448 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
449 if (unlikely(cascade_irq >= NR_IRQS))
450 do_bad_IRQ(cascade_irq, desc);
451 else
452 generic_handle_irq(cascade_irq);
453
454 out:
455 chained_irq_exit(chip, desc);
456}
457
458static struct irq_chip combiner_chip = {
459 .name = "COMBINER",
460 .irq_mask = combiner_mask_irq,
461 .irq_unmask = combiner_unmask_irq,
462};
463
464static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
465{
bb19a751
KK		 466 unsigned int max_nr;
467
468 if (soc_is_exynos5250())
469 max_nr = EXYNOS5_MAX_COMBINER_NR;
470 else
471 max_nr = EXYNOS4_MAX_COMBINER_NR;
472
473 if (combiner_nr >= max_nr)
cc511b8d
KK		 474 BUG();
475 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
476 BUG();
477 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
478}
479
1e60bc0b
TA		 480static void __init combiner_init_one(unsigned int combiner_nr,
481 void __iomem *base)
cc511b8d 482{
cc511b8d 483 combiner_data[combiner_nr].base = base;
1e60bc0b
TA		 484 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
485 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
cc511b8d
KK		 486 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
487
488 /* Disable all interrupts */
cc511b8d
KK		 489 __raw_writel(combiner_data[combiner_nr].irq_mask,
490 base + COMBINER_ENABLE_CLEAR);
1e60bc0b 491}
cc511b8d 492
1e60bc0b
TA		 493static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
494 irq_hw_number_t hw)
495{
496 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
497 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
498 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
499
500 return 0;
501}
cc511b8d 502
1e60bc0b
TA		 503static struct irq_domain_ops combiner_irq_domain_ops = {
504 .map = combiner_irq_domain_map,
505};
506
507void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
508{
509 int i, irq_base;
510 unsigned int max_nr, nr_irq;
511
512 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
513 EXYNOS4_MAX_COMBINER_NR;
514 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
515
516 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
517 if (IS_ERR_VALUE(irq_base)) {
518 irq_base = COMBINER_IRQ(0, 0);
519 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
520 }
521
522 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
523 &combiner_irq_domain_ops, &combiner_data);
524 if (WARN_ON(!combiner_irq_domain)) {
525 pr_warning("%s: irq domain init failed\n", __func__);
526 return;
527 }
528
529 for (i = 0; i < max_nr; i++) {
530 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
531 combiner_cascade_irq(i, IRQ_SPI(i));
cc511b8d
KK		 532 }
533}
534
237c78be
AB		 535#ifdef CONFIG_OF
536static const struct of_device_id exynos4_dt_irq_match[] = {
537 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
538 {},
539};
540#endif
cc511b8d
KK		 541
542void __init exynos4_init_irq(void)
543{
40ba95fd 544 unsigned int gic_bank_offset;
cc511b8d
KK		 545
546 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
547
237c78be 548 if (!of_have_populated_dt())
75294957 549 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be
AB		 550#ifdef CONFIG_OF
551 else
552 of_irq_init(exynos4_dt_irq_match);
553#endif
cc511b8d 554
1e60bc0b 555 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 556
557 /*
558 * The parameters of s5p_init_irq() are for VIC init.
559 * Theses parameters should be NULL and 0 because EXYNOS4
560 * uses GIC instead of VIC.
561 */
562 s5p_init_irq(NULL, 0);
563}
564
94c7ca71
KK		 565void __init exynos5_init_irq(void)
566{
6fff5a11 567#ifdef CONFIG_OF
5699b0ca 568 of_irq_init(exynos4_dt_irq_match);
6fff5a11 569#endif
1e60bc0b 570 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 571
572 /*
573 * The parameters of s5p_init_irq() are for VIC init.
574 * Theses parameters should be NULL and 0 because EXYNOS4
575 * uses GIC instead of VIC.
576 */
577 s5p_init_irq(NULL, 0);
578}
579
9ee6af9c
TA		 580struct bus_type exynos_subsys = {
581 .name = "exynos-core",
582 .dev_name = "exynos-core",
94c7ca71
KK		 583};
584
7affca35 585static struct device exynos4_dev = {
9ee6af9c 586 .bus = &exynos_subsys,
94c7ca71
KK		 587};
588
589static int __init exynos_core_init(void)
cc511b8d 590{
9ee6af9c 591 return subsys_system_register(&exynos_subsys, NULL);
cc511b8d 592}
94c7ca71 593core_initcall(exynos_core_init);
cc511b8d
KK		 594
595#ifdef CONFIG_CACHE_L2X0
596static int __init exynos4_l2x0_cache_init(void)
597{
e1b1994e
IH		 598 int ret;
599
94c7ca71
KK		 600 if (soc_is_exynos5250())
601 return 0;
602
6cdeddcc
ADK		 603 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
604 if (!ret) {
605 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
606 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
607 return 0;
608 }
cc511b8d 609
b756a50f
ADK		 610 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
611 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
612 /* TAG, Data Latency Control: 2 cycles */
613 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 614
b756a50f
ADK		 615 if (soc_is_exynos4212() || soc_is_exynos4412())
616 l2x0_saved_regs.data_latency = 0x120;
617 else
618 l2x0_saved_regs.data_latency = 0x110;
619
620 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
621 l2x0_saved_regs.pwr_ctrl =
622 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 623
b756a50f 624 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 625
b756a50f
ADK		 626 __raw_writel(l2x0_saved_regs.tag_latency,
627 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
628 __raw_writel(l2x0_saved_regs.data_latency,
629 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 630
b756a50f
ADK		 631 /* L2X0 Prefetch Control */
632 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
633 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
634
635 /* L2X0 Power Control */
636 __raw_writel(l2x0_saved_regs.pwr_ctrl,
637 S5P_VA_L2CC + L2X0_POWER_CTRL);
638
639 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
640 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
641 }
cc511b8d 642
6cdeddcc 643 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 644 return 0;
645}
cc511b8d
KK		 646early_initcall(exynos4_l2x0_cache_init);
647#endif
648
94c7ca71
KK		 649static int __init exynos5_l2_cache_init(void)
650{
651 unsigned int val;
652
653 if (!soc_is_exynos5250())
654 return 0;
655
656 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
657 "bic %0, %0, #(1 << 2)\n" /* cache disable */
658 "mcr p15, 0, %0, c1, c0, 0\n"
659 "mrc p15, 1, %0, c9, c0, 2\n"
660 : "=r"(val));
661
662 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
663
664 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
665 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
666 "orr %0, %0, #(1 << 2)\n" /* cache enable */
667 "mcr p15, 0, %0, c1, c0, 0\n"
668 : : "r"(val));
669
670 return 0;
671}
672early_initcall(exynos5_l2_cache_init);
673
906c789c 674static int __init exynos_init(void)
cc511b8d
KK		 675{
676 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71 677
9ee6af9c 678 return device_register(&exynos4_dev);
cc511b8d
KK		 679}
680
cc511b8d
KK		 681/* uart registration process */
682
920f4880 683static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 684{
685 struct s3c2410_uartcfg *tcfg = cfg;
686 u32 ucnt;
687
237c78be
AB		 688 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
689 tcfg->has_fracval = 1;
cc511b8d 690
171c067c
KK		 691 if (soc_is_exynos5250())
692 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
693 else
694 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 695}
696
330c90a5
EK		 697static void __iomem *exynos_eint_base;
698
cc511b8d
KK		 699static DEFINE_SPINLOCK(eint_lock);
700
701static unsigned int eint0_15_data[16];
702
330c90a5 703static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 704{
330c90a5
EK		 705 if (irq < IRQ_EINT(0))
706 return -EINVAL;
cc511b8d 707
330c90a5
EK		 708 irq -= IRQ_EINT(0);
709 if (irq < 8)
710 return EXYNOS4_GPX0(irq);
711
712 irq -= 8;
713 if (irq < 8)
714 return EXYNOS4_GPX1(irq);
715
716 irq -= 8;
717 if (irq < 8)
718 return EXYNOS4_GPX2(irq);
719
720 irq -= 8;
721 if (irq < 8)
722 return EXYNOS4_GPX3(irq);
723
724 return -EINVAL;
725}
726
727static inline int exynos5_irq_to_gpio(unsigned int irq)
728{
729 if (irq < IRQ_EINT(0))
730 return -EINVAL;
731
732 irq -= IRQ_EINT(0);
733 if (irq < 8)
734 return EXYNOS5_GPX0(irq);
735
736 irq -= 8;
737 if (irq < 8)
738 return EXYNOS5_GPX1(irq);
739
740 irq -= 8;
741 if (irq < 8)
742 return EXYNOS5_GPX2(irq);
cc511b8d 743
330c90a5
EK		 744 irq -= 8;
745 if (irq < 8)
746 return EXYNOS5_GPX3(irq);
747
748 return -EINVAL;
cc511b8d
KK		 749}
750
bb19a751
KK		 751static unsigned int exynos4_eint0_15_src_int[16] = {
752 EXYNOS4_IRQ_EINT0,
753 EXYNOS4_IRQ_EINT1,
754 EXYNOS4_IRQ_EINT2,
755 EXYNOS4_IRQ_EINT3,
756 EXYNOS4_IRQ_EINT4,
757 EXYNOS4_IRQ_EINT5,
758 EXYNOS4_IRQ_EINT6,
759 EXYNOS4_IRQ_EINT7,
760 EXYNOS4_IRQ_EINT8,
761 EXYNOS4_IRQ_EINT9,
762 EXYNOS4_IRQ_EINT10,
763 EXYNOS4_IRQ_EINT11,
764 EXYNOS4_IRQ_EINT12,
765 EXYNOS4_IRQ_EINT13,
766 EXYNOS4_IRQ_EINT14,
767 EXYNOS4_IRQ_EINT15,
768};
cc511b8d 769
bb19a751
KK		 770static unsigned int exynos5_eint0_15_src_int[16] = {
771 EXYNOS5_IRQ_EINT0,
772 EXYNOS5_IRQ_EINT1,
773 EXYNOS5_IRQ_EINT2,
774 EXYNOS5_IRQ_EINT3,
775 EXYNOS5_IRQ_EINT4,
776 EXYNOS5_IRQ_EINT5,
777 EXYNOS5_IRQ_EINT6,
778 EXYNOS5_IRQ_EINT7,
779 EXYNOS5_IRQ_EINT8,
780 EXYNOS5_IRQ_EINT9,
781 EXYNOS5_IRQ_EINT10,
782 EXYNOS5_IRQ_EINT11,
783 EXYNOS5_IRQ_EINT12,
784 EXYNOS5_IRQ_EINT13,
785 EXYNOS5_IRQ_EINT14,
786 EXYNOS5_IRQ_EINT15,
787};
330c90a5 788static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 789{
790 u32 mask;
791
792 spin_lock(&eint_lock);
330c90a5
EK		 793 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
794 mask |= EINT_OFFSET_BIT(data->irq);
795 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 796 spin_unlock(&eint_lock);
797}
798
330c90a5 799static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 800{
801 u32 mask;
802
803 spin_lock(&eint_lock);
330c90a5
EK		 804 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
805 mask &= ~(EINT_OFFSET_BIT(data->irq));
806 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 807 spin_unlock(&eint_lock);
808}
809
330c90a5 810static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 811{
330c90a5
EK		 812 __raw_writel(EINT_OFFSET_BIT(data->irq),
813 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 814}
815
330c90a5 816static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 817{
330c90a5
EK		 818 exynos_irq_eint_mask(data);
819 exynos_irq_eint_ack(data);
cc511b8d
KK		 820}
821
330c90a5 822static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 823{
824 int offs = EINT_OFFSET(data->irq);
825 int shift;
826 u32 ctrl, mask;
827 u32 newvalue = 0;
828
829 switch (type) {
830 case IRQ_TYPE_EDGE_RISING:
831 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
832 break;
833
834 case IRQ_TYPE_EDGE_FALLING:
835 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
836 break;
837
838 case IRQ_TYPE_EDGE_BOTH:
839 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
840 break;
841
842 case IRQ_TYPE_LEVEL_LOW:
843 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
844 break;
845
846 case IRQ_TYPE_LEVEL_HIGH:
847 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
848 break;
849
850 default:
851 printk(KERN_ERR "No such irq type %d", type);
852 return -EINVAL;
853 }
854
855 shift = (offs & 0x7) * 4;
856 mask = 0x7 << shift;
857
858 spin_lock(&eint_lock);
330c90a5 859 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 860 ctrl &= ~mask;
861 ctrl |= newvalue << shift;
330c90a5 862 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 863 spin_unlock(&eint_lock);
864
330c90a5
EK		 865 if (soc_is_exynos5250())
866 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
867 else
868 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 869
870 return 0;
871}
872
330c90a5
EK		 873static struct irq_chip exynos_irq_eint = {
874 .name = "exynos-eint",
875 .irq_mask = exynos_irq_eint_mask,
876 .irq_unmask = exynos_irq_eint_unmask,
877 .irq_mask_ack = exynos_irq_eint_maskack,
878 .irq_ack = exynos_irq_eint_ack,
879 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 880#ifdef CONFIG_PM
881 .irq_set_wake = s3c_irqext_wake,
882#endif
883};
884
885/*
886 * exynos4_irq_demux_eint
887 *
888 * This function demuxes the IRQ from from EINTs 16 to 31.
889 * It is designed to be inlined into the specific handler
890 * s5p_irq_demux_eintX_Y.
891 *
892 * Each EINT pend/mask registers handle eight of them.
893 */
330c90a5 894static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 895{
896 unsigned int irq;
897
330c90a5
EK		 898 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
899 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 900
901 status &= ~mask;
902 status &= 0xff;
903
904 while (status) {
905 irq = fls(status) - 1;
906 generic_handle_irq(irq + start);
907 status &= ~(1 << irq);
908 }
909}
910
330c90a5 911static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 912{
913 struct irq_chip *chip = irq_get_chip(irq);
914 chained_irq_enter(chip, desc);
330c90a5
EK		 915 exynos_irq_demux_eint(IRQ_EINT(16));
916 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 917 chained_irq_exit(chip, desc);
918}
919
bb19a751 920static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 921{
922 u32 *irq_data = irq_get_handler_data(irq);
923 struct irq_chip *chip = irq_get_chip(irq);
924
925 chained_irq_enter(chip, desc);
926 chip->irq_mask(&desc->irq_data);
927
928 if (chip->irq_ack)
929 chip->irq_ack(&desc->irq_data);
930
931 generic_handle_irq(*irq_data);
932
933 chip->irq_unmask(&desc->irq_data);
934 chained_irq_exit(chip, desc);
935}
936
330c90a5 937static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 938{
939 int irq;
940
94c7ca71 941 if (soc_is_exynos5250())
330c90a5
EK		 942 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
943 else
944 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
945
946 if (exynos_eint_base == NULL) {
947 pr_err("unable to ioremap for EINT base address\n");
948 return -ENOMEM;
949 }
94c7ca71 950
cc511b8d 951 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 952 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 953 handle_level_irq);
954 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
955 }
956
330c90a5 957 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 958
959 for (irq = 0 ; irq <= 15 ; irq++) {
960 eint0_15_data[irq] = IRQ_EINT(irq);
961
bb19a751
KK		 962 if (soc_is_exynos5250()) {
963 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
964 &eint0_15_data[irq]);
965 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
966 exynos_irq_eint0_15);
967 } else {
968 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
969 &eint0_15_data[irq]);
970 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
971 exynos_irq_eint0_15);
972 }
cc511b8d
KK		 973 }
974
975 return 0;
976}
330c90a5 977arch_initcall(exynos_init_irq_eint);
Linux kernel - Deliverables
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