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ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
[deliverable/linux.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
7affca35 16#include <linux/device.h>
cc511b8d
KK		 17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
237c78be 20#include <linux/of.h>
5b7897db 21#include <linux/of_fdt.h>
237c78be 22#include <linux/of_irq.h>
1e60bc0b
TA		 23#include <linux/export.h>
24#include <linux/irqdomain.h>
e873a47c 25#include <linux/of_address.h>
cc511b8d
KK		 26
27#include <asm/proc-fns.h>
40ba95fd 28#include <asm/exception.h>
cc511b8d
KK		 29#include <asm/hardware/cache-l2x0.h>
30#include <asm/hardware/gic.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
b756a50f 33#include <asm/cacheflush.h>
cc511b8d
KK		 34
35#include <mach/regs-irq.h>
36#include <mach/regs-pmu.h>
37#include <mach/regs-gpio.h>
b756a50f 38#include <mach/pmu.h>
cc511b8d
KK		 39
40#include <plat/cpu.h>
41#include <plat/clock.h>
42#include <plat/devs.h>
43#include <plat/pm.h>
cc511b8d
KK		 44#include <plat/sdhci.h>
45#include <plat/gpio-cfg.h>
46#include <plat/adc-core.h>
47#include <plat/fb-core.h>
48#include <plat/fimc-core.h>
49#include <plat/iic-core.h>
50#include <plat/tv-core.h>
308b3afb 51#include <plat/spi-core.h>
cc511b8d
KK		 52#include <plat/regs-serial.h>
53
54#include "common.h"
6cdeddcc
ADK		 55#define L2_AUX_VAL 0x7C470001
56#define L2_AUX_MASK 0xC200ffff
cc511b8d 57
cc511b8d
KK		 58static const char name_exynos4210[] = "EXYNOS4210";
59static const char name_exynos4212[] = "EXYNOS4212";
60static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 61static const char name_exynos5250[] = "EXYNOS5250";
2edb36c4 62static const char name_exynos5440[] = "EXYNOS5440";
cc511b8d 63
906c789c 64static void exynos4_map_io(void);
94c7ca71 65static void exynos5_map_io(void);
2edb36c4 66static void exynos5440_map_io(void);
906c789c 67static void exynos4_init_clocks(int xtal);
94c7ca71 68static void exynos5_init_clocks(int xtal);
920f4880 69static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 70static int exynos_init(void);
cc511b8d
KK		 71
72static struct cpu_table cpu_ids[] __initdata = {
73 {
74 .idcode = EXYNOS4210_CPU_ID,
75 .idmask = EXYNOS4_CPU_MASK,
76 .map_io = exynos4_map_io,
77 .init_clocks = exynos4_init_clocks,
920f4880 78 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 79 .init = exynos_init,
80 .name = name_exynos4210,
81 }, {
82 .idcode = EXYNOS4212_CPU_ID,
83 .idmask = EXYNOS4_CPU_MASK,
84 .map_io = exynos4_map_io,
85 .init_clocks = exynos4_init_clocks,
920f4880 86 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 87 .init = exynos_init,
88 .name = name_exynos4212,
89 }, {
90 .idcode = EXYNOS4412_CPU_ID,
91 .idmask = EXYNOS4_CPU_MASK,
92 .map_io = exynos4_map_io,
93 .init_clocks = exynos4_init_clocks,
920f4880 94 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 95 .init = exynos_init,
96 .name = name_exynos4412,
94c7ca71
KK		 97 }, {
98 .idcode = EXYNOS5250_SOC_ID,
99 .idmask = EXYNOS5_SOC_MASK,
100 .map_io = exynos5_map_io,
101 .init_clocks = exynos5_init_clocks,
102 .init_uarts = exynos_init_uarts,
103 .init = exynos_init,
104 .name = name_exynos5250,
2edb36c4
KK		 105 }, {
106 .idcode = EXYNOS5440_SOC_ID,
107 .idmask = EXYNOS5_SOC_MASK,
108 .map_io = exynos5440_map_io,
109 .init = exynos_init,
110 .name = name_exynos5440,
cc511b8d
KK		 111 },
112};
113
114/* Initial IO mappings */
115
116static struct map_desc exynos_iodesc[] __initdata = {
117 {
118 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 119 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 120 .length = SZ_4K,
121 .type = MT_DEVICE,
94c7ca71
KK		 122 },
123};
124
5b7897db 125#ifdef CONFIG_ARCH_EXYNOS5
2edb36c4
KK		 126static struct map_desc exynos5440_iodesc[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_CHIPID,
129 .pfn = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
5b7897db 134#endif
2edb36c4 135
94c7ca71
KK		 136static struct map_desc exynos4_iodesc[] __initdata = {
137 {
cc511b8d
KK		 138 .virtual = (unsigned long)S3C_VA_SYS,
139 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
140 .length = SZ_64K,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S3C_VA_TIMER,
144 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
145 .length = SZ_16K,
146 .type = MT_DEVICE,
147 }, {
148 .virtual = (unsigned long)S3C_VA_WATCHDOG,
149 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
150 .length = SZ_4K,
151 .type = MT_DEVICE,
152 }, {
153 .virtual = (unsigned long)S5P_VA_SROMC,
154 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
155 .length = SZ_4K,
156 .type = MT_DEVICE,
157 }, {
158 .virtual = (unsigned long)S5P_VA_SYSTIMER,
159 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
160 .length = SZ_4K,
161 .type = MT_DEVICE,
162 }, {
163 .virtual = (unsigned long)S5P_VA_PMU,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
165 .length = SZ_64K,
166 .type = MT_DEVICE,
167 }, {
168 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
170 .length = SZ_4K,
171 .type = MT_DEVICE,
172 }, {
173 .virtual = (unsigned long)S5P_VA_GIC_CPU,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
175 .length = SZ_64K,
176 .type = MT_DEVICE,
177 }, {
178 .virtual = (unsigned long)S5P_VA_GIC_DIST,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
180 .length = SZ_64K,
181 .type = MT_DEVICE,
182 }, {
183 .virtual = (unsigned long)S3C_VA_UART,
184 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
185 .length = SZ_512K,
186 .type = MT_DEVICE,
94c7ca71 187 }, {
cc511b8d
KK		 188 .virtual = (unsigned long)S5P_VA_CMU,
189 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
190 .length = SZ_128K,
191 .type = MT_DEVICE,
192 }, {
193 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
194 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
195 .length = SZ_8K,
196 .type = MT_DEVICE,
197 }, {
198 .virtual = (unsigned long)S5P_VA_L2CC,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
200 .length = SZ_4K,
201 .type = MT_DEVICE,
cc511b8d
KK		 202 }, {
203 .virtual = (unsigned long)S5P_VA_DMC0,
204 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 205 .length = SZ_64K,
206 .type = MT_DEVICE,
207 }, {
208 .virtual = (unsigned long)S5P_VA_DMC1,
209 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
210 .length = SZ_64K,
cc511b8d 211 .type = MT_DEVICE,
cc511b8d
KK		 212 }, {
213 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
214 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
215 .length = SZ_4K,
216 .type = MT_DEVICE,
217 },
218};
219
220static struct map_desc exynos4_iodesc0[] __initdata = {
221 {
222 .virtual = (unsigned long)S5P_VA_SYSRAM,
223 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
224 .length = SZ_4K,
225 .type = MT_DEVICE,
226 },
227};
228
229static struct map_desc exynos4_iodesc1[] __initdata = {
230 {
231 .virtual = (unsigned long)S5P_VA_SYSRAM,
232 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
233 .length = SZ_4K,
234 .type = MT_DEVICE,
235 },
236};
237
94c7ca71
KK		 238static struct map_desc exynos5_iodesc[] __initdata = {
239 {
240 .virtual = (unsigned long)S3C_VA_SYS,
241 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
242 .length = SZ_64K,
243 .type = MT_DEVICE,
244 }, {
245 .virtual = (unsigned long)S3C_VA_TIMER,
246 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
247 .length = SZ_16K,
248 .type = MT_DEVICE,
249 }, {
250 .virtual = (unsigned long)S3C_VA_WATCHDOG,
251 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
252 .length = SZ_4K,
253 .type = MT_DEVICE,
254 }, {
255 .virtual = (unsigned long)S5P_VA_SROMC,
256 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
257 .length = SZ_4K,
258 .type = MT_DEVICE,
259 }, {
260 .virtual = (unsigned long)S5P_VA_SYSTIMER,
261 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
262 .length = SZ_4K,
263 .type = MT_DEVICE,
264 }, {
265 .virtual = (unsigned long)S5P_VA_SYSRAM,
266 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
267 .length = SZ_4K,
268 .type = MT_DEVICE,
269 }, {
270 .virtual = (unsigned long)S5P_VA_CMU,
271 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
272 .length = 144 * SZ_1K,
273 .type = MT_DEVICE,
274 }, {
275 .virtual = (unsigned long)S5P_VA_PMU,
276 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
277 .length = SZ_64K,
278 .type = MT_DEVICE,
279 }, {
280 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
281 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
282 .length = SZ_4K,
283 .type = MT_DEVICE,
284 }, {
285 .virtual = (unsigned long)S3C_VA_UART,
286 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
287 .length = SZ_512K,
288 .type = MT_DEVICE,
289 }, {
290 .virtual = (unsigned long)S5P_VA_GIC_CPU,
291 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
c9ce7dbd 292 .length = SZ_8K,
94c7ca71
KK		 293 .type = MT_DEVICE,
294 }, {
295 .virtual = (unsigned long)S5P_VA_GIC_DIST,
296 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
c9ce7dbd 297 .length = SZ_4K,
94c7ca71
KK		 298 .type = MT_DEVICE,
299 },
300};
301
2edb36c4
KK		 302static struct map_desc exynos5440_iodesc0[] __initdata = {
303 {
304 .virtual = (unsigned long)S3C_VA_UART,
305 .pfn = __phys_to_pfn(EXYNOS5440_PA_UART0),
306 .length = SZ_512K,
307 .type = MT_DEVICE,
308 },
309};
310
9eb48595 311void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 312{
313 __raw_writel(0x1, S5P_SWRESET);
314}
315
94c7ca71
KK		 316void exynos5_restart(char mode, const char *cmd)
317{
2edb36c4
KK		 318 u32 val;
319 void __iomem *addr;
320
321 if (of_machine_is_compatible("samsung,exynos5250")) {
322 val = 0x1;
323 addr = EXYNOS_SWRESET;
324 } else if (of_machine_is_compatible("samsung,exynos5440")) {
325 val = (0x10 << 20) | (0x1 << 16);
326 addr = EXYNOS5440_SWRESET;
327 } else {
328 pr_err("%s: cannot support non-DT\n", __func__);
329 return;
330 }
331
332 __raw_writel(val, addr);
94c7ca71
KK		 333}
334
bb13fabc
SG		 335void __init exynos_init_late(void)
336{
2edb36c4
KK		 337 if (of_machine_is_compatible("samsung,exynos5440"))
338 /* to be supported later */
339 return;
340
bb13fabc
SG		 341 exynos_pm_late_initcall();
342}
343
cc511b8d
KK		 344/*
345 * exynos_map_io
346 *
347 * register the standard cpu IO areas
348 */
349
350void __init exynos_init_io(struct map_desc *mach_desc, int size)
351{
5b7897db
DA		 352 struct map_desc *iodesc = exynos_iodesc;
353 int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
354#if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
355 unsigned long root = of_get_flat_dt_root();
356
cc511b8d 357 /* initialize the io descriptors we need for initialization */
5b7897db
DA		 358 if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
359 iodesc = exynos5440_iodesc;
360 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
361 }
362#endif
363
364 iotable_init(iodesc, iodesc_sz);
2edb36c4 365
cc511b8d
KK		 366 if (mach_desc)
367 iotable_init(mach_desc, size);
368
369 /* detect cpu id and rev. */
370 s5p_init_cpu(S5P_VA_CHIPID);
371
372 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
373}
374
906c789c 375static void __init exynos4_map_io(void)
cc511b8d
KK		 376{
377 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
378
379 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
380 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
381 else
382 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
383
384 /* initialize device information early */
385 exynos4_default_sdhci0();
386 exynos4_default_sdhci1();
387 exynos4_default_sdhci2();
388 exynos4_default_sdhci3();
389
390 s3c_adc_setname("samsung-adc-v3");
391
392 s3c_fimc_setname(0, "exynos4-fimc");
393 s3c_fimc_setname(1, "exynos4-fimc");
394 s3c_fimc_setname(2, "exynos4-fimc");
395 s3c_fimc_setname(3, "exynos4-fimc");
396
8482c81c
TA		 397 s3c_sdhci_setname(0, "exynos4-sdhci");
398 s3c_sdhci_setname(1, "exynos4-sdhci");
399 s3c_sdhci_setname(2, "exynos4-sdhci");
400 s3c_sdhci_setname(3, "exynos4-sdhci");
401
cc511b8d
KK		 402 /* The I2C bus controllers are directly compatible with s3c2440 */
403 s3c_i2c0_setname("s3c2440-i2c");
404 s3c_i2c1_setname("s3c2440-i2c");
405 s3c_i2c2_setname("s3c2440-i2c");
406
407 s5p_fb_setname(0, "exynos4-fb");
408 s5p_hdmi_setname("exynos4-hdmi");
308b3afb
HS		 409
410 s3c64xx_spi_setname("exynos4210-spi");
cc511b8d
KK		 411}
412
94c7ca71
KK		 413static void __init exynos5_map_io(void)
414{
415 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
416
bb19a751
KK		 417 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
418 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
419 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
420 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
421
8482c81c
TA		 422 s3c_sdhci_setname(0, "exynos4-sdhci");
423 s3c_sdhci_setname(1, "exynos4-sdhci");
424 s3c_sdhci_setname(2, "exynos4-sdhci");
425 s3c_sdhci_setname(3, "exynos4-sdhci");
426
94c7ca71
KK		 427 /* The I2C bus controllers are directly compatible with s3c2440 */
428 s3c_i2c0_setname("s3c2440-i2c");
429 s3c_i2c1_setname("s3c2440-i2c");
430 s3c_i2c2_setname("s3c2440-i2c");
308b3afb
HS		 431
432 s3c64xx_spi_setname("exynos4210-spi");
94c7ca71
KK		 433}
434
906c789c 435static void __init exynos4_init_clocks(int xtal)
cc511b8d
KK		 436{
437 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
438
439 s3c24xx_register_baseclocks(xtal);
440 s5p_register_clocks(xtal);
441
442 if (soc_is_exynos4210())
443 exynos4210_register_clocks();
444 else if (soc_is_exynos4212() || soc_is_exynos4412())
445 exynos4212_register_clocks();
446
447 exynos4_register_clocks();
448 exynos4_setup_clocks();
449}
450
2edb36c4
KK		 451static void __init exynos5440_map_io(void)
452{
453 iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
454}
455
94c7ca71
KK		 456static void __init exynos5_init_clocks(int xtal)
457{
458 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
459
460 s3c24xx_register_baseclocks(xtal);
461 s5p_register_clocks(xtal);
462
463 exynos5_register_clocks();
464 exynos5_setup_clocks();
465}
466
cc511b8d
KK		 467#define COMBINER_ENABLE_SET 0x0
468#define COMBINER_ENABLE_CLEAR 0x4
469#define COMBINER_INT_STATUS 0xC
470
471static DEFINE_SPINLOCK(irq_controller_lock);
472
473struct combiner_chip_data {
474 unsigned int irq_offset;
475 unsigned int irq_mask;
476 void __iomem *base;
477};
478
1e60bc0b 479static struct irq_domain *combiner_irq_domain;
cc511b8d
KK		 480static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
481
482static inline void __iomem *combiner_base(struct irq_data *data)
483{
484 struct combiner_chip_data *combiner_data =
485 irq_data_get_irq_chip_data(data);
486
487 return combiner_data->base;
488}
489
490static void combiner_mask_irq(struct irq_data *data)
491{
1e60bc0b 492 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 493
494 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
495}
496
497static void combiner_unmask_irq(struct irq_data *data)
498{
1e60bc0b 499 u32 mask = 1 << (data->hwirq % 32);
cc511b8d
KK		 500
501 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
502}
503
504static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
505{
506 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
507 struct irq_chip *chip = irq_get_chip(irq);
508 unsigned int cascade_irq, combiner_irq;
509 unsigned long status;
510
511 chained_irq_enter(chip, desc);
512
513 spin_lock(&irq_controller_lock);
514 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
515 spin_unlock(&irq_controller_lock);
516 status &= chip_data->irq_mask;
517
518 if (status == 0)
519 goto out;
520
521 combiner_irq = __ffs(status);
522
523 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
524 if (unlikely(cascade_irq >= NR_IRQS))
525 do_bad_IRQ(cascade_irq, desc);
526 else
527 generic_handle_irq(cascade_irq);
528
529 out:
530 chained_irq_exit(chip, desc);
531}
532
533static struct irq_chip combiner_chip = {
534 .name = "COMBINER",
535 .irq_mask = combiner_mask_irq,
536 .irq_unmask = combiner_unmask_irq,
537};
538
539static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
540{
bb19a751
KK		 541 unsigned int max_nr;
542
543 if (soc_is_exynos5250())
544 max_nr = EXYNOS5_MAX_COMBINER_NR;
545 else
546 max_nr = EXYNOS4_MAX_COMBINER_NR;
547
548 if (combiner_nr >= max_nr)
cc511b8d
KK		 549 BUG();
550 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
551 BUG();
552 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
553}
554
1e60bc0b
TA		 555static void __init combiner_init_one(unsigned int combiner_nr,
556 void __iomem *base)
cc511b8d 557{
cc511b8d 558 combiner_data[combiner_nr].base = base;
1e60bc0b
TA		 559 combiner_data[combiner_nr].irq_offset = irq_find_mapping(
560 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
cc511b8d
KK		 561 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
562
563 /* Disable all interrupts */
cc511b8d
KK		 564 __raw_writel(combiner_data[combiner_nr].irq_mask,
565 base + COMBINER_ENABLE_CLEAR);
1e60bc0b 566}
cc511b8d 567
e873a47c
TA		 568#ifdef CONFIG_OF
569static int combiner_irq_domain_xlate(struct irq_domain *d,
570 struct device_node *controller,
571 const u32 *intspec, unsigned int intsize,
572 unsigned long *out_hwirq,
573 unsigned int *out_type)
574{
575 if (d->of_node != controller)
576 return -EINVAL;
577
578 if (intsize < 2)
579 return -EINVAL;
580
581 *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
582 *out_type = 0;
583
584 return 0;
585}
586#else
587static int combiner_irq_domain_xlate(struct irq_domain *d,
588 struct device_node *controller,
589 const u32 *intspec, unsigned int intsize,
590 unsigned long *out_hwirq,
591 unsigned int *out_type)
592{
593 return -EINVAL;
594}
595#endif
596
1e60bc0b
TA		 597static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
598 irq_hw_number_t hw)
599{
600 irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
601 irq_set_chip_data(irq, &combiner_data[hw >> 3]);
602 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
603
604 return 0;
605}
cc511b8d 606
1e60bc0b 607static struct irq_domain_ops combiner_irq_domain_ops = {
e873a47c 608 .xlate = combiner_irq_domain_xlate,
1e60bc0b
TA		 609 .map = combiner_irq_domain_map,
610};
611
2a2b0e20
SK		 612static void __init combiner_init(void __iomem *combiner_base,
613 struct device_node *np)
1e60bc0b 614{
e873a47c 615 int i, irq, irq_base;
1e60bc0b
TA		 616 unsigned int max_nr, nr_irq;
617
e873a47c
TA		 618 if (np) {
619 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
620 pr_warning("%s: number of combiners not specified, "
621 "setting default as %d.\n",
622 __func__, EXYNOS4_MAX_COMBINER_NR);
623 max_nr = EXYNOS4_MAX_COMBINER_NR;
624 }
625 } else {
626 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
627 EXYNOS4_MAX_COMBINER_NR;
628 }
1e60bc0b
TA		 629 nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
630
631 irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
632 if (IS_ERR_VALUE(irq_base)) {
633 irq_base = COMBINER_IRQ(0, 0);
634 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
635 }
636
637 combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
638 &combiner_irq_domain_ops, &combiner_data);
639 if (WARN_ON(!combiner_irq_domain)) {
640 pr_warning("%s: irq domain init failed\n", __func__);
641 return;
642 }
643
644 for (i = 0; i < max_nr; i++) {
645 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
820f3dd7
AB		 646 irq = IRQ_SPI(i);
647#ifdef CONFIG_OF
648 if (np)
649 irq = irq_of_parse_and_map(np, i);
650#endif
e873a47c 651 combiner_cascade_irq(i, irq);
cc511b8d
KK		 652 }
653}
654
237c78be 655#ifdef CONFIG_OF
e873a47c
TA		 656int __init combiner_of_init(struct device_node *np, struct device_node *parent)
657{
658 void __iomem *combiner_base;
659
660 combiner_base = of_iomap(np, 0);
661 if (!combiner_base) {
662 pr_err("%s: failed to map combiner registers\n", __func__);
663 return -ENXIO;
664 }
665
666 combiner_init(combiner_base, np);
667
668 return 0;
669}
670
2edb36c4 671static const struct of_device_id exynos_dt_irq_match[] = {
237c78be 672 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
2edb36c4 673 { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
e873a47c
TA		 674 { .compatible = "samsung,exynos4210-combiner",
675 .data = combiner_of_init, },
237c78be
AB		 676 {},
677};
678#endif
cc511b8d
KK		 679
680void __init exynos4_init_irq(void)
681{
40ba95fd 682 unsigned int gic_bank_offset;
cc511b8d
KK		 683
684 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
685
237c78be 686 if (!of_have_populated_dt())
75294957 687 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be
AB		 688#ifdef CONFIG_OF
689 else
2edb36c4 690 of_irq_init(exynos_dt_irq_match);
237c78be 691#endif
cc511b8d 692
e873a47c
TA		 693 if (!of_have_populated_dt())
694 combiner_init(S5P_VA_COMBINER_BASE, NULL);
cc511b8d
KK		 695
696 /*
697 * The parameters of s5p_init_irq() are for VIC init.
698 * Theses parameters should be NULL and 0 because EXYNOS4
699 * uses GIC instead of VIC.
700 */
701 s5p_init_irq(NULL, 0);
702}
703
94c7ca71
KK		 704void __init exynos5_init_irq(void)
705{
6fff5a11 706#ifdef CONFIG_OF
2edb36c4 707 of_irq_init(exynos_dt_irq_match);
6fff5a11 708#endif
cc511b8d
KK		 709 /*
710 * The parameters of s5p_init_irq() are for VIC init.
711 * Theses parameters should be NULL and 0 because EXYNOS4
712 * uses GIC instead of VIC.
713 */
714 s5p_init_irq(NULL, 0);
715}
716
9ee6af9c
TA		 717struct bus_type exynos_subsys = {
718 .name = "exynos-core",
719 .dev_name = "exynos-core",
94c7ca71
KK		 720};
721
7affca35 722static struct device exynos4_dev = {
9ee6af9c 723 .bus = &exynos_subsys,
94c7ca71
KK		 724};
725
726static int __init exynos_core_init(void)
cc511b8d 727{
9ee6af9c 728 return subsys_system_register(&exynos_subsys, NULL);
cc511b8d 729}
94c7ca71 730core_initcall(exynos_core_init);
cc511b8d
KK		 731
732#ifdef CONFIG_CACHE_L2X0
733static int __init exynos4_l2x0_cache_init(void)
734{
e1b1994e
IH		 735 int ret;
736
2edb36c4 737 if (soc_is_exynos5250() || soc_is_exynos5440())
94c7ca71
KK		 738 return 0;
739
6cdeddcc
ADK		 740 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
741 if (!ret) {
742 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
743 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
744 return 0;
745 }
cc511b8d 746
b756a50f
ADK		 747 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
748 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
749 /* TAG, Data Latency Control: 2 cycles */
750 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 751
b756a50f
ADK		 752 if (soc_is_exynos4212() || soc_is_exynos4412())
753 l2x0_saved_regs.data_latency = 0x120;
754 else
755 l2x0_saved_regs.data_latency = 0x110;
756
757 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
758 l2x0_saved_regs.pwr_ctrl =
759 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 760
b756a50f 761 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 762
b756a50f
ADK		 763 __raw_writel(l2x0_saved_regs.tag_latency,
764 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
765 __raw_writel(l2x0_saved_regs.data_latency,
766 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 767
b756a50f
ADK		 768 /* L2X0 Prefetch Control */
769 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
770 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
771
772 /* L2X0 Power Control */
773 __raw_writel(l2x0_saved_regs.pwr_ctrl,
774 S5P_VA_L2CC + L2X0_POWER_CTRL);
775
776 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
777 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
778 }
cc511b8d 779
6cdeddcc 780 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 781 return 0;
782}
cc511b8d
KK		 783early_initcall(exynos4_l2x0_cache_init);
784#endif
785
906c789c 786static int __init exynos_init(void)
cc511b8d
KK		 787{
788 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71 789
9ee6af9c 790 return device_register(&exynos4_dev);
cc511b8d
KK		 791}
792
cc511b8d
KK		 793/* uart registration process */
794
920f4880 795static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 796{
797 struct s3c2410_uartcfg *tcfg = cfg;
798 u32 ucnt;
799
237c78be
AB		 800 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
801 tcfg->has_fracval = 1;
cc511b8d 802
171c067c
KK		 803 if (soc_is_exynos5250())
804 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
805 else
806 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 807}
808
330c90a5
EK		 809static void __iomem *exynos_eint_base;
810
cc511b8d
KK		 811static DEFINE_SPINLOCK(eint_lock);
812
813static unsigned int eint0_15_data[16];
814
330c90a5 815static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 816{
330c90a5
EK		 817 if (irq < IRQ_EINT(0))
818 return -EINVAL;
cc511b8d 819
330c90a5
EK		 820 irq -= IRQ_EINT(0);
821 if (irq < 8)
822 return EXYNOS4_GPX0(irq);
823
824 irq -= 8;
825 if (irq < 8)
826 return EXYNOS4_GPX1(irq);
827
828 irq -= 8;
829 if (irq < 8)
830 return EXYNOS4_GPX2(irq);
831
832 irq -= 8;
833 if (irq < 8)
834 return EXYNOS4_GPX3(irq);
835
836 return -EINVAL;
837}
838
839static inline int exynos5_irq_to_gpio(unsigned int irq)
840{
841 if (irq < IRQ_EINT(0))
842 return -EINVAL;
843
844 irq -= IRQ_EINT(0);
845 if (irq < 8)
846 return EXYNOS5_GPX0(irq);
847
848 irq -= 8;
849 if (irq < 8)
850 return EXYNOS5_GPX1(irq);
851
852 irq -= 8;
853 if (irq < 8)
854 return EXYNOS5_GPX2(irq);
cc511b8d 855
330c90a5
EK		 856 irq -= 8;
857 if (irq < 8)
858 return EXYNOS5_GPX3(irq);
859
860 return -EINVAL;
cc511b8d
KK		 861}
862
bb19a751
KK		 863static unsigned int exynos4_eint0_15_src_int[16] = {
864 EXYNOS4_IRQ_EINT0,
865 EXYNOS4_IRQ_EINT1,
866 EXYNOS4_IRQ_EINT2,
867 EXYNOS4_IRQ_EINT3,
868 EXYNOS4_IRQ_EINT4,
869 EXYNOS4_IRQ_EINT5,
870 EXYNOS4_IRQ_EINT6,
871 EXYNOS4_IRQ_EINT7,
872 EXYNOS4_IRQ_EINT8,
873 EXYNOS4_IRQ_EINT9,
874 EXYNOS4_IRQ_EINT10,
875 EXYNOS4_IRQ_EINT11,
876 EXYNOS4_IRQ_EINT12,
877 EXYNOS4_IRQ_EINT13,
878 EXYNOS4_IRQ_EINT14,
879 EXYNOS4_IRQ_EINT15,
880};
cc511b8d 881
bb19a751
KK		 882static unsigned int exynos5_eint0_15_src_int[16] = {
883 EXYNOS5_IRQ_EINT0,
884 EXYNOS5_IRQ_EINT1,
885 EXYNOS5_IRQ_EINT2,
886 EXYNOS5_IRQ_EINT3,
887 EXYNOS5_IRQ_EINT4,
888 EXYNOS5_IRQ_EINT5,
889 EXYNOS5_IRQ_EINT6,
890 EXYNOS5_IRQ_EINT7,
891 EXYNOS5_IRQ_EINT8,
892 EXYNOS5_IRQ_EINT9,
893 EXYNOS5_IRQ_EINT10,
894 EXYNOS5_IRQ_EINT11,
895 EXYNOS5_IRQ_EINT12,
896 EXYNOS5_IRQ_EINT13,
897 EXYNOS5_IRQ_EINT14,
898 EXYNOS5_IRQ_EINT15,
899};
330c90a5 900static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 901{
902 u32 mask;
903
904 spin_lock(&eint_lock);
330c90a5
EK		 905 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
906 mask |= EINT_OFFSET_BIT(data->irq);
907 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 908 spin_unlock(&eint_lock);
909}
910
330c90a5 911static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 912{
913 u32 mask;
914
915 spin_lock(&eint_lock);
330c90a5
EK		 916 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
917 mask &= ~(EINT_OFFSET_BIT(data->irq));
918 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 919 spin_unlock(&eint_lock);
920}
921
330c90a5 922static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 923{
330c90a5
EK		 924 __raw_writel(EINT_OFFSET_BIT(data->irq),
925 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 926}
927
330c90a5 928static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 929{
330c90a5
EK		 930 exynos_irq_eint_mask(data);
931 exynos_irq_eint_ack(data);
cc511b8d
KK		 932}
933
330c90a5 934static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 935{
936 int offs = EINT_OFFSET(data->irq);
937 int shift;
938 u32 ctrl, mask;
939 u32 newvalue = 0;
940
941 switch (type) {
942 case IRQ_TYPE_EDGE_RISING:
943 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
944 break;
945
946 case IRQ_TYPE_EDGE_FALLING:
947 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
948 break;
949
950 case IRQ_TYPE_EDGE_BOTH:
951 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
952 break;
953
954 case IRQ_TYPE_LEVEL_LOW:
955 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
956 break;
957
958 case IRQ_TYPE_LEVEL_HIGH:
959 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
960 break;
961
962 default:
963 printk(KERN_ERR "No such irq type %d", type);
964 return -EINVAL;
965 }
966
967 shift = (offs & 0x7) * 4;
968 mask = 0x7 << shift;
969
970 spin_lock(&eint_lock);
330c90a5 971 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 972 ctrl &= ~mask;
973 ctrl |= newvalue << shift;
330c90a5 974 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 975 spin_unlock(&eint_lock);
976
330c90a5
EK		 977 if (soc_is_exynos5250())
978 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
979 else
980 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 981
982 return 0;
983}
984
330c90a5
EK		 985static struct irq_chip exynos_irq_eint = {
986 .name = "exynos-eint",
987 .irq_mask = exynos_irq_eint_mask,
988 .irq_unmask = exynos_irq_eint_unmask,
989 .irq_mask_ack = exynos_irq_eint_maskack,
990 .irq_ack = exynos_irq_eint_ack,
991 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 992#ifdef CONFIG_PM
993 .irq_set_wake = s3c_irqext_wake,
994#endif
995};
996
997/*
998 * exynos4_irq_demux_eint
999 *
1000 * This function demuxes the IRQ from from EINTs 16 to 31.
1001 * It is designed to be inlined into the specific handler
1002 * s5p_irq_demux_eintX_Y.
1003 *
1004 * Each EINT pend/mask registers handle eight of them.
1005 */
330c90a5 1006static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 1007{
1008 unsigned int irq;
1009
330c90a5
EK		 1010 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
1011 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 1012
1013 status &= ~mask;
1014 status &= 0xff;
1015
1016 while (status) {
1017 irq = fls(status) - 1;
1018 generic_handle_irq(irq + start);
1019 status &= ~(1 << irq);
1020 }
1021}
1022
330c90a5 1023static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 1024{
1025 struct irq_chip *chip = irq_get_chip(irq);
1026 chained_irq_enter(chip, desc);
330c90a5
EK		 1027 exynos_irq_demux_eint(IRQ_EINT(16));
1028 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 1029 chained_irq_exit(chip, desc);
1030}
1031
bb19a751 1032static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 1033{
1034 u32 *irq_data = irq_get_handler_data(irq);
1035 struct irq_chip *chip = irq_get_chip(irq);
1036
1037 chained_irq_enter(chip, desc);
1038 chip->irq_mask(&desc->irq_data);
1039
1040 if (chip->irq_ack)
1041 chip->irq_ack(&desc->irq_data);
1042
1043 generic_handle_irq(*irq_data);
1044
1045 chip->irq_unmask(&desc->irq_data);
1046 chained_irq_exit(chip, desc);
1047}
1048
330c90a5 1049static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 1050{
1051 int irq;
1052
fef05c29
TA		 1053#ifdef CONFIG_PINCTRL_SAMSUNG
1054 /*
1055 * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1056 * functionality along with support for external gpio and wakeup
1057 * interrupts. If the samsung pinctrl driver is enabled and includes
1058 * the wakeup interrupt support, then the setting up external wakeup
1059 * interrupts here can be skipped. This check here is temporary to
1060 * allow exynos4 platforms that do not use Samsung pinctrl driver to
1061 * co-exist with platforms that do. When all of the Samsung Exynos4
1062 * platforms switch over to using the pinctrl driver, the wakeup
1063 * interrupt support code here can be completely removed.
1064 */
1065 struct device_node *pctrl_np, *wkup_np;
1066 const char *pctrl_compat = "samsung,pinctrl-exynos4210";
1067 const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1068
1069 for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
1070 if (of_device_is_available(pctrl_np)) {
1071 wkup_np = of_find_compatible_node(pctrl_np, NULL,
1072 wkup_compat);
1073 if (wkup_np)
1074 return -ENODEV;
1075 }
1076 }
1077#endif
2edb36c4
KK		 1078 if (soc_is_exynos5440())
1079 return 0;
fef05c29 1080
94c7ca71 1081 if (soc_is_exynos5250())
330c90a5
EK		 1082 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1083 else
1084 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1085
1086 if (exynos_eint_base == NULL) {
1087 pr_err("unable to ioremap for EINT base address\n");
1088 return -ENOMEM;
1089 }
94c7ca71 1090
cc511b8d 1091 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 1092 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 1093 handle_level_irq);
1094 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1095 }
1096
330c90a5 1097 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 1098
1099 for (irq = 0 ; irq <= 15 ; irq++) {
1100 eint0_15_data[irq] = IRQ_EINT(irq);
1101
bb19a751
KK		 1102 if (soc_is_exynos5250()) {
1103 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1104 &eint0_15_data[irq]);
1105 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1106 exynos_irq_eint0_15);
1107 } else {
1108 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1109 &eint0_15_data[irq]);
1110 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1111 exynos_irq_eint0_15);
1112 }
cc511b8d
KK		 1113 }
1114
1115 return 0;
1116}
330c90a5 1117arch_initcall(exynos_init_irq_eint);
Linux kernel - Deliverables
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