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ARM: ep93xx: use machine specific hook for late init
[deliverable/linux.git] / arch / arm / mach-exynos / common.c
CommitLineData
cc511b8d
KK		 1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for EXYNOS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/irq.h>
15#include <linux/io.h>
7affca35 16#include <linux/device.h>
cc511b8d
KK		 17#include <linux/gpio.h>
18#include <linux/sched.h>
19#include <linux/serial_core.h>
237c78be
AB		 20#include <linux/of.h>
21#include <linux/of_irq.h>
cc511b8d
KK		 22
23#include <asm/proc-fns.h>
40ba95fd 24#include <asm/exception.h>
cc511b8d
KK		 25#include <asm/hardware/cache-l2x0.h>
26#include <asm/hardware/gic.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
b756a50f 29#include <asm/cacheflush.h>
cc511b8d
KK		 30
31#include <mach/regs-irq.h>
32#include <mach/regs-pmu.h>
33#include <mach/regs-gpio.h>
b756a50f 34#include <mach/pmu.h>
cc511b8d
KK		 35
36#include <plat/cpu.h>
37#include <plat/clock.h>
38#include <plat/devs.h>
39#include <plat/pm.h>
cc511b8d
KK		 40#include <plat/sdhci.h>
41#include <plat/gpio-cfg.h>
42#include <plat/adc-core.h>
43#include <plat/fb-core.h>
44#include <plat/fimc-core.h>
45#include <plat/iic-core.h>
46#include <plat/tv-core.h>
47#include <plat/regs-serial.h>
48
49#include "common.h"
6cdeddcc
ADK		 50#define L2_AUX_VAL 0x7C470001
51#define L2_AUX_MASK 0xC200ffff
cc511b8d 52
cc511b8d
KK		 53static const char name_exynos4210[] = "EXYNOS4210";
54static const char name_exynos4212[] = "EXYNOS4212";
55static const char name_exynos4412[] = "EXYNOS4412";
94c7ca71 56static const char name_exynos5250[] = "EXYNOS5250";
cc511b8d 57
906c789c 58static void exynos4_map_io(void);
94c7ca71 59static void exynos5_map_io(void);
906c789c 60static void exynos4_init_clocks(int xtal);
94c7ca71 61static void exynos5_init_clocks(int xtal);
920f4880 62static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
906c789c 63static int exynos_init(void);
cc511b8d
KK		 64
65static struct cpu_table cpu_ids[] __initdata = {
66 {
67 .idcode = EXYNOS4210_CPU_ID,
68 .idmask = EXYNOS4_CPU_MASK,
69 .map_io = exynos4_map_io,
70 .init_clocks = exynos4_init_clocks,
920f4880 71 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 72 .init = exynos_init,
73 .name = name_exynos4210,
74 }, {
75 .idcode = EXYNOS4212_CPU_ID,
76 .idmask = EXYNOS4_CPU_MASK,
77 .map_io = exynos4_map_io,
78 .init_clocks = exynos4_init_clocks,
920f4880 79 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 80 .init = exynos_init,
81 .name = name_exynos4212,
82 }, {
83 .idcode = EXYNOS4412_CPU_ID,
84 .idmask = EXYNOS4_CPU_MASK,
85 .map_io = exynos4_map_io,
86 .init_clocks = exynos4_init_clocks,
920f4880 87 .init_uarts = exynos_init_uarts,
cc511b8d
KK		 88 .init = exynos_init,
89 .name = name_exynos4412,
94c7ca71
KK		 90 }, {
91 .idcode = EXYNOS5250_SOC_ID,
92 .idmask = EXYNOS5_SOC_MASK,
93 .map_io = exynos5_map_io,
94 .init_clocks = exynos5_init_clocks,
95 .init_uarts = exynos_init_uarts,
96 .init = exynos_init,
97 .name = name_exynos5250,
cc511b8d
KK		 98 },
99};
100
101/* Initial IO mappings */
102
103static struct map_desc exynos_iodesc[] __initdata = {
104 {
105 .virtual = (unsigned long)S5P_VA_CHIPID,
94c7ca71 106 .pfn = __phys_to_pfn(EXYNOS_PA_CHIPID),
cc511b8d
KK		 107 .length = SZ_4K,
108 .type = MT_DEVICE,
94c7ca71
KK		 109 },
110};
111
112static struct map_desc exynos4_iodesc[] __initdata = {
113 {
cc511b8d
KK		 114 .virtual = (unsigned long)S3C_VA_SYS,
115 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
116 .length = SZ_64K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_TIMER,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
121 .length = SZ_16K,
122 .type = MT_DEVICE,
123 }, {
124 .virtual = (unsigned long)S3C_VA_WATCHDOG,
125 .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
126 .length = SZ_4K,
127 .type = MT_DEVICE,
128 }, {
129 .virtual = (unsigned long)S5P_VA_SROMC,
130 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
131 .length = SZ_4K,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = (unsigned long)S5P_VA_SYSTIMER,
135 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
136 .length = SZ_4K,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (unsigned long)S5P_VA_PMU,
140 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
141 .length = SZ_64K,
142 .type = MT_DEVICE,
143 }, {
144 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
145 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
146 .length = SZ_4K,
147 .type = MT_DEVICE,
148 }, {
149 .virtual = (unsigned long)S5P_VA_GIC_CPU,
150 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
151 .length = SZ_64K,
152 .type = MT_DEVICE,
153 }, {
154 .virtual = (unsigned long)S5P_VA_GIC_DIST,
155 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
156 .length = SZ_64K,
157 .type = MT_DEVICE,
158 }, {
159 .virtual = (unsigned long)S3C_VA_UART,
160 .pfn = __phys_to_pfn(EXYNOS4_PA_UART),
161 .length = SZ_512K,
162 .type = MT_DEVICE,
94c7ca71 163 }, {
cc511b8d
KK		 164 .virtual = (unsigned long)S5P_VA_CMU,
165 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
166 .length = SZ_128K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
170 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
171 .length = SZ_8K,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = (unsigned long)S5P_VA_L2CC,
175 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
176 .length = SZ_4K,
177 .type = MT_DEVICE,
cc511b8d
KK		 178 }, {
179 .virtual = (unsigned long)S5P_VA_DMC0,
180 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08
MH		 181 .length = SZ_64K,
182 .type = MT_DEVICE,
183 }, {
184 .virtual = (unsigned long)S5P_VA_DMC1,
185 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
186 .length = SZ_64K,
cc511b8d 187 .type = MT_DEVICE,
cc511b8d
KK		 188 }, {
189 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
190 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
191 .length = SZ_4K,
192 .type = MT_DEVICE,
193 },
194};
195
196static struct map_desc exynos4_iodesc0[] __initdata = {
197 {
198 .virtual = (unsigned long)S5P_VA_SYSRAM,
199 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
200 .length = SZ_4K,
201 .type = MT_DEVICE,
202 },
203};
204
205static struct map_desc exynos4_iodesc1[] __initdata = {
206 {
207 .virtual = (unsigned long)S5P_VA_SYSRAM,
208 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
209 .length = SZ_4K,
210 .type = MT_DEVICE,
211 },
212};
213
94c7ca71
KK		 214static struct map_desc exynos5_iodesc[] __initdata = {
215 {
216 .virtual = (unsigned long)S3C_VA_SYS,
217 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
218 .length = SZ_64K,
219 .type = MT_DEVICE,
220 }, {
221 .virtual = (unsigned long)S3C_VA_TIMER,
222 .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
223 .length = SZ_16K,
224 .type = MT_DEVICE,
225 }, {
226 .virtual = (unsigned long)S3C_VA_WATCHDOG,
227 .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
228 .length = SZ_4K,
229 .type = MT_DEVICE,
230 }, {
231 .virtual = (unsigned long)S5P_VA_SROMC,
232 .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
233 .length = SZ_4K,
234 .type = MT_DEVICE,
235 }, {
236 .virtual = (unsigned long)S5P_VA_SYSTIMER,
237 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
238 .length = SZ_4K,
239 .type = MT_DEVICE,
240 }, {
241 .virtual = (unsigned long)S5P_VA_SYSRAM,
242 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
243 .length = SZ_4K,
244 .type = MT_DEVICE,
245 }, {
246 .virtual = (unsigned long)S5P_VA_CMU,
247 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
248 .length = 144 * SZ_1K,
249 .type = MT_DEVICE,
250 }, {
251 .virtual = (unsigned long)S5P_VA_PMU,
252 .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
253 .length = SZ_64K,
254 .type = MT_DEVICE,
255 }, {
256 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
257 .pfn = __phys_to_pfn(EXYNOS5_PA_COMBINER),
258 .length = SZ_4K,
259 .type = MT_DEVICE,
260 }, {
261 .virtual = (unsigned long)S3C_VA_UART,
262 .pfn = __phys_to_pfn(EXYNOS5_PA_UART),
263 .length = SZ_512K,
264 .type = MT_DEVICE,
265 }, {
266 .virtual = (unsigned long)S5P_VA_GIC_CPU,
267 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
268 .length = SZ_64K,
269 .type = MT_DEVICE,
270 }, {
271 .virtual = (unsigned long)S5P_VA_GIC_DIST,
272 .pfn = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
273 .length = SZ_64K,
274 .type = MT_DEVICE,
275 },
276};
277
9eb48595 278void exynos4_restart(char mode, const char *cmd)
cc511b8d
KK		 279{
280 __raw_writel(0x1, S5P_SWRESET);
281}
282
94c7ca71
KK		 283void exynos5_restart(char mode, const char *cmd)
284{
285 __raw_writel(0x1, EXYNOS_SWRESET);
286}
287
cc511b8d
KK		 288/*
289 * exynos_map_io
290 *
291 * register the standard cpu IO areas
292 */
293
294void __init exynos_init_io(struct map_desc *mach_desc, int size)
295{
296 /* initialize the io descriptors we need for initialization */
297 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
298 if (mach_desc)
299 iotable_init(mach_desc, size);
300
301 /* detect cpu id and rev. */
302 s5p_init_cpu(S5P_VA_CHIPID);
303
304 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
305}
306
906c789c 307static void __init exynos4_map_io(void)
cc511b8d
KK		 308{
309 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
310
311 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
312 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
313 else
314 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
315
316 /* initialize device information early */
317 exynos4_default_sdhci0();
318 exynos4_default_sdhci1();
319 exynos4_default_sdhci2();
320 exynos4_default_sdhci3();
321
322 s3c_adc_setname("samsung-adc-v3");
323
324 s3c_fimc_setname(0, "exynos4-fimc");
325 s3c_fimc_setname(1, "exynos4-fimc");
326 s3c_fimc_setname(2, "exynos4-fimc");
327 s3c_fimc_setname(3, "exynos4-fimc");
328
329 /* The I2C bus controllers are directly compatible with s3c2440 */
330 s3c_i2c0_setname("s3c2440-i2c");
331 s3c_i2c1_setname("s3c2440-i2c");
332 s3c_i2c2_setname("s3c2440-i2c");
333
334 s5p_fb_setname(0, "exynos4-fb");
335 s5p_hdmi_setname("exynos4-hdmi");
336}
337
94c7ca71
KK		 338static void __init exynos5_map_io(void)
339{
340 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
341
bb19a751
KK		 342 s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
343 s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
344 s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
345 s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
346
94c7ca71
KK		 347 /* The I2C bus controllers are directly compatible with s3c2440 */
348 s3c_i2c0_setname("s3c2440-i2c");
349 s3c_i2c1_setname("s3c2440-i2c");
350 s3c_i2c2_setname("s3c2440-i2c");
351}
352
906c789c 353static void __init exynos4_init_clocks(int xtal)
cc511b8d
KK		 354{
355 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
356
357 s3c24xx_register_baseclocks(xtal);
358 s5p_register_clocks(xtal);
359
360 if (soc_is_exynos4210())
361 exynos4210_register_clocks();
362 else if (soc_is_exynos4212() || soc_is_exynos4412())
363 exynos4212_register_clocks();
364
365 exynos4_register_clocks();
366 exynos4_setup_clocks();
367}
368
94c7ca71
KK		 369static void __init exynos5_init_clocks(int xtal)
370{
371 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
372
373 s3c24xx_register_baseclocks(xtal);
374 s5p_register_clocks(xtal);
375
376 exynos5_register_clocks();
377 exynos5_setup_clocks();
378}
379
cc511b8d
KK		 380#define COMBINER_ENABLE_SET 0x0
381#define COMBINER_ENABLE_CLEAR 0x4
382#define COMBINER_INT_STATUS 0xC
383
384static DEFINE_SPINLOCK(irq_controller_lock);
385
386struct combiner_chip_data {
387 unsigned int irq_offset;
388 unsigned int irq_mask;
389 void __iomem *base;
390};
391
392static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
393
394static inline void __iomem *combiner_base(struct irq_data *data)
395{
396 struct combiner_chip_data *combiner_data =
397 irq_data_get_irq_chip_data(data);
398
399 return combiner_data->base;
400}
401
402static void combiner_mask_irq(struct irq_data *data)
403{
404 u32 mask = 1 << (data->irq % 32);
405
406 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
407}
408
409static void combiner_unmask_irq(struct irq_data *data)
410{
411 u32 mask = 1 << (data->irq % 32);
412
413 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
414}
415
416static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
417{
418 struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
419 struct irq_chip *chip = irq_get_chip(irq);
420 unsigned int cascade_irq, combiner_irq;
421 unsigned long status;
422
423 chained_irq_enter(chip, desc);
424
425 spin_lock(&irq_controller_lock);
426 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
427 spin_unlock(&irq_controller_lock);
428 status &= chip_data->irq_mask;
429
430 if (status == 0)
431 goto out;
432
433 combiner_irq = __ffs(status);
434
435 cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
436 if (unlikely(cascade_irq >= NR_IRQS))
437 do_bad_IRQ(cascade_irq, desc);
438 else
439 generic_handle_irq(cascade_irq);
440
441 out:
442 chained_irq_exit(chip, desc);
443}
444
445static struct irq_chip combiner_chip = {
446 .name = "COMBINER",
447 .irq_mask = combiner_mask_irq,
448 .irq_unmask = combiner_unmask_irq,
449};
450
451static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
452{
bb19a751
KK		 453 unsigned int max_nr;
454
455 if (soc_is_exynos5250())
456 max_nr = EXYNOS5_MAX_COMBINER_NR;
457 else
458 max_nr = EXYNOS4_MAX_COMBINER_NR;
459
460 if (combiner_nr >= max_nr)
cc511b8d
KK		 461 BUG();
462 if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
463 BUG();
464 irq_set_chained_handler(irq, combiner_handle_cascade_irq);
465}
466
467static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
468 unsigned int irq_start)
469{
470 unsigned int i;
bb19a751 471 unsigned int max_nr;
cc511b8d 472
bb19a751
KK		 473 if (soc_is_exynos5250())
474 max_nr = EXYNOS5_MAX_COMBINER_NR;
475 else
476 max_nr = EXYNOS4_MAX_COMBINER_NR;
477
478 if (combiner_nr >= max_nr)
cc511b8d
KK		 479 BUG();
480
481 combiner_data[combiner_nr].base = base;
482 combiner_data[combiner_nr].irq_offset = irq_start;
483 combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
484
485 /* Disable all interrupts */
486
487 __raw_writel(combiner_data[combiner_nr].irq_mask,
488 base + COMBINER_ENABLE_CLEAR);
489
490 /* Setup the Linux IRQ subsystem */
491
492 for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
493 + MAX_IRQ_IN_COMBINER; i++) {
494 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
495 irq_set_chip_data(i, &combiner_data[combiner_nr]);
496 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
497 }
498}
499
237c78be
AB		 500#ifdef CONFIG_OF
501static const struct of_device_id exynos4_dt_irq_match[] = {
502 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
503 {},
504};
505#endif
cc511b8d
KK		 506
507void __init exynos4_init_irq(void)
508{
509 int irq;
40ba95fd 510 unsigned int gic_bank_offset;
cc511b8d
KK		 511
512 gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
513
237c78be 514 if (!of_have_populated_dt())
75294957 515 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
237c78be
AB		 516#ifdef CONFIG_OF
517 else
518 of_irq_init(exynos4_dt_irq_match);
519#endif
cc511b8d 520
bb19a751 521 for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
cc511b8d
KK		 522
523 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
524 COMBINER_IRQ(irq, 0));
525 combiner_cascade_irq(irq, IRQ_SPI(irq));
526 }
527
528 /*
529 * The parameters of s5p_init_irq() are for VIC init.
530 * Theses parameters should be NULL and 0 because EXYNOS4
531 * uses GIC instead of VIC.
532 */
533 s5p_init_irq(NULL, 0);
534}
535
94c7ca71
KK		 536void __init exynos5_init_irq(void)
537{
538 int irq;
539
540 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
cc511b8d 541
bb19a751 542 for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
cc511b8d
KK		 543 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
544 COMBINER_IRQ(irq, 0));
545 combiner_cascade_irq(irq, IRQ_SPI(irq));
546 }
547
548 /*
549 * The parameters of s5p_init_irq() are for VIC init.
550 * Theses parameters should be NULL and 0 because EXYNOS4
551 * uses GIC instead of VIC.
552 */
553 s5p_init_irq(NULL, 0);
554}
555
7affca35
LT		 556struct bus_type exynos4_subsys = {
557 .name = "exynos4-core",
558 .dev_name = "exynos4-core",
cc511b8d
KK		 559};
560
94c7ca71
KK		 561struct bus_type exynos5_subsys = {
562 .name = "exynos5-core",
563 .dev_name = "exynos5-core",
564};
565
7affca35
LT		 566static struct device exynos4_dev = {
567 .bus = &exynos4_subsys,
cc511b8d
KK		 568};
569
94c7ca71
KK		 570static struct device exynos5_dev = {
571 .bus = &exynos5_subsys,
572};
573
574static int __init exynos_core_init(void)
cc511b8d 575{
94c7ca71
KK		 576 if (soc_is_exynos5250())
577 return subsys_system_register(&exynos5_subsys, NULL);
578 else
579 return subsys_system_register(&exynos4_subsys, NULL);
cc511b8d 580}
94c7ca71 581core_initcall(exynos_core_init);
cc511b8d
KK		 582
583#ifdef CONFIG_CACHE_L2X0
584static int __init exynos4_l2x0_cache_init(void)
585{
e1b1994e
IH		 586 int ret;
587
94c7ca71
KK		 588 if (soc_is_exynos5250())
589 return 0;
590
6cdeddcc
ADK		 591 ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
592 if (!ret) {
593 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
594 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
595 return 0;
596 }
cc511b8d 597
b756a50f
ADK		 598 if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
599 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
600 /* TAG, Data Latency Control: 2 cycles */
601 l2x0_saved_regs.tag_latency = 0x110;
cc511b8d 602
b756a50f
ADK		 603 if (soc_is_exynos4212() || soc_is_exynos4412())
604 l2x0_saved_regs.data_latency = 0x120;
605 else
606 l2x0_saved_regs.data_latency = 0x110;
607
608 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
609 l2x0_saved_regs.pwr_ctrl =
610 (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
cc511b8d 611
b756a50f 612 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d 613
b756a50f
ADK		 614 __raw_writel(l2x0_saved_regs.tag_latency,
615 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
616 __raw_writel(l2x0_saved_regs.data_latency,
617 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d 618
b756a50f
ADK		 619 /* L2X0 Prefetch Control */
620 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
621 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
622
623 /* L2X0 Power Control */
624 __raw_writel(l2x0_saved_regs.pwr_ctrl,
625 S5P_VA_L2CC + L2X0_POWER_CTRL);
626
627 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
628 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
629 }
cc511b8d 630
6cdeddcc 631 l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
cc511b8d
KK		 632 return 0;
633}
cc511b8d
KK		 634early_initcall(exynos4_l2x0_cache_init);
635#endif
636
94c7ca71
KK		 637static int __init exynos5_l2_cache_init(void)
638{
639 unsigned int val;
640
641 if (!soc_is_exynos5250())
642 return 0;
643
644 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
645 "bic %0, %0, #(1 << 2)\n" /* cache disable */
646 "mcr p15, 0, %0, c1, c0, 0\n"
647 "mrc p15, 1, %0, c9, c0, 2\n"
648 : "=r"(val));
649
650 val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
651
652 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
653 asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
654 "orr %0, %0, #(1 << 2)\n" /* cache enable */
655 "mcr p15, 0, %0, c1, c0, 0\n"
656 : : "r"(val));
657
658 return 0;
659}
660early_initcall(exynos5_l2_cache_init);
661
906c789c 662static int __init exynos_init(void)
cc511b8d
KK		 663{
664 printk(KERN_INFO "EXYNOS: Initializing architecture\n");
94c7ca71
KK		 665
666 if (soc_is_exynos5250())
667 return device_register(&exynos5_dev);
668 else
669 return device_register(&exynos4_dev);
cc511b8d
KK		 670}
671
cc511b8d
KK		 672/* uart registration process */
673
920f4880 674static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
cc511b8d
KK		 675{
676 struct s3c2410_uartcfg *tcfg = cfg;
677 u32 ucnt;
678
237c78be
AB		 679 for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
680 tcfg->has_fracval = 1;
cc511b8d 681
171c067c
KK		 682 if (soc_is_exynos5250())
683 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
684 else
685 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
cc511b8d
KK		 686}
687
330c90a5
EK		 688static void __iomem *exynos_eint_base;
689
cc511b8d
KK		 690static DEFINE_SPINLOCK(eint_lock);
691
692static unsigned int eint0_15_data[16];
693
330c90a5 694static inline int exynos4_irq_to_gpio(unsigned int irq)
cc511b8d 695{
330c90a5
EK		 696 if (irq < IRQ_EINT(0))
697 return -EINVAL;
cc511b8d 698
330c90a5
EK		 699 irq -= IRQ_EINT(0);
700 if (irq < 8)
701 return EXYNOS4_GPX0(irq);
702
703 irq -= 8;
704 if (irq < 8)
705 return EXYNOS4_GPX1(irq);
706
707 irq -= 8;
708 if (irq < 8)
709 return EXYNOS4_GPX2(irq);
710
711 irq -= 8;
712 if (irq < 8)
713 return EXYNOS4_GPX3(irq);
714
715 return -EINVAL;
716}
717
718static inline int exynos5_irq_to_gpio(unsigned int irq)
719{
720 if (irq < IRQ_EINT(0))
721 return -EINVAL;
722
723 irq -= IRQ_EINT(0);
724 if (irq < 8)
725 return EXYNOS5_GPX0(irq);
726
727 irq -= 8;
728 if (irq < 8)
729 return EXYNOS5_GPX1(irq);
730
731 irq -= 8;
732 if (irq < 8)
733 return EXYNOS5_GPX2(irq);
cc511b8d 734
330c90a5
EK		 735 irq -= 8;
736 if (irq < 8)
737 return EXYNOS5_GPX3(irq);
738
739 return -EINVAL;
cc511b8d
KK		 740}
741
bb19a751
KK		 742static unsigned int exynos4_eint0_15_src_int[16] = {
743 EXYNOS4_IRQ_EINT0,
744 EXYNOS4_IRQ_EINT1,
745 EXYNOS4_IRQ_EINT2,
746 EXYNOS4_IRQ_EINT3,
747 EXYNOS4_IRQ_EINT4,
748 EXYNOS4_IRQ_EINT5,
749 EXYNOS4_IRQ_EINT6,
750 EXYNOS4_IRQ_EINT7,
751 EXYNOS4_IRQ_EINT8,
752 EXYNOS4_IRQ_EINT9,
753 EXYNOS4_IRQ_EINT10,
754 EXYNOS4_IRQ_EINT11,
755 EXYNOS4_IRQ_EINT12,
756 EXYNOS4_IRQ_EINT13,
757 EXYNOS4_IRQ_EINT14,
758 EXYNOS4_IRQ_EINT15,
759};
cc511b8d 760
bb19a751
KK		 761static unsigned int exynos5_eint0_15_src_int[16] = {
762 EXYNOS5_IRQ_EINT0,
763 EXYNOS5_IRQ_EINT1,
764 EXYNOS5_IRQ_EINT2,
765 EXYNOS5_IRQ_EINT3,
766 EXYNOS5_IRQ_EINT4,
767 EXYNOS5_IRQ_EINT5,
768 EXYNOS5_IRQ_EINT6,
769 EXYNOS5_IRQ_EINT7,
770 EXYNOS5_IRQ_EINT8,
771 EXYNOS5_IRQ_EINT9,
772 EXYNOS5_IRQ_EINT10,
773 EXYNOS5_IRQ_EINT11,
774 EXYNOS5_IRQ_EINT12,
775 EXYNOS5_IRQ_EINT13,
776 EXYNOS5_IRQ_EINT14,
777 EXYNOS5_IRQ_EINT15,
778};
330c90a5 779static inline void exynos_irq_eint_mask(struct irq_data *data)
cc511b8d
KK		 780{
781 u32 mask;
782
783 spin_lock(&eint_lock);
330c90a5
EK		 784 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
785 mask |= EINT_OFFSET_BIT(data->irq);
786 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 787 spin_unlock(&eint_lock);
788}
789
330c90a5 790static void exynos_irq_eint_unmask(struct irq_data *data)
cc511b8d
KK		 791{
792 u32 mask;
793
794 spin_lock(&eint_lock);
330c90a5
EK		 795 mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
796 mask &= ~(EINT_OFFSET_BIT(data->irq));
797 __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
cc511b8d
KK		 798 spin_unlock(&eint_lock);
799}
800
330c90a5 801static inline void exynos_irq_eint_ack(struct irq_data *data)
cc511b8d 802{
330c90a5
EK		 803 __raw_writel(EINT_OFFSET_BIT(data->irq),
804 EINT_PEND(exynos_eint_base, data->irq));
cc511b8d
KK		 805}
806
330c90a5 807static void exynos_irq_eint_maskack(struct irq_data *data)
cc511b8d 808{
330c90a5
EK		 809 exynos_irq_eint_mask(data);
810 exynos_irq_eint_ack(data);
cc511b8d
KK		 811}
812
330c90a5 813static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
cc511b8d
KK		 814{
815 int offs = EINT_OFFSET(data->irq);
816 int shift;
817 u32 ctrl, mask;
818 u32 newvalue = 0;
819
820 switch (type) {
821 case IRQ_TYPE_EDGE_RISING:
822 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
823 break;
824
825 case IRQ_TYPE_EDGE_FALLING:
826 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
827 break;
828
829 case IRQ_TYPE_EDGE_BOTH:
830 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
831 break;
832
833 case IRQ_TYPE_LEVEL_LOW:
834 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
835 break;
836
837 case IRQ_TYPE_LEVEL_HIGH:
838 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
839 break;
840
841 default:
842 printk(KERN_ERR "No such irq type %d", type);
843 return -EINVAL;
844 }
845
846 shift = (offs & 0x7) * 4;
847 mask = 0x7 << shift;
848
849 spin_lock(&eint_lock);
330c90a5 850 ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 851 ctrl &= ~mask;
852 ctrl |= newvalue << shift;
330c90a5 853 __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
cc511b8d
KK		 854 spin_unlock(&eint_lock);
855
330c90a5
EK		 856 if (soc_is_exynos5250())
857 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
858 else
859 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
cc511b8d
KK		 860
861 return 0;
862}
863
330c90a5
EK		 864static struct irq_chip exynos_irq_eint = {
865 .name = "exynos-eint",
866 .irq_mask = exynos_irq_eint_mask,
867 .irq_unmask = exynos_irq_eint_unmask,
868 .irq_mask_ack = exynos_irq_eint_maskack,
869 .irq_ack = exynos_irq_eint_ack,
870 .irq_set_type = exynos_irq_eint_set_type,
cc511b8d
KK		 871#ifdef CONFIG_PM
872 .irq_set_wake = s3c_irqext_wake,
873#endif
874};
875
876/*
877 * exynos4_irq_demux_eint
878 *
879 * This function demuxes the IRQ from from EINTs 16 to 31.
880 * It is designed to be inlined into the specific handler
881 * s5p_irq_demux_eintX_Y.
882 *
883 * Each EINT pend/mask registers handle eight of them.
884 */
330c90a5 885static inline void exynos_irq_demux_eint(unsigned int start)
cc511b8d
KK		 886{
887 unsigned int irq;
888
330c90a5
EK		 889 u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
890 u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
cc511b8d
KK		 891
892 status &= ~mask;
893 status &= 0xff;
894
895 while (status) {
896 irq = fls(status) - 1;
897 generic_handle_irq(irq + start);
898 status &= ~(1 << irq);
899 }
900}
901
330c90a5 902static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 903{
904 struct irq_chip *chip = irq_get_chip(irq);
905 chained_irq_enter(chip, desc);
330c90a5
EK		 906 exynos_irq_demux_eint(IRQ_EINT(16));
907 exynos_irq_demux_eint(IRQ_EINT(24));
cc511b8d
KK		 908 chained_irq_exit(chip, desc);
909}
910
bb19a751 911static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
cc511b8d
KK		 912{
913 u32 *irq_data = irq_get_handler_data(irq);
914 struct irq_chip *chip = irq_get_chip(irq);
915
916 chained_irq_enter(chip, desc);
917 chip->irq_mask(&desc->irq_data);
918
919 if (chip->irq_ack)
920 chip->irq_ack(&desc->irq_data);
921
922 generic_handle_irq(*irq_data);
923
924 chip->irq_unmask(&desc->irq_data);
925 chained_irq_exit(chip, desc);
926}
927
330c90a5 928static int __init exynos_init_irq_eint(void)
cc511b8d
KK		 929{
930 int irq;
931
94c7ca71 932 if (soc_is_exynos5250())
330c90a5
EK		 933 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
934 else
935 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
936
937 if (exynos_eint_base == NULL) {
938 pr_err("unable to ioremap for EINT base address\n");
939 return -ENOMEM;
940 }
94c7ca71 941
cc511b8d 942 for (irq = 0 ; irq <= 31 ; irq++) {
330c90a5 943 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
cc511b8d
KK		 944 handle_level_irq);
945 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
946 }
947
330c90a5 948 irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
cc511b8d
KK		 949
950 for (irq = 0 ; irq <= 15 ; irq++) {
951 eint0_15_data[irq] = IRQ_EINT(irq);
952
bb19a751
KK		 953 if (soc_is_exynos5250()) {
954 irq_set_handler_data(exynos5_eint0_15_src_int[irq],
955 &eint0_15_data[irq]);
956 irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
957 exynos_irq_eint0_15);
958 } else {
959 irq_set_handler_data(exynos4_eint0_15_src_int[irq],
960 &eint0_15_data[irq]);
961 irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
962 exynos_irq_eint0_15);
963 }
cc511b8d
KK		 964 }
965
966 return 0;
967}
330c90a5 968arch_initcall(exynos_init_irq_eint);
Linux kernel - Deliverables
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