[deliverable/linux.git] / arch / arm / mach-exynos / common.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Common Codes for EXYNOS
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/cacheflush.h>

#include <mach/regs-irq.h>
#include <mach/regs-pmu.h>
#include <mach/regs-gpio.h>
#include <mach/pmu.h>

#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/sdhci.h>
#include <plat/gpio-cfg.h>
#include <plat/adc-core.h>
#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
#include <plat/tv-core.h>
#include <plat/regs-serial.h>

#include "common.h"

static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";

static struct cpu_table cpu_ids[] __initdata = {
	{
		.idcode		= EXYNOS4210_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init_clocks	= exynos4_init_clocks,
		.init_uarts	= exynos4_init_uarts,
		.init		= exynos_init,
		.name		= name_exynos4210,
	}, {
		.idcode		= EXYNOS4212_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init_clocks	= exynos4_init_clocks,
		.init_uarts	= exynos4_init_uarts,
		.init		= exynos_init,
		.name		= name_exynos4212,
	}, {
		.idcode		= EXYNOS4412_CPU_ID,
		.idmask		= EXYNOS4_CPU_MASK,
		.map_io		= exynos4_map_io,
		.init_clocks	= exynos4_init_clocks,
		.init_uarts	= exynos4_init_uarts,
		.init		= exynos_init,
		.name		= name_exynos4412,
	},
};

/* Initial IO mappings */

static struct map_desc exynos_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_CHIPID,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_UART,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),
		.length		= SZ_512K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_L2CC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GPIO1,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GPIO2,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GPIO3,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO3),
		.length		= SZ_256,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC0,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc1[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static void exynos_idle(void)
{
	if (!need_resched())
		cpu_do_idle();

	local_irq_enable();
}

void exynos4_restart(char mode, const char *cmd)
{
	__raw_writel(0x1, S5P_SWRESET);
}

/*
 * exynos_map_io
 *
 * register the standard cpu IO areas
 */

void __init exynos_init_io(struct map_desc *mach_desc, int size)
{
	/* initialize the io descriptors we need for initialization */
	iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
	if (mach_desc)
		iotable_init(mach_desc, size);

	/* detect cpu id and rev. */
	s5p_init_cpu(S5P_VA_CHIPID);

	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}

void __init exynos4_map_io(void)
{
	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
		iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	else
		iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));

	/* initialize device information early */
	exynos4_default_sdhci0();
	exynos4_default_sdhci1();
	exynos4_default_sdhci2();
	exynos4_default_sdhci3();

	s3c_adc_setname("samsung-adc-v3");

	s3c_fimc_setname(0, "exynos4-fimc");
	s3c_fimc_setname(1, "exynos4-fimc");
	s3c_fimc_setname(2, "exynos4-fimc");
	s3c_fimc_setname(3, "exynos4-fimc");

	/* The I2C bus controllers are directly compatible with s3c2440 */
	s3c_i2c0_setname("s3c2440-i2c");
	s3c_i2c1_setname("s3c2440-i2c");
	s3c_i2c2_setname("s3c2440-i2c");

	s5p_fb_setname(0, "exynos4-fb");
	s5p_hdmi_setname("exynos4-hdmi");
}

void __init exynos4_init_clocks(int xtal)
{
	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);

	s3c24xx_register_baseclocks(xtal);
	s5p_register_clocks(xtal);

	if (soc_is_exynos4210())
		exynos4210_register_clocks();
	else if (soc_is_exynos4212() || soc_is_exynos4412())
		exynos4212_register_clocks();

	exynos4_register_clocks();
	exynos4_setup_clocks();
}

#define COMBINER_ENABLE_SET	0x0
#define COMBINER_ENABLE_CLEAR	0x4
#define COMBINER_INT_STATUS	0xC

static DEFINE_SPINLOCK(irq_controller_lock);

struct combiner_chip_data {
	unsigned int irq_offset;
	unsigned int irq_mask;
	void __iomem *base;
};

static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];

static inline void __iomem *combiner_base(struct irq_data *data)
{
	struct combiner_chip_data *combiner_data =
		irq_data_get_irq_chip_data(data);

	return combiner_data->base;
}

static void combiner_mask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->irq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}

static void combiner_unmask_irq(struct irq_data *data)
{
	u32 mask = 1 << (data->irq % 32);

	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}

static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);
	unsigned int cascade_irq, combiner_irq;
	unsigned long status;

	chained_irq_enter(chip, desc);

	spin_lock(&irq_controller_lock);
	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
	spin_unlock(&irq_controller_lock);
	status &= chip_data->irq_mask;

	if (status == 0)
		goto out;

	combiner_irq = __ffs(status);

	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
	if (unlikely(cascade_irq >= NR_IRQS))
		do_bad_IRQ(cascade_irq, desc);
	else
		generic_handle_irq(cascade_irq);

 out:
	chained_irq_exit(chip, desc);
}

static struct irq_chip combiner_chip = {
	.name		= "COMBINER",
	.irq_mask	= combiner_mask_irq,
	.irq_unmask	= combiner_unmask_irq,
};

static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
	if (combiner_nr >= MAX_COMBINER_NR)
		BUG();
	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
		BUG();
	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
}

static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
			  unsigned int irq_start)
{
	unsigned int i;

	if (combiner_nr >= MAX_COMBINER_NR)
		BUG();

	combiner_data[combiner_nr].base = base;
	combiner_data[combiner_nr].irq_offset = irq_start;
	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);

	/* Disable all interrupts */

	__raw_writel(combiner_data[combiner_nr].irq_mask,
		     base + COMBINER_ENABLE_CLEAR);

	/* Setup the Linux IRQ subsystem */

	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
				+ MAX_IRQ_IN_COMBINER; i++) {
		irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
		irq_set_chip_data(i, &combiner_data[combiner_nr]);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
	}
}

#ifdef CONFIG_OF
static const struct of_device_id exynos4_dt_irq_match[] = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{},
};
#endif

void __init exynos4_init_irq(void)
{
	int irq;
	unsigned int gic_bank_offset;

	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;

	if (!of_have_populated_dt())
		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
#ifdef CONFIG_OF
	else
		of_irq_init(exynos4_dt_irq_match);
#endif

	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
				COMBINER_IRQ(irq, 0));
		combiner_cascade_irq(irq, IRQ_SPI(irq));
	}

	/*
	 * The parameters of s5p_init_irq() are for VIC init.
	 * Theses parameters should be NULL and 0 because EXYNOS4
	 * uses GIC instead of VIC.
	 */
	s5p_init_irq(NULL, 0);
}

struct bus_type exynos4_subsys = {
	.name		= "exynos4-core",
	.dev_name	= "exynos4-core",
};

static struct device exynos4_dev = {
	.bus	= &exynos4_subsys,
};

static int __init exynos4_core_init(void)
{
	return subsys_system_register(&exynos4_subsys, NULL);
}
core_initcall(exynos4_core_init);

#ifdef CONFIG_CACHE_L2X0
static int __init exynos4_l2x0_cache_init(void)
{
	if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
		l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
		/* TAG, Data Latency Control: 2 cycles */
		l2x0_saved_regs.tag_latency = 0x110;

		if (soc_is_exynos4212() || soc_is_exynos4412())
			l2x0_saved_regs.data_latency = 0x120;
		else
			l2x0_saved_regs.data_latency = 0x110;

		l2x0_saved_regs.prefetch_ctrl = 0x30000007;
		l2x0_saved_regs.pwr_ctrl =
			(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);

		l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);

		__raw_writel(l2x0_saved_regs.tag_latency,
				S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
		__raw_writel(l2x0_saved_regs.data_latency,
				S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);

		/* L2X0 Prefetch Control */
		__raw_writel(l2x0_saved_regs.prefetch_ctrl,
				S5P_VA_L2CC + L2X0_PREFETCH_CTRL);

		/* L2X0 Power Control */
		__raw_writel(l2x0_saved_regs.pwr_ctrl,
				S5P_VA_L2CC + L2X0_POWER_CTRL);

		clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
		clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
	}

	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);

	return 0;
}

early_initcall(exynos4_l2x0_cache_init);
#endif

int __init exynos_init(void)
{
	printk(KERN_INFO "EXYNOS: Initializing architecture\n");

	/* set idle function */
	pm_idle = exynos_idle;

	return device_register(&exynos4_dev);
}

/* uart registration process */

void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
	struct s3c2410_uartcfg *tcfg = cfg;
	u32 ucnt;

	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
		tcfg->has_fracval = 1;

	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
}

static DEFINE_SPINLOCK(eint_lock);

static unsigned int eint0_15_data[16];

static unsigned int exynos4_get_irq_nr(unsigned int number)
{
	u32 ret = 0;

	switch (number) {
	case 0 ... 3:
		ret = (number + IRQ_EINT0);
		break;
	case 4 ... 7:
		ret = (number + (IRQ_EINT4 - 4));
		break;
	case 8 ... 15:
		ret = (number + (IRQ_EINT8 - 8));
		break;
	default:
		printk(KERN_ERR "number available : %d\n", number);
	}

	return ret;
}

static inline void exynos4_irq_eint_mask(struct irq_data *data)
{
	u32 mask;

	spin_lock(&eint_lock);
	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask |= eint_irq_to_bit(data->irq);
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	spin_unlock(&eint_lock);
}

static void exynos4_irq_eint_unmask(struct irq_data *data)
{
	u32 mask;

	spin_lock(&eint_lock);
	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	mask &= ~(eint_irq_to_bit(data->irq));
	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	spin_unlock(&eint_lock);
}

static inline void exynos4_irq_eint_ack(struct irq_data *data)
{
	__raw_writel(eint_irq_to_bit(data->irq),
		     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}

static void exynos4_irq_eint_maskack(struct irq_data *data)
{
	exynos4_irq_eint_mask(data);
	exynos4_irq_eint_ack(data);
}

static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
	int offs = EINT_OFFSET(data->irq);
	int shift;
	u32 ctrl, mask;
	u32 newvalue = 0;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		newvalue = S5P_IRQ_TYPE_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
		break;

	default:
		printk(KERN_ERR "No such irq type %d", type);
		return -EINVAL;
	}

	shift = (offs & 0x7) * 4;
	mask = 0x7 << shift;

	spin_lock(&eint_lock);
	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
	ctrl &= ~mask;
	ctrl |= newvalue << shift;
	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
	spin_unlock(&eint_lock);

	switch (offs) {
	case 0 ... 7:
		s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
		break;
	case 8 ... 15:
		s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
		break;
	case 16 ... 23:
		s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
		break;
	case 24 ... 31:
		s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
		break;
	default:
		printk(KERN_ERR "No such irq number %d", offs);
	}

	return 0;
}

static struct irq_chip exynos4_irq_eint = {
	.name		= "exynos4-eint",
	.irq_mask	= exynos4_irq_eint_mask,
	.irq_unmask	= exynos4_irq_eint_unmask,
	.irq_mask_ack	= exynos4_irq_eint_maskack,
	.irq_ack	= exynos4_irq_eint_ack,
	.irq_set_type	= exynos4_irq_eint_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= s3c_irqext_wake,
#endif
};

/*
 * exynos4_irq_demux_eint
 *
 * This function demuxes the IRQ from from EINTs 16 to 31.
 * It is designed to be inlined into the specific handler
 * s5p_irq_demux_eintX_Y.
 *
 * Each EINT pend/mask registers handle eight of them.
 */
static inline void exynos4_irq_demux_eint(unsigned int start)
{
	unsigned int irq;

	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));

	status &= ~mask;
	status &= 0xff;

	while (status) {
		irq = fls(status) - 1;
		generic_handle_irq(irq + start);
		status &= ~(1 << irq);
	}
}

static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
	struct irq_chip *chip = irq_get_chip(irq);
	chained_irq_enter(chip, desc);
	exynos4_irq_demux_eint(IRQ_EINT(16));
	exynos4_irq_demux_eint(IRQ_EINT(24));
	chained_irq_exit(chip, desc);
}

static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
	u32 *irq_data = irq_get_handler_data(irq);
	struct irq_chip *chip = irq_get_chip(irq);

	chained_irq_enter(chip, desc);
	chip->irq_mask(&desc->irq_data);

	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);

	generic_handle_irq(*irq_data);

	chip->irq_unmask(&desc->irq_data);
	chained_irq_exit(chip, desc);
}

int __init exynos4_init_irq_eint(void)
{
	int irq;

	for (irq = 0 ; irq <= 31 ; irq++) {
		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
					 handle_level_irq);
		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);

	for (irq = 0 ; irq <= 15 ; irq++) {
		eint0_15_data[irq] = IRQ_EINT(irq);

		irq_set_handler_data(exynos4_get_irq_nr(irq),
				     &eint0_15_data[irq]);
		irq_set_chained_handler(exynos4_get_irq_nr(irq),
					exynos4_irq_eint0_15);
	}

	return 0;
}
arch_initcall(exynos4_init_irq_eint);
Commit	Line	Data
cc511b8d KK	1	/*
	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* Common Codes for EXYNOS
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
7affca35	16	#include <linux/device.h>
cc511b8d KK	17	#include <linux/gpio.h>
	18	#include <linux/sched.h>
	19	#include <linux/serial_core.h>
237c78be AB	20	#include <linux/of.h>
237c78be AB	21	#include <linux/of_irq.h>
cc511b8d KK	22
cc511b8d KK	23	#include <asm/proc-fns.h>
40ba95fd	24	#include <asm/exception.h>
cc511b8d KK	25	#include <asm/hardware/cache-l2x0.h>
	26	#include <asm/hardware/gic.h>
	27	#include <asm/mach/map.h>
	28	#include <asm/mach/irq.h>
b756a50f	29	#include <asm/cacheflush.h>
cc511b8d KK	30
	31	#include <mach/regs-irq.h>
	32	#include <mach/regs-pmu.h>
	33	#include <mach/regs-gpio.h>
b756a50f	34	#include <mach/pmu.h>
cc511b8d KK	35
	36	#include <plat/cpu.h>
	37	#include <plat/clock.h>
	38	#include <plat/devs.h>
	39	#include <plat/pm.h>
cc511b8d KK	40	#include <plat/sdhci.h>
	41	#include <plat/gpio-cfg.h>
	42	#include <plat/adc-core.h>
	43	#include <plat/fb-core.h>
	44	#include <plat/fimc-core.h>
	45	#include <plat/iic-core.h>
	46	#include <plat/tv-core.h>
	47	#include <plat/regs-serial.h>
	48
	49	#include "common.h"
	50
cc511b8d KK	51	static const char name_exynos4210[] = "EXYNOS4210";
	52	static const char name_exynos4212[] = "EXYNOS4212";
	53	static const char name_exynos4412[] = "EXYNOS4412";
	54
	55	static struct cpu_table cpu_ids[] __initdata = {
	56	{
	57	.idcode = EXYNOS4210_CPU_ID,
	58	.idmask = EXYNOS4_CPU_MASK,
	59	.map_io = exynos4_map_io,
	60	.init_clocks = exynos4_init_clocks,
	61	.init_uarts = exynos4_init_uarts,
	62	.init = exynos_init,
	63	.name = name_exynos4210,
	64	}, {
	65	.idcode = EXYNOS4212_CPU_ID,
	66	.idmask = EXYNOS4_CPU_MASK,
	67	.map_io = exynos4_map_io,
	68	.init_clocks = exynos4_init_clocks,
	69	.init_uarts = exynos4_init_uarts,
	70	.init = exynos_init,
	71	.name = name_exynos4212,
	72	}, {
	73	.idcode = EXYNOS4412_CPU_ID,
	74	.idmask = EXYNOS4_CPU_MASK,
	75	.map_io = exynos4_map_io,
	76	.init_clocks = exynos4_init_clocks,
	77	.init_uarts = exynos4_init_uarts,
	78	.init = exynos_init,
	79	.name = name_exynos4412,
	80	},
	81	};
	82
	83	/* Initial IO mappings */
	84
	85	static struct map_desc exynos_iodesc[] __initdata = {
	86	{
	87	.virtual = (unsigned long)S5P_VA_CHIPID,
	88	.pfn = __phys_to_pfn(EXYNOS4_PA_CHIPID),
	89	.length = SZ_4K,
	90	.type = MT_DEVICE,
	91	}, {
	92	.virtual = (unsigned long)S3C_VA_SYS,
	93	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
	94	.length = SZ_64K,
	95	.type = MT_DEVICE,
	96	}, {
	97	.virtual = (unsigned long)S3C_VA_TIMER,
	98	.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
	99	.length = SZ_16K,
	100	.type = MT_DEVICE,
	101	}, {
	102	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	103	.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
	104	.length = SZ_4K,
	105	.type = MT_DEVICE,
	106	}, {
	107	.virtual = (unsigned long)S5P_VA_SROMC,
	108	.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
	109	.length = SZ_4K,
	110	.type = MT_DEVICE,
	111	}, {
	112	.virtual = (unsigned long)S5P_VA_SYSTIMER,
	113	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
	114	.length = SZ_4K,
115	.type = MT_DEVICE,
116	}, {
117	.virtual = (unsigned long)S5P_VA_PMU,
118	.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
119	.length = SZ_64K,
120	.type = MT_DEVICE,
121	}, {
122	.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
123	.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
124	.length = SZ_4K,
125	.type = MT_DEVICE,
126	}, {
127	.virtual = (unsigned long)S5P_VA_GIC_CPU,
128	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
129	.length = SZ_64K,
130	.type = MT_DEVICE,
131	}, {
132	.virtual = (unsigned long)S5P_VA_GIC_DIST,
133	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
134	.length = SZ_64K,
135	.type = MT_DEVICE,
136	}, {
137	.virtual = (unsigned long)S3C_VA_UART,
138	.pfn = __phys_to_pfn(EXYNOS4_PA_UART),
139	.length = SZ_512K,
140	.type = MT_DEVICE,
141	},
142	};
143
144	static struct map_desc exynos4_iodesc[] __initdata = {
145	{
146	.virtual = (unsigned long)S5P_VA_CMU,
147	.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
148	.length = SZ_128K,
149	.type = MT_DEVICE,
150	}, {
151	.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
152	.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
153	.length = SZ_8K,
154	.type = MT_DEVICE,
155	}, {
156	.virtual = (unsigned long)S5P_VA_L2CC,
157	.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
158	.length = SZ_4K,
159	.type = MT_DEVICE,
160	}, {
161	.virtual = (unsigned long)S5P_VA_GPIO1,
162	.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
163	.length = SZ_4K,
164	.type = MT_DEVICE,
165	}, {
166	.virtual = (unsigned long)S5P_VA_GPIO2,
167	.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
168	.length = SZ_4K,
169	.type = MT_DEVICE,
170	}, {
171	.virtual = (unsigned long)S5P_VA_GPIO3,
172	.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
173	.length = SZ_256,
174	.type = MT_DEVICE,
175	}, {
176	.virtual = (unsigned long)S5P_VA_DMC0,
177	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
178	.length = SZ_4K,
179	.type = MT_DEVICE,
cc511b8d KK	180	}, {
	181	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
	182	.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
	183	.length = SZ_4K,
	184	.type = MT_DEVICE,
	185	},
	186	};
	187
	188	static struct map_desc exynos4_iodesc0[] __initdata = {
	189	{
	190	.virtual = (unsigned long)S5P_VA_SYSRAM,
	191	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
	192	.length = SZ_4K,
	193	.type = MT_DEVICE,
	194	},
	195	};
	196
	197	static struct map_desc exynos4_iodesc1[] __initdata = {
	198	{
	199	.virtual = (unsigned long)S5P_VA_SYSRAM,
	200	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
	201	.length = SZ_4K,
	202	.type = MT_DEVICE,
	203	},
	204	};
	205
	206	static void exynos_idle(void)
	207	{
	208	if (!need_resched())
	209	cpu_do_idle();
	210
	211	local_irq_enable();
	212	}
	213
9eb48595	214	void exynos4_restart(char mode, const char *cmd)
cc511b8d KK	215	{
	216	__raw_writel(0x1, S5P_SWRESET);
	217	}
	218
	219	/*
	220	* exynos_map_io
	221	*
	222	* register the standard cpu IO areas
	223	*/
	224
	225	void __init exynos_init_io(struct map_desc *mach_desc, int size)
	226	{
	227	/* initialize the io descriptors we need for initialization */
	228	iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
	229	if (mach_desc)
	230	iotable_init(mach_desc, size);
	231
	232	/* detect cpu id and rev. */
	233	s5p_init_cpu(S5P_VA_CHIPID);
	234
	235	s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
	236	}
	237
	238	void __init exynos4_map_io(void)
	239	{
	240	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
	241
	242	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
	243	iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
	244	else
	245	iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
	246
	247	/* initialize device information early */
	248	exynos4_default_sdhci0();
	249	exynos4_default_sdhci1();
	250	exynos4_default_sdhci2();
	251	exynos4_default_sdhci3();
	252
	253	s3c_adc_setname("samsung-adc-v3");
	254
	255	s3c_fimc_setname(0, "exynos4-fimc");
	256	s3c_fimc_setname(1, "exynos4-fimc");
	257	s3c_fimc_setname(2, "exynos4-fimc");
	258	s3c_fimc_setname(3, "exynos4-fimc");
	259
	260	/* The I2C bus controllers are directly compatible with s3c2440 */
	261	s3c_i2c0_setname("s3c2440-i2c");
	262	s3c_i2c1_setname("s3c2440-i2c");
	263	s3c_i2c2_setname("s3c2440-i2c");
	264
	265	s5p_fb_setname(0, "exynos4-fb");
	266	s5p_hdmi_setname("exynos4-hdmi");
	267	}
	268
	269	void __init exynos4_init_clocks(int xtal)
	270	{
	271	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
	272
	273	s3c24xx_register_baseclocks(xtal);
	274	s5p_register_clocks(xtal);
	275
	276	if (soc_is_exynos4210())
	277	exynos4210_register_clocks();
	278	else if (soc_is_exynos4212() \|\| soc_is_exynos4412())
279	exynos4212_register_clocks();
280
281	exynos4_register_clocks();
282	exynos4_setup_clocks();
283	}
284
285	#define COMBINER_ENABLE_SET 0x0
286	#define COMBINER_ENABLE_CLEAR 0x4
287	#define COMBINER_INT_STATUS 0xC
288
289	static DEFINE_SPINLOCK(irq_controller_lock);
290
291	struct combiner_chip_data {
292	unsigned int irq_offset;
293	unsigned int irq_mask;
294	void __iomem *base;
295	};
296
297	static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
298
299	static inline void __iomem combiner_base(struct irq_data data)
300	{
301	struct combiner_chip_data *combiner_data =
302	irq_data_get_irq_chip_data(data);
303
304	return combiner_data->base;
305	}
306
307	static void combiner_mask_irq(struct irq_data *data)
308	{
309	u32 mask = 1 << (data->irq % 32);
310
311	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
312	}
313
314	static void combiner_unmask_irq(struct irq_data *data)
315	{
316	u32 mask = 1 << (data->irq % 32);
317
318	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
319	}
320
321	static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
322	{
323	struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
324	struct irq_chip *chip = irq_get_chip(irq);
325	unsigned int cascade_irq, combiner_irq;
326	unsigned long status;
327
328	chained_irq_enter(chip, desc);
329
330	spin_lock(&irq_controller_lock);
331	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
332	spin_unlock(&irq_controller_lock);
333	status &= chip_data->irq_mask;
334
335	if (status == 0)
336	goto out;
337
338	combiner_irq = __ffs(status);
339
340	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
341	if (unlikely(cascade_irq >= NR_IRQS))
342	do_bad_IRQ(cascade_irq, desc);
343	else
344	generic_handle_irq(cascade_irq);
345
346	out:
347	chained_irq_exit(chip, desc);
348	}
349
350	static struct irq_chip combiner_chip = {
351	.name = "COMBINER",
352	.irq_mask = combiner_mask_irq,
353	.irq_unmask = combiner_unmask_irq,
354	};
355
356	static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
357	{
358	if (combiner_nr >= MAX_COMBINER_NR)
359	BUG();
360	if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
361	BUG();
362	irq_set_chained_handler(irq, combiner_handle_cascade_irq);
363	}
364
365	static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
366	unsigned int irq_start)
367	{
368	unsigned int i;
369
370	if (combiner_nr >= MAX_COMBINER_NR)
371	BUG();
372
373	combiner_data[combiner_nr].base = base;
374	combiner_data[combiner_nr].irq_offset = irq_start;
375	combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
376
377	/* Disable all interrupts */
378
379	__raw_writel(combiner_data[combiner_nr].irq_mask,
380	base + COMBINER_ENABLE_CLEAR);
381
382	/* Setup the Linux IRQ subsystem */
383
384	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
385	+ MAX_IRQ_IN_COMBINER; i++) {
386	irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
387	irq_set_chip_data(i, &combiner_data[combiner_nr]);
388	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
389	}
390	}
391
237c78be AB	392	#ifdef CONFIG_OF
	393	static const struct of_device_id exynos4_dt_irq_match[] = {
	394	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	395	{},
	396	};
	397	#endif
cc511b8d KK	398
	399	void __init exynos4_init_irq(void)
	400	{
	401	int irq;
40ba95fd	402	unsigned int gic_bank_offset;
cc511b8d KK	403
	404	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
	405
237c78be AB	406	if (!of_have_populated_dt())
	407	gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
	408	#ifdef CONFIG_OF
	409	else
	410	of_irq_init(exynos4_dt_irq_match);
	411	#endif
cc511b8d KK	412
	413	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
	414
	415	combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
	416	COMBINER_IRQ(irq, 0));
	417	combiner_cascade_irq(irq, IRQ_SPI(irq));
	418	}
	419
	420	/*
	421	* The parameters of s5p_init_irq() are for VIC init.
	422	* Theses parameters should be NULL and 0 because EXYNOS4
	423	* uses GIC instead of VIC.
	424	*/
	425	s5p_init_irq(NULL, 0);
	426	}
	427
7affca35 LT	428	struct bus_type exynos4_subsys = {
	429	.name = "exynos4-core",
	430	.dev_name = "exynos4-core",
cc511b8d KK	431	};
cc511b8d KK	432
7affca35 LT	433	static struct device exynos4_dev = {
7affca35 LT	434	.bus = &exynos4_subsys,
cc511b8d KK	435	};
	436
	437	static int __init exynos4_core_init(void)
	438	{
7affca35	439	return subsys_system_register(&exynos4_subsys, NULL);
cc511b8d KK	440	}
	441	core_initcall(exynos4_core_init);
	442
	443	#ifdef CONFIG_CACHE_L2X0
	444	static int __init exynos4_l2x0_cache_init(void)
	445	{
b756a50f ADK	446	if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
	447	l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
	448	/* TAG, Data Latency Control: 2 cycles */
	449	l2x0_saved_regs.tag_latency = 0x110;
cc511b8d	450
b756a50f ADK	451	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	452	l2x0_saved_regs.data_latency = 0x120;
	453	else
	454	l2x0_saved_regs.data_latency = 0x110;
	455
	456	l2x0_saved_regs.prefetch_ctrl = 0x30000007;
	457	l2x0_saved_regs.pwr_ctrl =
	458	(L2X0_DYNAMIC_CLK_GATING_EN \| L2X0_STNDBY_MODE_EN);
	459
	460	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
cc511b8d	461
b756a50f ADK	462	__raw_writel(l2x0_saved_regs.tag_latency,
	463	S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
	464	__raw_writel(l2x0_saved_regs.data_latency,
	465	S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
cc511b8d	466
b756a50f ADK	467	/* L2X0 Prefetch Control */
	468	__raw_writel(l2x0_saved_regs.prefetch_ctrl,
	469	S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
	470
	471	/* L2X0 Power Control */
	472	__raw_writel(l2x0_saved_regs.pwr_ctrl,
	473	S5P_VA_L2CC + L2X0_POWER_CTRL);
	474
	475	clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
	476	clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
	477	}
cc511b8d KK	478
	479	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
	480
	481	return 0;
	482	}
	483
	484	early_initcall(exynos4_l2x0_cache_init);
	485	#endif
	486
	487	int __init exynos_init(void)
	488	{
	489	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
	490
	491	/* set idle function */
	492	pm_idle = exynos_idle;
	493
7affca35	494	return device_register(&exynos4_dev);
cc511b8d KK	495	}
cc511b8d KK	496
cc511b8d KK	497	/* uart registration process */
	498
	499	void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	500	{
	501	struct s3c2410_uartcfg *tcfg = cfg;
	502	u32 ucnt;
	503
237c78be AB	504	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
237c78be AB	505	tcfg->has_fracval = 1;
cc511b8d	506
237c78be	507	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
cc511b8d KK	508	}
	509
	510	static DEFINE_SPINLOCK(eint_lock);
	511
	512	static unsigned int eint0_15_data[16];
	513
	514	static unsigned int exynos4_get_irq_nr(unsigned int number)
	515	{
	516	u32 ret = 0;
	517
	518	switch (number) {
	519	case 0 ... 3:
	520	ret = (number + IRQ_EINT0);
	521	break;
	522	case 4 ... 7:
	523	ret = (number + (IRQ_EINT4 - 4));
	524	break;
	525	case 8 ... 15:
	526	ret = (number + (IRQ_EINT8 - 8));
	527	break;
	528	default:
	529	printk(KERN_ERR "number available : %d\n", number);
	530	}
	531
	532	return ret;
	533	}
	534
	535	static inline void exynos4_irq_eint_mask(struct irq_data *data)
	536	{
	537	u32 mask;
	538
	539	spin_lock(&eint_lock);
	540	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	541	mask \|= eint_irq_to_bit(data->irq);
	542	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	543	spin_unlock(&eint_lock);
	544	}
	545
	546	static void exynos4_irq_eint_unmask(struct irq_data *data)
	547	{
	548	u32 mask;
	549
	550	spin_lock(&eint_lock);
	551	mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	552	mask &= ~(eint_irq_to_bit(data->irq));
	553	__raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
	554	spin_unlock(&eint_lock);
	555	}
	556
	557	static inline void exynos4_irq_eint_ack(struct irq_data *data)
	558	{
	559	__raw_writel(eint_irq_to_bit(data->irq),
	560	S5P_EINT_PEND(EINT_REG_NR(data->irq)));
	561	}
	562
	563	static void exynos4_irq_eint_maskack(struct irq_data *data)
	564	{
	565	exynos4_irq_eint_mask(data);
	566	exynos4_irq_eint_ack(data);
	567	}
	568
	569	static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
	570	{
	571	int offs = EINT_OFFSET(data->irq);
572	int shift;
573	u32 ctrl, mask;
574	u32 newvalue = 0;
575
576	switch (type) {
577	case IRQ_TYPE_EDGE_RISING:
578	newvalue = S5P_IRQ_TYPE_EDGE_RISING;
579	break;
580
581	case IRQ_TYPE_EDGE_FALLING:
582	newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
583	break;
584
585	case IRQ_TYPE_EDGE_BOTH:
586	newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
587	break;
588
589	case IRQ_TYPE_LEVEL_LOW:
590	newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
591	break;
592
593	case IRQ_TYPE_LEVEL_HIGH:
594	newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
595	break;
596
597	default:
598	printk(KERN_ERR "No such irq type %d", type);
599	return -EINVAL;
600	}
601
602	shift = (offs & 0x7) * 4;
603	mask = 0x7 << shift;
604
605	spin_lock(&eint_lock);
606	ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
607	ctrl &= ~mask;
608	ctrl \|= newvalue << shift;
609	__raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
610	spin_unlock(&eint_lock);
611
612	switch (offs) {
613	case 0 ... 7:
614	s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
615	break;
616	case 8 ... 15:
617	s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
618	break;
619	case 16 ... 23:
620	s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
621	break;
622	case 24 ... 31:
623	s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
624	break;
625	default:
626	printk(KERN_ERR "No such irq number %d", offs);
627	}
628
629	return 0;
630	}
631
632	static struct irq_chip exynos4_irq_eint = {
633	.name = "exynos4-eint",
634	.irq_mask = exynos4_irq_eint_mask,
635	.irq_unmask = exynos4_irq_eint_unmask,
636	.irq_mask_ack = exynos4_irq_eint_maskack,
637	.irq_ack = exynos4_irq_eint_ack,
638	.irq_set_type = exynos4_irq_eint_set_type,
639	#ifdef CONFIG_PM
640	.irq_set_wake = s3c_irqext_wake,
641	#endif
642	};
643
644	/*
645	* exynos4_irq_demux_eint
646	*
647	* This function demuxes the IRQ from from EINTs 16 to 31.
648	* It is designed to be inlined into the specific handler
649	* s5p_irq_demux_eintX_Y.
650	*
651	* Each EINT pend/mask registers handle eight of them.
652	*/
653	static inline void exynos4_irq_demux_eint(unsigned int start)
654	{
655	unsigned int irq;
656
657	u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
658	u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
659
660	status &= ~mask;
661	status &= 0xff;
662
663	while (status) {
664	irq = fls(status) - 1;
665	generic_handle_irq(irq + start);
666	status &= ~(1 << irq);
667	}
668	}
669
670	static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
671	{
672	struct irq_chip *chip = irq_get_chip(irq);
673	chained_irq_enter(chip, desc);
674	exynos4_irq_demux_eint(IRQ_EINT(16));
675	exynos4_irq_demux_eint(IRQ_EINT(24));
676	chained_irq_exit(chip, desc);
677	}
678
679	static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
680	{
681	u32 *irq_data = irq_get_handler_data(irq);
682	struct irq_chip *chip = irq_get_chip(irq);
683
684	chained_irq_enter(chip, desc);
685	chip->irq_mask(&desc->irq_data);
686
687	if (chip->irq_ack)
688	chip->irq_ack(&desc->irq_data);
689
690	generic_handle_irq(*irq_data);
691
692	chip->irq_unmask(&desc->irq_data);
693	chained_irq_exit(chip, desc);
694	}
695
696	int __init exynos4_init_irq_eint(void)
697	{
698	int irq;
699
700	for (irq = 0 ; irq <= 31 ; irq++) {
701	irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
702	handle_level_irq);
703	set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
704	}
705
706	irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
707
708	for (irq = 0 ; irq <= 15 ; irq++) {
709	eint0_15_data[irq] = IRQ_EINT(irq);
710
711	irq_set_handler_data(exynos4_get_irq_nr(irq),
712	&eint0_15_data[irq]);
713	irq_set_chained_handler(exynos4_get_irq_nr(irq),
714	exynos4_irq_eint0_15);
715	}
716
717	return 0;
718	}
719	arch_initcall(exynos4_init_irq_eint);