[deliverable/linux.git] / arch / arm / mach-exynos / cpuidle.c

/* linux/arch/arm/mach-exynos4/cpuidle.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/time.h>

#include <asm/proc-fns.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <asm/unified.h>
#include <asm/cpuidle.h>
#include <mach/regs-pmu.h>
#include <mach/pmu.h>

#include <plat/cpu.h>

#define REG_DIRECTGO_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
#define REG_DIRECTGO_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))

#define S5P_CHECK_AFTR		0xFCBA0D10

static int exynos4_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index);

static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
	[0] = ARM_CPUIDLE_WFI_STATE,
	[1] = {
		.enter			= exynos4_enter_lowpower,
		.exit_latency		= 300,
		.target_residency	= 100000,
		.flags			= CPUIDLE_FLAG_TIME_VALID,
		.name			= "C1",
		.desc			= "ARM power down",
	},
};

static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);

static struct cpuidle_driver exynos4_idle_driver = {
	.name			= "exynos4_idle",
	.owner			= THIS_MODULE,
	.en_core_tk_irqen	= 1,
};

/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos4_set_wakeupmask(void)
{
	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
}

static unsigned int g_pwr_ctrl, g_diag_reg;

static void save_cpu_arch_register(void)
{
	/*read power control register*/
	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	/*read diagnostic register*/
	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	return;
}

static void restore_cpu_arch_register(void)
{
	/*write power control register*/
	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	/*write diagnostic register*/
	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	return;
}

static int idle_finisher(unsigned long flags)
{
	cpu_do_idle();
	return 1;
}

static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	unsigned long tmp;

	exynos4_set_wakeupmask();

	/* Set value of power down register for aftr mode */
	exynos_sys_powerdown_conf(SYS_AFTR);

	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);

	save_cpu_arch_register();

	/* Setting Central Sequence Register for power down mode */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	cpu_pm_enter();
	cpu_suspend(0, idle_finisher);

#ifdef CONFIG_SMP
	scu_enable(S5P_VA_SCU);
#endif
	cpu_pm_exit();

	restore_cpu_arch_register();

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	}

	/* Clear wakeup state register */
	__raw_writel(0x0, S5P_WAKEUP_STAT);

	return index;
}

static int exynos4_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	int new_index = index;

	/* This mode only can be entered when other core's are offline */
	if (num_online_cpus() > 1)
		new_index = drv->safe_state_index;

	if (new_index == 0)
		return arm_cpuidle_simple_enter(dev, drv, new_index);
	else
		return exynos4_enter_core0_aftr(dev, drv, new_index);
}

static int __init exynos4_init_cpuidle(void)
{
	int i, max_cpuidle_state, cpu_id;
	struct cpuidle_device *device;
	struct cpuidle_driver *drv = &exynos4_idle_driver;

	/* Setup cpuidle driver */
	drv->state_count = (sizeof(exynos4_cpuidle_set) /
				       sizeof(struct cpuidle_state));
	max_cpuidle_state = drv->state_count;
	for (i = 0; i < max_cpuidle_state; i++) {
		memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
				sizeof(struct cpuidle_state));
	}
	drv->safe_state_index = 0;
	cpuidle_register_driver(&exynos4_idle_driver);

	for_each_cpu(cpu_id, cpu_online_mask) {
		device = &per_cpu(exynos4_cpuidle_device, cpu_id);
		device->cpu = cpu_id;

		if (cpu_id == 0)
			device->state_count = (sizeof(exynos4_cpuidle_set) /
					       sizeof(struct cpuidle_state));
		else
			device->state_count = 1;	/* Support IDLE only */

		if (cpuidle_register_device(device)) {
			printk(KERN_ERR "CPUidle register device failed\n,");
			return -EIO;
		}
	}

	return 0;
}
device_initcall(exynos4_init_cpuidle);
Commit	Line	Data
3d739985 JL	1	/* linux/arch/arm/mach-exynos4/cpuidle.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/cpuidle.h>
67173ca4	14	#include <linux/cpu_pm.h>
3d739985	15	#include <linux/io.h>
76ee4557 KP	16	#include <linux/export.h>
76ee4557 KP	17	#include <linux/time.h>
3d739985 JL	18
3d739985 JL	19	#include <asm/proc-fns.h>
67173ca4 ADK	20	#include <asm/smp_scu.h>
	21	#include <asm/suspend.h>
	22	#include <asm/unified.h>
06c77b3c	23	#include <asm/cpuidle.h>
67173ca4 ADK	24	#include <mach/regs-pmu.h>
	25	#include <mach/pmu.h>
	26
	27	#include <plat/cpu.h>
	28
	29	#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	30	S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	31	(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
	32	#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	33	S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	34	(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
	35
	36	#define S5P_CHECK_AFTR 0xFCBA0D10
3d739985	37
67173ca4 ADK	38	static int exynos4_enter_lowpower(struct cpuidle_device *dev,
	39	struct cpuidle_driver *drv,
	40	int index);
3d739985	41
67173ca4	42	static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
06c77b3c	43	[0] = ARM_CPUIDLE_WFI_STATE,
67173ca4 ADK	44	[1] = {
	45	.enter = exynos4_enter_lowpower,
	46	.exit_latency = 300,
	47	.target_residency = 100000,
	48	.flags = CPUIDLE_FLAG_TIME_VALID,
	49	.name = "C1",
	50	.desc = "ARM power down",
	51	},
3d739985 JL	52	};
	53
	54	static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
	55
	56	static struct cpuidle_driver exynos4_idle_driver = {
06c77b3c ADK	57	.name = "exynos4_idle",
	58	.owner = THIS_MODULE,
	59	.en_core_tk_irqen = 1,
3d739985 JL	60	};
3d739985 JL	61
67173ca4 ADK	62	/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
	63	static void exynos4_set_wakeupmask(void)
	64	{
	65	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
	66	}
	67
	68	static unsigned int g_pwr_ctrl, g_diag_reg;
	69
	70	static void save_cpu_arch_register(void)
	71	{
	72	/read power control register/
	73	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	74	/read diagnostic register/
	75	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	76	return;
	77	}
	78
	79	static void restore_cpu_arch_register(void)
	80	{
	81	/write power control register/
	82	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	83	/write diagnostic register/
	84	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	85	return;
	86	}
	87
	88	static int idle_finisher(unsigned long flags)
	89	{
	90	cpu_do_idle();
	91	return 1;
	92	}
	93
	94	static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
	95	struct cpuidle_driver *drv,
	96	int index)
	97	{
67173ca4 ADK	98	unsigned long tmp;
67173ca4 ADK	99
67173ca4 ADK	100	exynos4_set_wakeupmask();
	101
	102	/* Set value of power down register for aftr mode */
7d44d2ba	103	exynos_sys_powerdown_conf(SYS_AFTR);
67173ca4 ADK	104
	105	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
	106	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
	107
	108	save_cpu_arch_register();
	109
	110	/* Setting Central Sequence Register for power down mode */
	111	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	112	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	113	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	114
	115	cpu_pm_enter();
	116	cpu_suspend(0, idle_finisher);
	117
	118	#ifdef CONFIG_SMP
	119	scu_enable(S5P_VA_SCU);
	120	#endif
	121	cpu_pm_exit();
	122
	123	restore_cpu_arch_register();
	124
	125	/*
	126	* If PMU failed while entering sleep mode, WFI will be
	127	* ignored by PMU and then exiting cpu_do_idle().
	128	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	129	* in this situation.
	130	*/
	131	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	132	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	133	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	134	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	135	}
	136
	137	/* Clear wakeup state register */
	138	__raw_writel(0x0, S5P_WAKEUP_STAT);
	139
e978aa7d	140	return index;
3d739985 JL	141	}
3d739985 JL	142
67173ca4 ADK	143	static int exynos4_enter_lowpower(struct cpuidle_device *dev,
	144	struct cpuidle_driver *drv,
	145	int index)
	146	{
	147	int new_index = index;
	148
	149	/* This mode only can be entered when other core's are offline */
	150	if (num_online_cpus() > 1)
	151	new_index = drv->safe_state_index;
	152
	153	if (new_index == 0)
06c77b3c	154	return arm_cpuidle_simple_enter(dev, drv, new_index);
67173ca4 ADK	155	else
	156	return exynos4_enter_core0_aftr(dev, drv, new_index);
	157	}
	158
3d739985 JL	159	static int __init exynos4_init_cpuidle(void)
	160	{
	161	int i, max_cpuidle_state, cpu_id;
	162	struct cpuidle_device *device;
46bcfad7 DD	163	struct cpuidle_driver *drv = &exynos4_idle_driver;
	164
	165	/* Setup cpuidle driver */
	166	drv->state_count = (sizeof(exynos4_cpuidle_set) /
	167	sizeof(struct cpuidle_state));
	168	max_cpuidle_state = drv->state_count;
	169	for (i = 0; i < max_cpuidle_state; i++) {
	170	memcpy(&drv->states[i], &exynos4_cpuidle_set[i],
	171	sizeof(struct cpuidle_state));
	172	}
67173ca4	173	drv->safe_state_index = 0;
3d739985 JL	174	cpuidle_register_driver(&exynos4_idle_driver);
	175
	176	for_each_cpu(cpu_id, cpu_online_mask) {
	177	device = &per_cpu(exynos4_cpuidle_device, cpu_id);
	178	device->cpu = cpu_id;
	179
67173ca4 ADK	180	if (cpu_id == 0)
	181	device->state_count = (sizeof(exynos4_cpuidle_set) /
	182	sizeof(struct cpuidle_state));
	183	else
	184	device->state_count = 1; /* Support IDLE only */
3d739985 JL	185
	186	if (cpuidle_register_device(device)) {
	187	printk(KERN_ERR "CPUidle register device failed\n,");
	188	return -EIO;
	189	}
	190	}
67173ca4	191
3d739985 JL	192	return 0;
	193	}
	194	device_initcall(exynos4_init_cpuidle);