[deliverable/linux.git] / arch / arm / mach-exynos / cpuidle.c

/* linux/arch/arm/mach-exynos4/cpuidle.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/time.h>
#include <linux/platform_device.h>

#include <asm/proc-fns.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <asm/unified.h>
#include <asm/cpuidle.h>

#include <plat/cpu.h>
#include <plat/pm.h>

#include <mach/map.h>

#include "common.h"
#include "regs-pmu.h"

#define REG_DIRECTGO_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
#define REG_DIRECTGO_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))

#define S5P_CHECK_AFTR		0xFCBA0D10

/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos4_set_wakeupmask(void)
{
	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
}

static unsigned int g_pwr_ctrl, g_diag_reg;

static void save_cpu_arch_register(void)
{
	/*read power control register*/
	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	/*read diagnostic register*/
	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	return;
}

static void restore_cpu_arch_register(void)
{
	/*write power control register*/
	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	/*write diagnostic register*/
	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	return;
}

static int idle_finisher(unsigned long flags)
{
	cpu_do_idle();
	return 1;
}

static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	unsigned long tmp;

	exynos4_set_wakeupmask();

	/* Set value of power down register for aftr mode */
	exynos_sys_powerdown_conf(SYS_AFTR);

	__raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);

	save_cpu_arch_register();

	/* Setting Central Sequence Register for power down mode */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	cpu_pm_enter();
	cpu_suspend(0, idle_finisher);

#ifdef CONFIG_SMP
	if (!soc_is_exynos5250())
		scu_enable(S5P_VA_SCU);
#endif
	cpu_pm_exit();

	restore_cpu_arch_register();

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	}

	/* Clear wakeup state register */
	__raw_writel(0x0, S5P_WAKEUP_STAT);

	return index;
}

static int exynos4_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	int new_index = index;

	/* AFTR can only be entered when cores other than CPU0 are offline */
	if (num_online_cpus() > 1 || dev->cpu != 0)
		new_index = drv->safe_state_index;

	if (new_index == 0)
		return arm_cpuidle_simple_enter(dev, drv, new_index);
	else
		return exynos4_enter_core0_aftr(dev, drv, new_index);
}

static struct cpuidle_driver exynos4_idle_driver = {
	.name			= "exynos4_idle",
	.owner			= THIS_MODULE,
	.states = {
		[0] = ARM_CPUIDLE_WFI_STATE,
		[1] = {
			.enter			= exynos4_enter_lowpower,
			.exit_latency		= 300,
			.target_residency	= 100000,
			.flags			= CPUIDLE_FLAG_TIME_VALID,
			.name			= "C1",
			.desc			= "ARM power down",
		},
	},
	.state_count = 2,
	.safe_state_index = 0,
};

static int exynos_cpuidle_probe(struct platform_device *pdev)
{
	int ret;

	if (soc_is_exynos5440())
		exynos4_idle_driver.state_count = 1;

	ret = cpuidle_register(&exynos4_idle_driver, NULL);
	if (ret) {
		dev_err(&pdev->dev, "failed to register cpuidle driver\n");
		return ret;
	}

	return 0;
}

static struct platform_driver exynos_cpuidle_driver = {
	.probe	= exynos_cpuidle_probe,
	.driver = {
		.name = "exynos_cpuidle",
		.owner = THIS_MODULE,
	},
};

module_platform_driver(exynos_cpuidle_driver);
Commit	Line	Data
3d739985 JL	1	/* linux/arch/arm/mach-exynos4/cpuidle.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/cpuidle.h>
67173ca4	14	#include <linux/cpu_pm.h>
3d739985	15	#include <linux/io.h>
76ee4557	16	#include <linux/export.h>
96c3a250	17	#include <linux/module.h>
76ee4557	18	#include <linux/time.h>
35baa336	19	#include <linux/platform_device.h>
3d739985 JL	20
3d739985 JL	21	#include <asm/proc-fns.h>
67173ca4 ADK	22	#include <asm/smp_scu.h>
	23	#include <asm/suspend.h>
	24	#include <asm/unified.h>
06c77b3c	25	#include <asm/cpuidle.h>
67173ca4 ADK	26
67173ca4 ADK	27	#include <plat/cpu.h>
89693016	28	#include <plat/pm.h>
67173ca4	29
b5fd1300 KK	30	#include <mach/map.h>
b5fd1300 KK	31
ccd458c1	32	#include "common.h"
65c9a853	33	#include "regs-pmu.h"
ccd458c1	34
67173ca4 ADK	35	#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	36	S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	37	(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
	38	#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	39	S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	40	(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
	41
	42	#define S5P_CHECK_AFTR 0xFCBA0D10
3d739985	43
67173ca4 ADK	44	/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
	45	static void exynos4_set_wakeupmask(void)
	46	{
	47	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
	48	}
	49
	50	static unsigned int g_pwr_ctrl, g_diag_reg;
	51
	52	static void save_cpu_arch_register(void)
	53	{
	54	/read power control register/
	55	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	56	/read diagnostic register/
	57	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	58	return;
	59	}
	60
	61	static void restore_cpu_arch_register(void)
	62	{
	63	/write power control register/
	64	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	65	/write diagnostic register/
	66	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	67	return;
	68	}
	69
	70	static int idle_finisher(unsigned long flags)
	71	{
	72	cpu_do_idle();
	73	return 1;
	74	}
	75
	76	static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
	77	struct cpuidle_driver *drv,
	78	int index)
	79	{
67173ca4 ADK	80	unsigned long tmp;
67173ca4 ADK	81
67173ca4 ADK	82	exynos4_set_wakeupmask();
	83
	84	/* Set value of power down register for aftr mode */
7d44d2ba	85	exynos_sys_powerdown_conf(SYS_AFTR);
67173ca4	86
8dec067d	87	__raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
67173ca4 ADK	88	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
	89
	90	save_cpu_arch_register();
	91
	92	/* Setting Central Sequence Register for power down mode */
	93	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	94	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	95	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	96
	97	cpu_pm_enter();
	98	cpu_suspend(0, idle_finisher);
	99
	100	#ifdef CONFIG_SMP
a633208f AK	101	if (!soc_is_exynos5250())
a633208f AK	102	scu_enable(S5P_VA_SCU);
67173ca4 ADK	103	#endif
	104	cpu_pm_exit();
	105
	106	restore_cpu_arch_register();
	107
	108	/*
	109	* If PMU failed while entering sleep mode, WFI will be
	110	* ignored by PMU and then exiting cpu_do_idle().
	111	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	112	* in this situation.
	113	*/
	114	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	115	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	116	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	117	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	118	}
	119
	120	/* Clear wakeup state register */
	121	__raw_writel(0x0, S5P_WAKEUP_STAT);
	122
e978aa7d	123	return index;
3d739985 JL	124	}
3d739985 JL	125
67173ca4 ADK	126	static int exynos4_enter_lowpower(struct cpuidle_device *dev,
	127	struct cpuidle_driver *drv,
	128	int index)
	129	{
	130	int new_index = index;
	131
118f5c1d BZ	132	/* AFTR can only be entered when cores other than CPU0 are offline */
118f5c1d BZ	133	if (num_online_cpus() > 1 \|\| dev->cpu != 0)
67173ca4 ADK	134	new_index = drv->safe_state_index;
	135
	136	if (new_index == 0)
06c77b3c	137	return arm_cpuidle_simple_enter(dev, drv, new_index);
67173ca4 ADK	138	else
	139	return exynos4_enter_core0_aftr(dev, drv, new_index);
	140	}
	141
53af16a1 DL	142	static struct cpuidle_driver exynos4_idle_driver = {
	143	.name = "exynos4_idle",
	144	.owner = THIS_MODULE,
	145	.states = {
	146	[0] = ARM_CPUIDLE_WFI_STATE,
	147	[1] = {
	148	.enter = exynos4_enter_lowpower,
	149	.exit_latency = 300,
	150	.target_residency = 100000,
	151	.flags = CPUIDLE_FLAG_TIME_VALID,
	152	.name = "C1",
	153	.desc = "ARM power down",
	154	},
	155	},
	156	.state_count = 2,
	157	.safe_state_index = 0,
	158	};
	159
f612a4fb	160	static int exynos_cpuidle_probe(struct platform_device *pdev)
3d739985	161	{
043c86b6	162	int ret;
46bcfad7	163
1e9fec0e ADK	164	if (soc_is_exynos5440())
	165	exynos4_idle_driver.state_count = 1;
	166
043c86b6	167	ret = cpuidle_register(&exynos4_idle_driver, NULL);
5db9f436	168	if (ret) {
ae7c4c87	169	dev_err(&pdev->dev, "failed to register cpuidle driver\n");
5db9f436	170	return ret;
46bcfad7	171	}
3d739985	172
3d739985 JL	173	return 0;
3d739985 JL	174	}
35baa336 BZ	175
	176	static struct platform_driver exynos_cpuidle_driver = {
	177	.probe = exynos_cpuidle_probe,
	178	.driver = {
	179	.name = "exynos_cpuidle",
	180	.owner = THIS_MODULE,
	181	},
	182	};
	183
	184	module_platform_driver(exynos_cpuidle_driver);