[deliverable/linux.git] / arch / arm / mach-exynos / cpuidle.c

/* linux/arch/arm/mach-exynos4/cpuidle.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/time.h>

#include <asm/proc-fns.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>
#include <asm/unified.h>
#include <asm/cpuidle.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>

#include <plat/cpu.h>

#include "common.h"

#define REG_DIRECTGO_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
#define REG_DIRECTGO_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))

#define S5P_CHECK_AFTR		0xFCBA0D10

static int exynos4_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index);

static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);

static struct cpuidle_driver exynos4_idle_driver = {
	.name			= "exynos4_idle",
	.owner			= THIS_MODULE,
	.en_core_tk_irqen	= 1,
	.states = {
		[0] = ARM_CPUIDLE_WFI_STATE,
		[1] = {
			.enter			= exynos4_enter_lowpower,
			.exit_latency		= 300,
			.target_residency	= 100000,
			.flags			= CPUIDLE_FLAG_TIME_VALID,
			.name			= "C1",
			.desc			= "ARM power down",
		},
	},
	.state_count = 2,
	.safe_state_index = 0,
};

/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos4_set_wakeupmask(void)
{
	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
}

static unsigned int g_pwr_ctrl, g_diag_reg;

static void save_cpu_arch_register(void)
{
	/*read power control register*/
	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	/*read diagnostic register*/
	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	return;
}

static void restore_cpu_arch_register(void)
{
	/*write power control register*/
	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	/*write diagnostic register*/
	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	return;
}

static int idle_finisher(unsigned long flags)
{
	cpu_do_idle();
	return 1;
}

static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	unsigned long tmp;

	exynos4_set_wakeupmask();

	/* Set value of power down register for aftr mode */
	exynos_sys_powerdown_conf(SYS_AFTR);

	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);

	save_cpu_arch_register();

	/* Setting Central Sequence Register for power down mode */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	cpu_pm_enter();
	cpu_suspend(0, idle_finisher);

#ifdef CONFIG_SMP
	if (!soc_is_exynos5250())
		scu_enable(S5P_VA_SCU);
#endif
	cpu_pm_exit();

	restore_cpu_arch_register();

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	}

	/* Clear wakeup state register */
	__raw_writel(0x0, S5P_WAKEUP_STAT);

	return index;
}

static int exynos4_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	int new_index = index;

	/* This mode only can be entered when other core's are offline */
	if (num_online_cpus() > 1)
		new_index = drv->safe_state_index;

	if (new_index == 0)
		return arm_cpuidle_simple_enter(dev, drv, new_index);
	else
		return exynos4_enter_core0_aftr(dev, drv, new_index);
}

static void __init exynos5_core_down_clk(void)
{
	unsigned int tmp;

	/*
	 * Enable arm clock down (in idle) and set arm divider
	 * ratios in WFI/WFE state.
	 */
	tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
	      PWR_CTRL1_CORE1_DOWN_RATIO | \
	      PWR_CTRL1_DIV2_DOWN_EN	 | \
	      PWR_CTRL1_DIV1_DOWN_EN	 | \
	      PWR_CTRL1_USE_CORE1_WFE	 | \
	      PWR_CTRL1_USE_CORE0_WFE	 | \
	      PWR_CTRL1_USE_CORE1_WFI	 | \
	      PWR_CTRL1_USE_CORE0_WFI;
	__raw_writel(tmp, EXYNOS5_PWR_CTRL1);

	/*
	 * Enable arm clock up (on exiting idle). Set arm divider
	 * ratios when not in idle along with the standby duration
	 * ratios.
	 */
	tmp = PWR_CTRL2_DIV2_UP_EN	 | \
	      PWR_CTRL2_DIV1_UP_EN	 | \
	      PWR_CTRL2_DUR_STANDBY2_VAL | \
	      PWR_CTRL2_DUR_STANDBY1_VAL | \
	      PWR_CTRL2_CORE2_UP_RATIO	 | \
	      PWR_CTRL2_CORE1_UP_RATIO;
	__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
}

static int __init exynos4_init_cpuidle(void)
{
	int cpu_id;
	struct cpuidle_device *device;

	if (soc_is_exynos5250())
		exynos5_core_down_clk();

	cpuidle_register_driver(&exynos4_idle_driver);

	for_each_cpu(cpu_id, cpu_online_mask) {
		device = &per_cpu(exynos4_cpuidle_device, cpu_id);
		device->cpu = cpu_id;

		/* Support IDLE only */
		if (cpu_id != 0)
			device->state_count = 1;

		if (cpuidle_register_device(device)) {
			printk(KERN_ERR "CPUidle register device failed\n,");
			return -EIO;
		}
	}

	return 0;
}
device_initcall(exynos4_init_cpuidle);
Commit	Line	Data
3d739985 JL	1	/* linux/arch/arm/mach-exynos4/cpuidle.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/init.h>
	13	#include <linux/cpuidle.h>
67173ca4	14	#include <linux/cpu_pm.h>
3d739985	15	#include <linux/io.h>
76ee4557 KP	16	#include <linux/export.h>
76ee4557 KP	17	#include <linux/time.h>
3d739985 JL	18
3d739985 JL	19	#include <asm/proc-fns.h>
67173ca4 ADK	20	#include <asm/smp_scu.h>
	21	#include <asm/suspend.h>
	22	#include <asm/unified.h>
06c77b3c	23	#include <asm/cpuidle.h>
0f9e0359	24	#include <mach/regs-clock.h>
67173ca4	25	#include <mach/regs-pmu.h>
67173ca4 ADK	26
	27	#include <plat/cpu.h>
	28
ccd458c1 KK	29	#include "common.h"
ccd458c1 KK	30
67173ca4 ADK	31	#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	32	S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	33	(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
	34	#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
	35	S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
	36	(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
	37
	38	#define S5P_CHECK_AFTR 0xFCBA0D10
3d739985	39
67173ca4 ADK	40	static int exynos4_enter_lowpower(struct cpuidle_device *dev,
	41	struct cpuidle_driver *drv,
	42	int index);
3d739985	43
3d739985 JL	44	static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
	45
	46	static struct cpuidle_driver exynos4_idle_driver = {
06c77b3c ADK	47	.name = "exynos4_idle",
	48	.owner = THIS_MODULE,
	49	.en_core_tk_irqen = 1,
2eb89f89 DL	50	.states = {
	51	[0] = ARM_CPUIDLE_WFI_STATE,
	52	[1] = {
	53	.enter = exynos4_enter_lowpower,
	54	.exit_latency = 300,
	55	.target_residency = 100000,
	56	.flags = CPUIDLE_FLAG_TIME_VALID,
	57	.name = "C1",
	58	.desc = "ARM power down",
	59	},
	60	},
	61	.state_count = 2,
	62	.safe_state_index = 0,
3d739985 JL	63	};
3d739985 JL	64
67173ca4 ADK	65	/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
	66	static void exynos4_set_wakeupmask(void)
	67	{
	68	__raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
	69	}
	70
	71	static unsigned int g_pwr_ctrl, g_diag_reg;
	72
	73	static void save_cpu_arch_register(void)
	74	{
	75	/read power control register/
	76	asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
	77	/read diagnostic register/
	78	asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
	79	return;
	80	}
	81
	82	static void restore_cpu_arch_register(void)
	83	{
	84	/write power control register/
	85	asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
	86	/write diagnostic register/
	87	asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
	88	return;
	89	}
	90
	91	static int idle_finisher(unsigned long flags)
	92	{
	93	cpu_do_idle();
	94	return 1;
	95	}
	96
	97	static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
	98	struct cpuidle_driver *drv,
	99	int index)
	100	{
67173ca4 ADK	101	unsigned long tmp;
67173ca4 ADK	102
67173ca4 ADK	103	exynos4_set_wakeupmask();
	104
	105	/* Set value of power down register for aftr mode */
7d44d2ba	106	exynos_sys_powerdown_conf(SYS_AFTR);
67173ca4 ADK	107
	108	__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
	109	__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
	110
	111	save_cpu_arch_register();
	112
	113	/* Setting Central Sequence Register for power down mode */
	114	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	115	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	116	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	117
	118	cpu_pm_enter();
	119	cpu_suspend(0, idle_finisher);
	120
	121	#ifdef CONFIG_SMP
a633208f AK	122	if (!soc_is_exynos5250())
a633208f AK	123	scu_enable(S5P_VA_SCU);
67173ca4 ADK	124	#endif
	125	cpu_pm_exit();
	126
	127	restore_cpu_arch_register();
	128
	129	/*
	130	* If PMU failed while entering sleep mode, WFI will be
	131	* ignored by PMU and then exiting cpu_do_idle().
	132	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	133	* in this situation.
	134	*/
	135	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	136	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	137	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	138	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	139	}
	140
	141	/* Clear wakeup state register */
	142	__raw_writel(0x0, S5P_WAKEUP_STAT);
	143
e978aa7d	144	return index;
3d739985 JL	145	}
3d739985 JL	146
67173ca4 ADK	147	static int exynos4_enter_lowpower(struct cpuidle_device *dev,
	148	struct cpuidle_driver *drv,
	149	int index)
	150	{
	151	int new_index = index;
	152
	153	/* This mode only can be entered when other core's are offline */
	154	if (num_online_cpus() > 1)
	155	new_index = drv->safe_state_index;
	156
	157	if (new_index == 0)
06c77b3c	158	return arm_cpuidle_simple_enter(dev, drv, new_index);
67173ca4 ADK	159	else
	160	return exynos4_enter_core0_aftr(dev, drv, new_index);
	161	}
	162
0f9e0359 AK	163	static void __init exynos5_core_down_clk(void)
	164	{
	165	unsigned int tmp;
	166
	167	/*
	168	* Enable arm clock down (in idle) and set arm divider
	169	* ratios in WFI/WFE state.
	170	*/
	171	tmp = PWR_CTRL1_CORE2_DOWN_RATIO \| \
	172	PWR_CTRL1_CORE1_DOWN_RATIO \| \
	173	PWR_CTRL1_DIV2_DOWN_EN \| \
	174	PWR_CTRL1_DIV1_DOWN_EN \| \
	175	PWR_CTRL1_USE_CORE1_WFE \| \
	176	PWR_CTRL1_USE_CORE0_WFE \| \
	177	PWR_CTRL1_USE_CORE1_WFI \| \
	178	PWR_CTRL1_USE_CORE0_WFI;
	179	__raw_writel(tmp, EXYNOS5_PWR_CTRL1);
	180
	181	/*
	182	* Enable arm clock up (on exiting idle). Set arm divider
	183	* ratios when not in idle along with the standby duration
	184	* ratios.
	185	*/
	186	tmp = PWR_CTRL2_DIV2_UP_EN \| \
	187	PWR_CTRL2_DIV1_UP_EN \| \
	188	PWR_CTRL2_DUR_STANDBY2_VAL \| \
	189	PWR_CTRL2_DUR_STANDBY1_VAL \| \
	190	PWR_CTRL2_CORE2_UP_RATIO \| \
	191	PWR_CTRL2_CORE1_UP_RATIO;
	192	__raw_writel(tmp, EXYNOS5_PWR_CTRL2);
	193	}
	194
3d739985 JL	195	static int __init exynos4_init_cpuidle(void)
3d739985 JL	196	{
2eb89f89	197	int cpu_id;
3d739985	198	struct cpuidle_device *device;
46bcfad7	199
0f9e0359 AK	200	if (soc_is_exynos5250())
	201	exynos5_core_down_clk();
	202
3d739985 JL	203	cpuidle_register_driver(&exynos4_idle_driver);
	204
	205	for_each_cpu(cpu_id, cpu_online_mask) {
	206	device = &per_cpu(exynos4_cpuidle_device, cpu_id);
	207	device->cpu = cpu_id;
	208
2eb89f89 DL	209	/* Support IDLE only */
	210	if (cpu_id != 0)
	211	device->state_count = 1;
3d739985 JL	212
	213	if (cpuidle_register_device(device)) {
	214	printk(KERN_ERR "CPUidle register device failed\n,");
	215	return -EIO;
	216	}
	217	}
67173ca4	218
3d739985 JL	219	return 0;
	220	}
	221	device_initcall(exynos4_init_cpuidle);