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3d739985 JL |
1 | /* linux/arch/arm/mach-exynos4/cpuidle.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/cpuidle.h> | |
67173ca4 | 14 | #include <linux/cpu_pm.h> |
3d739985 | 15 | #include <linux/io.h> |
76ee4557 | 16 | #include <linux/export.h> |
96c3a250 | 17 | #include <linux/module.h> |
76ee4557 | 18 | #include <linux/time.h> |
35baa336 | 19 | #include <linux/platform_device.h> |
3d739985 JL |
20 | |
21 | #include <asm/proc-fns.h> | |
67173ca4 ADK |
22 | #include <asm/smp_scu.h> |
23 | #include <asm/suspend.h> | |
24 | #include <asm/unified.h> | |
06c77b3c | 25 | #include <asm/cpuidle.h> |
67173ca4 ADK |
26 | |
27 | #include <plat/cpu.h> | |
89693016 | 28 | #include <plat/pm.h> |
67173ca4 | 29 | |
b5fd1300 KK |
30 | #include <mach/map.h> |
31 | ||
ccd458c1 | 32 | #include "common.h" |
65c9a853 | 33 | #include "regs-pmu.h" |
ccd458c1 | 34 | |
67173ca4 ADK |
35 | #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ |
36 | S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
37 | (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) | |
38 | #define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ | |
39 | S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
40 | (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) | |
41 | ||
42 | #define S5P_CHECK_AFTR 0xFCBA0D10 | |
3d739985 | 43 | |
3d739985 JL |
44 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); |
45 | ||
67173ca4 ADK |
46 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ |
47 | static void exynos4_set_wakeupmask(void) | |
48 | { | |
49 | __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); | |
50 | } | |
51 | ||
52 | static unsigned int g_pwr_ctrl, g_diag_reg; | |
53 | ||
54 | static void save_cpu_arch_register(void) | |
55 | { | |
56 | /*read power control register*/ | |
57 | asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); | |
58 | /*read diagnostic register*/ | |
59 | asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); | |
60 | return; | |
61 | } | |
62 | ||
63 | static void restore_cpu_arch_register(void) | |
64 | { | |
65 | /*write power control register*/ | |
66 | asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); | |
67 | /*write diagnostic register*/ | |
68 | asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); | |
69 | return; | |
70 | } | |
71 | ||
72 | static int idle_finisher(unsigned long flags) | |
73 | { | |
74 | cpu_do_idle(); | |
75 | return 1; | |
76 | } | |
77 | ||
78 | static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, | |
79 | struct cpuidle_driver *drv, | |
80 | int index) | |
81 | { | |
67173ca4 ADK |
82 | unsigned long tmp; |
83 | ||
67173ca4 ADK |
84 | exynos4_set_wakeupmask(); |
85 | ||
86 | /* Set value of power down register for aftr mode */ | |
7d44d2ba | 87 | exynos_sys_powerdown_conf(SYS_AFTR); |
67173ca4 | 88 | |
8dec067d | 89 | __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR); |
67173ca4 ADK |
90 | __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); |
91 | ||
92 | save_cpu_arch_register(); | |
93 | ||
94 | /* Setting Central Sequence Register for power down mode */ | |
95 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
96 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
97 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
98 | ||
99 | cpu_pm_enter(); | |
100 | cpu_suspend(0, idle_finisher); | |
101 | ||
102 | #ifdef CONFIG_SMP | |
a633208f AK |
103 | if (!soc_is_exynos5250()) |
104 | scu_enable(S5P_VA_SCU); | |
67173ca4 ADK |
105 | #endif |
106 | cpu_pm_exit(); | |
107 | ||
108 | restore_cpu_arch_register(); | |
109 | ||
110 | /* | |
111 | * If PMU failed while entering sleep mode, WFI will be | |
112 | * ignored by PMU and then exiting cpu_do_idle(). | |
113 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
114 | * in this situation. | |
115 | */ | |
116 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
117 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
118 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
119 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
120 | } | |
121 | ||
122 | /* Clear wakeup state register */ | |
123 | __raw_writel(0x0, S5P_WAKEUP_STAT); | |
124 | ||
e978aa7d | 125 | return index; |
3d739985 JL |
126 | } |
127 | ||
67173ca4 ADK |
128 | static int exynos4_enter_lowpower(struct cpuidle_device *dev, |
129 | struct cpuidle_driver *drv, | |
130 | int index) | |
131 | { | |
132 | int new_index = index; | |
133 | ||
118f5c1d BZ |
134 | /* AFTR can only be entered when cores other than CPU0 are offline */ |
135 | if (num_online_cpus() > 1 || dev->cpu != 0) | |
67173ca4 ADK |
136 | new_index = drv->safe_state_index; |
137 | ||
138 | if (new_index == 0) | |
06c77b3c | 139 | return arm_cpuidle_simple_enter(dev, drv, new_index); |
67173ca4 ADK |
140 | else |
141 | return exynos4_enter_core0_aftr(dev, drv, new_index); | |
142 | } | |
143 | ||
53af16a1 DL |
144 | static struct cpuidle_driver exynos4_idle_driver = { |
145 | .name = "exynos4_idle", | |
146 | .owner = THIS_MODULE, | |
147 | .states = { | |
148 | [0] = ARM_CPUIDLE_WFI_STATE, | |
149 | [1] = { | |
150 | .enter = exynos4_enter_lowpower, | |
151 | .exit_latency = 300, | |
152 | .target_residency = 100000, | |
153 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
154 | .name = "C1", | |
155 | .desc = "ARM power down", | |
156 | }, | |
157 | }, | |
158 | .state_count = 2, | |
159 | .safe_state_index = 0, | |
160 | }; | |
161 | ||
f612a4fb | 162 | static int exynos_cpuidle_probe(struct platform_device *pdev) |
3d739985 | 163 | { |
5db9f436 | 164 | int cpu_id, ret; |
3d739985 | 165 | struct cpuidle_device *device; |
46bcfad7 | 166 | |
1e9fec0e ADK |
167 | if (soc_is_exynos5440()) |
168 | exynos4_idle_driver.state_count = 1; | |
169 | ||
5db9f436 DL |
170 | ret = cpuidle_register_driver(&exynos4_idle_driver); |
171 | if (ret) { | |
ae7c4c87 | 172 | dev_err(&pdev->dev, "failed to register cpuidle driver\n"); |
5db9f436 | 173 | return ret; |
46bcfad7 | 174 | } |
3d739985 | 175 | |
329afd26 | 176 | for_each_online_cpu(cpu_id) { |
3d739985 JL |
177 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); |
178 | device->cpu = cpu_id; | |
179 | ||
5db9f436 DL |
180 | ret = cpuidle_register_device(device); |
181 | if (ret) { | |
ae7c4c87 | 182 | dev_err(&pdev->dev, "failed to register cpuidle device\n"); |
5db9f436 | 183 | return ret; |
3d739985 JL |
184 | } |
185 | } | |
67173ca4 | 186 | |
3d739985 JL |
187 | return 0; |
188 | } | |
35baa336 BZ |
189 | |
190 | static struct platform_driver exynos_cpuidle_driver = { | |
191 | .probe = exynos_cpuidle_probe, | |
192 | .driver = { | |
193 | .name = "exynos_cpuidle", | |
194 | .owner = THIS_MODULE, | |
195 | }, | |
196 | }; | |
197 | ||
198 | module_platform_driver(exynos_cpuidle_driver); |