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3d739985 JL |
1 | /* linux/arch/arm/mach-exynos4/cpuidle.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/cpuidle.h> | |
67173ca4 | 14 | #include <linux/cpu_pm.h> |
3d739985 | 15 | #include <linux/io.h> |
76ee4557 KP |
16 | #include <linux/export.h> |
17 | #include <linux/time.h> | |
35baa336 | 18 | #include <linux/platform_device.h> |
3d739985 JL |
19 | |
20 | #include <asm/proc-fns.h> | |
67173ca4 ADK |
21 | #include <asm/smp_scu.h> |
22 | #include <asm/suspend.h> | |
23 | #include <asm/unified.h> | |
06c77b3c | 24 | #include <asm/cpuidle.h> |
0f9e0359 | 25 | #include <mach/regs-clock.h> |
67173ca4 | 26 | #include <mach/regs-pmu.h> |
67173ca4 ADK |
27 | |
28 | #include <plat/cpu.h> | |
89693016 | 29 | #include <plat/pm.h> |
67173ca4 | 30 | |
ccd458c1 KK |
31 | #include "common.h" |
32 | ||
67173ca4 ADK |
33 | #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ |
34 | S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
35 | (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) | |
36 | #define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ | |
37 | S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | |
38 | (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) | |
39 | ||
40 | #define S5P_CHECK_AFTR 0xFCBA0D10 | |
3d739985 | 41 | |
67173ca4 ADK |
42 | static int exynos4_enter_lowpower(struct cpuidle_device *dev, |
43 | struct cpuidle_driver *drv, | |
44 | int index); | |
3d739985 | 45 | |
3d739985 JL |
46 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); |
47 | ||
48 | static struct cpuidle_driver exynos4_idle_driver = { | |
06c77b3c ADK |
49 | .name = "exynos4_idle", |
50 | .owner = THIS_MODULE, | |
2eb89f89 DL |
51 | .states = { |
52 | [0] = ARM_CPUIDLE_WFI_STATE, | |
53 | [1] = { | |
54 | .enter = exynos4_enter_lowpower, | |
55 | .exit_latency = 300, | |
56 | .target_residency = 100000, | |
57 | .flags = CPUIDLE_FLAG_TIME_VALID, | |
58 | .name = "C1", | |
59 | .desc = "ARM power down", | |
60 | }, | |
61 | }, | |
62 | .state_count = 2, | |
63 | .safe_state_index = 0, | |
3d739985 JL |
64 | }; |
65 | ||
67173ca4 ADK |
66 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ |
67 | static void exynos4_set_wakeupmask(void) | |
68 | { | |
69 | __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); | |
70 | } | |
71 | ||
72 | static unsigned int g_pwr_ctrl, g_diag_reg; | |
73 | ||
74 | static void save_cpu_arch_register(void) | |
75 | { | |
76 | /*read power control register*/ | |
77 | asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); | |
78 | /*read diagnostic register*/ | |
79 | asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); | |
80 | return; | |
81 | } | |
82 | ||
83 | static void restore_cpu_arch_register(void) | |
84 | { | |
85 | /*write power control register*/ | |
86 | asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); | |
87 | /*write diagnostic register*/ | |
88 | asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); | |
89 | return; | |
90 | } | |
91 | ||
92 | static int idle_finisher(unsigned long flags) | |
93 | { | |
94 | cpu_do_idle(); | |
95 | return 1; | |
96 | } | |
97 | ||
98 | static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, | |
99 | struct cpuidle_driver *drv, | |
100 | int index) | |
101 | { | |
67173ca4 ADK |
102 | unsigned long tmp; |
103 | ||
67173ca4 ADK |
104 | exynos4_set_wakeupmask(); |
105 | ||
106 | /* Set value of power down register for aftr mode */ | |
7d44d2ba | 107 | exynos_sys_powerdown_conf(SYS_AFTR); |
67173ca4 ADK |
108 | |
109 | __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); | |
110 | __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); | |
111 | ||
112 | save_cpu_arch_register(); | |
113 | ||
114 | /* Setting Central Sequence Register for power down mode */ | |
115 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
116 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
117 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
118 | ||
119 | cpu_pm_enter(); | |
120 | cpu_suspend(0, idle_finisher); | |
121 | ||
122 | #ifdef CONFIG_SMP | |
a633208f AK |
123 | if (!soc_is_exynos5250()) |
124 | scu_enable(S5P_VA_SCU); | |
67173ca4 ADK |
125 | #endif |
126 | cpu_pm_exit(); | |
127 | ||
128 | restore_cpu_arch_register(); | |
129 | ||
130 | /* | |
131 | * If PMU failed while entering sleep mode, WFI will be | |
132 | * ignored by PMU and then exiting cpu_do_idle(). | |
133 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
134 | * in this situation. | |
135 | */ | |
136 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
137 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
138 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
139 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
140 | } | |
141 | ||
142 | /* Clear wakeup state register */ | |
143 | __raw_writel(0x0, S5P_WAKEUP_STAT); | |
144 | ||
e978aa7d | 145 | return index; |
3d739985 JL |
146 | } |
147 | ||
67173ca4 ADK |
148 | static int exynos4_enter_lowpower(struct cpuidle_device *dev, |
149 | struct cpuidle_driver *drv, | |
150 | int index) | |
151 | { | |
152 | int new_index = index; | |
153 | ||
154 | /* This mode only can be entered when other core's are offline */ | |
155 | if (num_online_cpus() > 1) | |
156 | new_index = drv->safe_state_index; | |
157 | ||
158 | if (new_index == 0) | |
06c77b3c | 159 | return arm_cpuidle_simple_enter(dev, drv, new_index); |
67173ca4 ADK |
160 | else |
161 | return exynos4_enter_core0_aftr(dev, drv, new_index); | |
162 | } | |
163 | ||
0f9e0359 AK |
164 | static void __init exynos5_core_down_clk(void) |
165 | { | |
166 | unsigned int tmp; | |
167 | ||
168 | /* | |
169 | * Enable arm clock down (in idle) and set arm divider | |
170 | * ratios in WFI/WFE state. | |
171 | */ | |
172 | tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ | |
173 | PWR_CTRL1_CORE1_DOWN_RATIO | \ | |
174 | PWR_CTRL1_DIV2_DOWN_EN | \ | |
175 | PWR_CTRL1_DIV1_DOWN_EN | \ | |
176 | PWR_CTRL1_USE_CORE1_WFE | \ | |
177 | PWR_CTRL1_USE_CORE0_WFE | \ | |
178 | PWR_CTRL1_USE_CORE1_WFI | \ | |
179 | PWR_CTRL1_USE_CORE0_WFI; | |
180 | __raw_writel(tmp, EXYNOS5_PWR_CTRL1); | |
181 | ||
182 | /* | |
183 | * Enable arm clock up (on exiting idle). Set arm divider | |
184 | * ratios when not in idle along with the standby duration | |
185 | * ratios. | |
186 | */ | |
187 | tmp = PWR_CTRL2_DIV2_UP_EN | \ | |
188 | PWR_CTRL2_DIV1_UP_EN | \ | |
189 | PWR_CTRL2_DUR_STANDBY2_VAL | \ | |
190 | PWR_CTRL2_DUR_STANDBY1_VAL | \ | |
191 | PWR_CTRL2_CORE2_UP_RATIO | \ | |
192 | PWR_CTRL2_CORE1_UP_RATIO; | |
193 | __raw_writel(tmp, EXYNOS5_PWR_CTRL2); | |
194 | } | |
195 | ||
f612a4fb | 196 | static int exynos_cpuidle_probe(struct platform_device *pdev) |
3d739985 | 197 | { |
5db9f436 | 198 | int cpu_id, ret; |
3d739985 | 199 | struct cpuidle_device *device; |
46bcfad7 | 200 | |
0f9e0359 AK |
201 | if (soc_is_exynos5250()) |
202 | exynos5_core_down_clk(); | |
203 | ||
1e9fec0e ADK |
204 | if (soc_is_exynos5440()) |
205 | exynos4_idle_driver.state_count = 1; | |
206 | ||
5db9f436 DL |
207 | ret = cpuidle_register_driver(&exynos4_idle_driver); |
208 | if (ret) { | |
ae7c4c87 | 209 | dev_err(&pdev->dev, "failed to register cpuidle driver\n"); |
5db9f436 | 210 | return ret; |
46bcfad7 | 211 | } |
3d739985 | 212 | |
329afd26 | 213 | for_each_online_cpu(cpu_id) { |
3d739985 JL |
214 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); |
215 | device->cpu = cpu_id; | |
216 | ||
2eb89f89 DL |
217 | /* Support IDLE only */ |
218 | if (cpu_id != 0) | |
219 | device->state_count = 1; | |
3d739985 | 220 | |
5db9f436 DL |
221 | ret = cpuidle_register_device(device); |
222 | if (ret) { | |
ae7c4c87 | 223 | dev_err(&pdev->dev, "failed to register cpuidle device\n"); |
5db9f436 | 224 | return ret; |
3d739985 JL |
225 | } |
226 | } | |
67173ca4 | 227 | |
3d739985 JL |
228 | return 0; |
229 | } | |
35baa336 BZ |
230 | |
231 | static struct platform_driver exynos_cpuidle_driver = { | |
232 | .probe = exynos_cpuidle_probe, | |
233 | .driver = { | |
234 | .name = "exynos_cpuidle", | |
235 | .owner = THIS_MODULE, | |
236 | }, | |
237 | }; | |
238 | ||
239 | module_platform_driver(exynos_cpuidle_driver); |