[deliverable/linux.git] / arch / arm / mach-exynos / dma.c

/* linux/arch/arm/mach-exynos4/dma.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
 *	Jaswinder Singh <jassi.brar@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl330.h>
#include <linux/of.h>

#include <asm/irq.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <plat/cpu.h>

#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/dma.h>

static u64 dma_dmamask = DMA_BIT_MASK(32);

static u8 exynos4210_pdma0_peri[] = {
	DMACH_PCM0_RX,
	DMACH_PCM0_TX,
	DMACH_PCM2_RX,
	DMACH_PCM2_TX,
	DMACH_MSM_REQ0,
	DMACH_MSM_REQ2,
	DMACH_SPI0_RX,
	DMACH_SPI0_TX,
	DMACH_SPI2_RX,
	DMACH_SPI2_TX,
	DMACH_I2S0S_TX,
	DMACH_I2S0_RX,
	DMACH_I2S0_TX,
	DMACH_I2S2_RX,
	DMACH_I2S2_TX,
	DMACH_UART0_RX,
	DMACH_UART0_TX,
	DMACH_UART2_RX,
	DMACH_UART2_TX,
	DMACH_UART4_RX,
	DMACH_UART4_TX,
	DMACH_SLIMBUS0_RX,
	DMACH_SLIMBUS0_TX,
	DMACH_SLIMBUS2_RX,
	DMACH_SLIMBUS2_TX,
	DMACH_SLIMBUS4_RX,
	DMACH_SLIMBUS4_TX,
	DMACH_AC97_MICIN,
	DMACH_AC97_PCMIN,
	DMACH_AC97_PCMOUT,
};

static u8 exynos4212_pdma0_peri[] = {
	DMACH_PCM0_RX,
	DMACH_PCM0_TX,
	DMACH_PCM2_RX,
	DMACH_PCM2_TX,
	DMACH_MIPI_HSI0,
	DMACH_MIPI_HSI1,
	DMACH_SPI0_RX,
	DMACH_SPI0_TX,
	DMACH_SPI2_RX,
	DMACH_SPI2_TX,
	DMACH_I2S0S_TX,
	DMACH_I2S0_RX,
	DMACH_I2S0_TX,
	DMACH_I2S2_RX,
	DMACH_I2S2_TX,
	DMACH_UART0_RX,
	DMACH_UART0_TX,
	DMACH_UART2_RX,
	DMACH_UART2_TX,
	DMACH_UART4_RX,
	DMACH_UART4_TX,
	DMACH_SLIMBUS0_RX,
	DMACH_SLIMBUS0_TX,
	DMACH_SLIMBUS2_RX,
	DMACH_SLIMBUS2_TX,
	DMACH_SLIMBUS4_RX,
	DMACH_SLIMBUS4_TX,
	DMACH_AC97_MICIN,
	DMACH_AC97_PCMIN,
	DMACH_AC97_PCMOUT,
	DMACH_MIPI_HSI4,
	DMACH_MIPI_HSI5,
};

struct dma_pl330_platdata exynos4_pdma0_pdata;

static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
	EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);

static u8 exynos4210_pdma1_peri[] = {
	DMACH_PCM0_RX,
	DMACH_PCM0_TX,
	DMACH_PCM1_RX,
	DMACH_PCM1_TX,
	DMACH_MSM_REQ1,
	DMACH_MSM_REQ3,
	DMACH_SPI1_RX,
	DMACH_SPI1_TX,
	DMACH_I2S0S_TX,
	DMACH_I2S0_RX,
	DMACH_I2S0_TX,
	DMACH_I2S1_RX,
	DMACH_I2S1_TX,
	DMACH_UART0_RX,
	DMACH_UART0_TX,
	DMACH_UART1_RX,
	DMACH_UART1_TX,
	DMACH_UART3_RX,
	DMACH_UART3_TX,
	DMACH_SLIMBUS1_RX,
	DMACH_SLIMBUS1_TX,
	DMACH_SLIMBUS3_RX,
	DMACH_SLIMBUS3_TX,
	DMACH_SLIMBUS5_RX,
	DMACH_SLIMBUS5_TX,
};

static u8 exynos4212_pdma1_peri[] = {
	DMACH_PCM0_RX,
	DMACH_PCM0_TX,
	DMACH_PCM1_RX,
	DMACH_PCM1_TX,
	DMACH_MIPI_HSI2,
	DMACH_MIPI_HSI3,
	DMACH_SPI1_RX,
	DMACH_SPI1_TX,
	DMACH_I2S0S_TX,
	DMACH_I2S0_RX,
	DMACH_I2S0_TX,
	DMACH_I2S1_RX,
	DMACH_I2S1_TX,
	DMACH_UART0_RX,
	DMACH_UART0_TX,
	DMACH_UART1_RX,
	DMACH_UART1_TX,
	DMACH_UART3_RX,
	DMACH_UART3_TX,
	DMACH_SLIMBUS1_RX,
	DMACH_SLIMBUS1_TX,
	DMACH_SLIMBUS3_RX,
	DMACH_SLIMBUS3_TX,
	DMACH_SLIMBUS5_RX,
	DMACH_SLIMBUS5_TX,
	DMACH_SLIMBUS0AUX_RX,
	DMACH_SLIMBUS0AUX_TX,
	DMACH_SPDIF,
	DMACH_MIPI_HSI6,
	DMACH_MIPI_HSI7,
};

static struct dma_pl330_platdata exynos4_pdma1_pdata;

static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
	EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);

static u8 mdma_peri[] = {
	DMACH_MTOM_0,
	DMACH_MTOM_1,
	DMACH_MTOM_2,
	DMACH_MTOM_3,
	DMACH_MTOM_4,
	DMACH_MTOM_5,
	DMACH_MTOM_6,
	DMACH_MTOM_7,
};

static struct dma_pl330_platdata exynos4_mdma1_pdata = {
	.nr_valid_peri = ARRAY_SIZE(mdma_peri),
	.peri_id = mdma_peri,
};

static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
	EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);

static int __init exynos4_dma_init(void)
{
	if (of_have_populated_dt())
		return 0;

	if (soc_is_exynos4210()) {
		exynos4_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4210_pdma0_peri);
		exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
		exynos4_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4210_pdma1_peri);
		exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
		exynos4_pdma0_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4212_pdma0_peri);
		exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
		exynos4_pdma1_pdata.nr_valid_peri =
			ARRAY_SIZE(exynos4212_pdma1_peri);
		exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
	}

	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
	amba_device_register(&exynos4_pdma0_device, &iomem_resource);

	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
	amba_device_register(&exynos4_pdma1_device, &iomem_resource);

	dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
	amba_device_register(&exynos4_mdma1_device, &iomem_resource);

	return 0;
}
arch_initcall(exynos4_dma_init);
Commit	Line	Data
7d30e8b3 KK	1	/* linux/arch/arm/mach-exynos4/dma.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
8b0ae0b7 JB	6	* Copyright (C) 2010 Samsung Electronics Co. Ltd.
	7	* Jaswinder Singh <jassi.brar@samsung.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	22	*/
	23
8b0ae0b7	24	#include <linux/dma-mapping.h>
bf856fbb BK	25	#include <linux/amba/bus.h>
bf856fbb BK	26	#include <linux/amba/pl330.h>
fca3de6a	27	#include <linux/of.h>
8b0ae0b7	28
bf856fbb	29	#include <asm/irq.h>
8b0ae0b7 JB	30	#include <plat/devs.h>
8b0ae0b7 JB	31	#include <plat/irqs.h>
efd9960b	32	#include <plat/cpu.h>
8b0ae0b7 JB	33
	34	#include <mach/map.h>
	35	#include <mach/irqs.h>
bf856fbb	36	#include <mach/dma.h>
8b0ae0b7 JB	37
	38	static u64 dma_dmamask = DMA_BIT_MASK(32);
	39
efd9960b	40	static u8 exynos4210_pdma0_peri[] = {
e1cd8454 TA	41	DMACH_PCM0_RX,
	42	DMACH_PCM0_TX,
	43	DMACH_PCM2_RX,
	44	DMACH_PCM2_TX,
	45	DMACH_MSM_REQ0,
	46	DMACH_MSM_REQ2,
	47	DMACH_SPI0_RX,
	48	DMACH_SPI0_TX,
	49	DMACH_SPI2_RX,
	50	DMACH_SPI2_TX,
	51	DMACH_I2S0S_TX,
	52	DMACH_I2S0_RX,
	53	DMACH_I2S0_TX,
	54	DMACH_I2S2_RX,
	55	DMACH_I2S2_TX,
	56	DMACH_UART0_RX,
	57	DMACH_UART0_TX,
	58	DMACH_UART2_RX,
	59	DMACH_UART2_TX,
	60	DMACH_UART4_RX,
	61	DMACH_UART4_TX,
	62	DMACH_SLIMBUS0_RX,
	63	DMACH_SLIMBUS0_TX,
	64	DMACH_SLIMBUS2_RX,
	65	DMACH_SLIMBUS2_TX,
	66	DMACH_SLIMBUS4_RX,
	67	DMACH_SLIMBUS4_TX,
	68	DMACH_AC97_MICIN,
	69	DMACH_AC97_PCMIN,
	70	DMACH_AC97_PCMOUT,
8b0ae0b7 JB	71	};
8b0ae0b7 JB	72
efd9960b BK	73	static u8 exynos4212_pdma0_peri[] = {
	74	DMACH_PCM0_RX,
	75	DMACH_PCM0_TX,
	76	DMACH_PCM2_RX,
	77	DMACH_PCM2_TX,
	78	DMACH_MIPI_HSI0,
	79	DMACH_MIPI_HSI1,
	80	DMACH_SPI0_RX,
	81	DMACH_SPI0_TX,
	82	DMACH_SPI2_RX,
	83	DMACH_SPI2_TX,
	84	DMACH_I2S0S_TX,
	85	DMACH_I2S0_RX,
	86	DMACH_I2S0_TX,
	87	DMACH_I2S2_RX,
	88	DMACH_I2S2_TX,
	89	DMACH_UART0_RX,
	90	DMACH_UART0_TX,
	91	DMACH_UART2_RX,
	92	DMACH_UART2_TX,
	93	DMACH_UART4_RX,
	94	DMACH_UART4_TX,
	95	DMACH_SLIMBUS0_RX,
	96	DMACH_SLIMBUS0_TX,
	97	DMACH_SLIMBUS2_RX,
	98	DMACH_SLIMBUS2_TX,
	99	DMACH_SLIMBUS4_RX,
	100	DMACH_SLIMBUS4_TX,
	101	DMACH_AC97_MICIN,
	102	DMACH_AC97_PCMIN,
	103	DMACH_AC97_PCMOUT,
	104	DMACH_MIPI_HSI4,
	105	DMACH_MIPI_HSI5,
8b0ae0b7 JB	106	};
8b0ae0b7 JB	107
efd9960b BK	108	struct dma_pl330_platdata exynos4_pdma0_pdata;
efd9960b BK	109
60571f98 KK	110	static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
60571f98 KK	111	EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
8b0ae0b7	112
efd9960b	113	static u8 exynos4210_pdma1_peri[] = {
e1cd8454 TA	114	DMACH_PCM0_RX,
	115	DMACH_PCM0_TX,
	116	DMACH_PCM1_RX,
	117	DMACH_PCM1_TX,
	118	DMACH_MSM_REQ1,
	119	DMACH_MSM_REQ3,
	120	DMACH_SPI1_RX,
	121	DMACH_SPI1_TX,
	122	DMACH_I2S0S_TX,
	123	DMACH_I2S0_RX,
	124	DMACH_I2S0_TX,
	125	DMACH_I2S1_RX,
	126	DMACH_I2S1_TX,
	127	DMACH_UART0_RX,
	128	DMACH_UART0_TX,
	129	DMACH_UART1_RX,
	130	DMACH_UART1_TX,
	131	DMACH_UART3_RX,
	132	DMACH_UART3_TX,
	133	DMACH_SLIMBUS1_RX,
	134	DMACH_SLIMBUS1_TX,
	135	DMACH_SLIMBUS3_RX,
	136	DMACH_SLIMBUS3_TX,
	137	DMACH_SLIMBUS5_RX,
	138	DMACH_SLIMBUS5_TX,
8b0ae0b7 JB	139	};
8b0ae0b7 JB	140
efd9960b BK	141	static u8 exynos4212_pdma1_peri[] = {
	142	DMACH_PCM0_RX,
	143	DMACH_PCM0_TX,
	144	DMACH_PCM1_RX,
	145	DMACH_PCM1_TX,
	146	DMACH_MIPI_HSI2,
	147	DMACH_MIPI_HSI3,
	148	DMACH_SPI1_RX,
	149	DMACH_SPI1_TX,
	150	DMACH_I2S0S_TX,
	151	DMACH_I2S0_RX,
	152	DMACH_I2S0_TX,
	153	DMACH_I2S1_RX,
	154	DMACH_I2S1_TX,
	155	DMACH_UART0_RX,
	156	DMACH_UART0_TX,
	157	DMACH_UART1_RX,
	158	DMACH_UART1_TX,
	159	DMACH_UART3_RX,
	160	DMACH_UART3_TX,
	161	DMACH_SLIMBUS1_RX,
	162	DMACH_SLIMBUS1_TX,
	163	DMACH_SLIMBUS3_RX,
	164	DMACH_SLIMBUS3_TX,
	165	DMACH_SLIMBUS5_RX,
	166	DMACH_SLIMBUS5_TX,
	167	DMACH_SLIMBUS0AUX_RX,
	168	DMACH_SLIMBUS0AUX_TX,
	169	DMACH_SPDIF,
	170	DMACH_MIPI_HSI6,
	171	DMACH_MIPI_HSI7,
8b0ae0b7 JB	172	};
8b0ae0b7 JB	173
efd9960b BK	174	static struct dma_pl330_platdata exynos4_pdma1_pdata;
efd9960b BK	175
60571f98 KK	176	static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
60571f98 KK	177	EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
8b0ae0b7	178
9ed76e03 BK	179	static u8 mdma_peri[] = {
	180	DMACH_MTOM_0,
	181	DMACH_MTOM_1,
	182	DMACH_MTOM_2,
	183	DMACH_MTOM_3,
	184	DMACH_MTOM_4,
	185	DMACH_MTOM_5,
	186	DMACH_MTOM_6,
	187	DMACH_MTOM_7,
	188	};
	189
	190	static struct dma_pl330_platdata exynos4_mdma1_pdata = {
	191	.nr_valid_peri = ARRAY_SIZE(mdma_peri),
	192	.peri_id = mdma_peri,
	193	};
	194
	195	static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
	196	EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
	197
7d30e8b3	198	static int __init exynos4_dma_init(void)
8b0ae0b7	199	{
fca3de6a TA	200	if (of_have_populated_dt())
	201	return 0;
	202
efd9960b BK	203	if (soc_is_exynos4210()) {
	204	exynos4_pdma0_pdata.nr_valid_peri =
	205	ARRAY_SIZE(exynos4210_pdma0_peri);
	206	exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
	207	exynos4_pdma1_pdata.nr_valid_peri =
	208	ARRAY_SIZE(exynos4210_pdma1_peri);
	209	exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
	210	} else if (soc_is_exynos4212() \|\| soc_is_exynos4412()) {
	211	exynos4_pdma0_pdata.nr_valid_peri =
	212	ARRAY_SIZE(exynos4212_pdma0_peri);
	213	exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
	214	exynos4_pdma1_pdata.nr_valid_peri =
	215	ARRAY_SIZE(exynos4212_pdma1_peri);
	216	exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
	217	}
	218
e1cd8454 TA	219	dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
e1cd8454 TA	220	dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
75c06963	221	amba_device_register(&exynos4_pdma0_device, &iomem_resource);
e1cd8454 TA	222
	223	dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
	224	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
75c06963	225	amba_device_register(&exynos4_pdma1_device, &iomem_resource);
8b0ae0b7	226
9ed76e03 BK	227	dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
	228	amba_device_register(&exynos4_mdma1_device, &iomem_resource);
	229
8b0ae0b7 JB	230	return 0;
8b0ae0b7 JB	231	}
7d30e8b3	232	arch_initcall(exynos4_dma_init);