[deliverable/linux.git] / arch / arm / mach-exynos / exynos.c

/*
 * SAMSUNG EXYNOS Flattened Device Tree enabled machine
 *
 * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/serial_s3c.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/memory.h>

#include <plat/cpu.h>

#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"

static struct map_desc exynos4_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSTIMER,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COMBINER),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),
		.length		= SZ_128K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length		= SZ_8K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_L2CC,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC0,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_DMC1,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC1),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc0[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4_iodesc1[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4210_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos4x12_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5250_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S5P_VA_SYSRAM_NS,
		.pfn		= __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
};

static struct map_desc exynos5_iodesc[] __initdata = {
	{
		.virtual	= (unsigned long)S3C_VA_SYS,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_TIMER,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SROMC,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_SYSRAM,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_CMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),
		.length		= 144 * SZ_1K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= (unsigned long)S5P_VA_PMU,
		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	},
};

void exynos_restart(enum reboot_mode mode, const char *cmd)
{
	struct device_node *np;
	u32 val = 0x1;
	void __iomem *addr = EXYNOS_SWRESET;

	if (of_machine_is_compatible("samsung,exynos5440")) {
		u32 status;
		np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");

		addr = of_iomap(np, 0) + 0xbc;
		status = __raw_readl(addr);

		addr = of_iomap(np, 0) + 0xcc;
		val = __raw_readl(addr);

		val = (val & 0xffff0000) | (status & 0xffff);
	}

	__raw_writel(val, addr);
}

static struct platform_device exynos_cpuidle = {
	.name		= "exynos_cpuidle",
	.id		= -1,
};

void __init exynos_cpuidle_init(void)
{
	platform_device_register(&exynos_cpuidle);
}

void __init exynos_cpufreq_init(void)
{
	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
}

void __init exynos_init_late(void)
{
	if (of_machine_is_compatible("samsung,exynos5440"))
		/* to be supported later */
		return;

	pm_genpd_poweroff_unused();
	exynos_pm_init();
}

static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
					int depth, void *data)
{
	struct map_desc iodesc;
	__be32 *reg;
	unsigned long len;

	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
		!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
		return 0;

	reg = of_get_flat_dt_prop(node, "reg", &len);
	if (reg == NULL || len != (sizeof(unsigned long) * 2))
		return 0;

	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	iodesc.length = be32_to_cpu(reg[1]) - 1;
	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	iodesc.type = MT_DEVICE;
	iotable_init(&iodesc, 1);
	return 1;
}

/*
 * exynos_map_io
 *
 * register the standard cpu IO areas
 */
static void __init exynos_map_io(void)
{
	if (soc_is_exynos4())
		iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

	if (soc_is_exynos5())
		iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));

	if (soc_is_exynos4210()) {
		if (samsung_rev() == EXYNOS4210_REV_0)
			iotable_init(exynos4_iodesc0,
						ARRAY_SIZE(exynos4_iodesc0));
		else
			iotable_init(exynos4_iodesc1,
						ARRAY_SIZE(exynos4_iodesc1));
		iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	}
	if (soc_is_exynos4212() || soc_is_exynos4412())
		iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
	if (soc_is_exynos5250())
		iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}

void __init exynos_init_io(void)
{
	debug_ll_io_init();

	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);

	/* detect cpu id and rev. */
	s5p_init_cpu(S5P_VA_CHIPID);

	exynos_map_io();
}

struct bus_type exynos_subsys = {
	.name		= "exynos-core",
	.dev_name	= "exynos-core",
};

static int __init exynos_core_init(void)
{
	return subsys_system_register(&exynos_subsys, NULL);
}
core_initcall(exynos_core_init);

static int __init exynos4_l2x0_cache_init(void)
{
	return l2x0_of_init(0x3c400001, 0xc20fffff);
}
early_initcall(exynos4_l2x0_cache_init);

static void __init exynos_dt_machine_init(void)
{
	struct device_node *i2c_np;
	const char *i2c_compat = "samsung,s3c2440-i2c";
	unsigned int tmp;
	int id;

	/*
	 * Exynos5's legacy i2c controller and new high speed i2c
	 * controller have muxed interrupt sources. By default the
	 * interrupts for 4-channel HS-I2C controller are enabled.
	 * If node for first four channels of legacy i2c controller
	 * are available then re-configure the interrupts via the
	 * system register.
	 */
	if (soc_is_exynos5()) {
		for_each_compatible_node(i2c_np, NULL, i2c_compat) {
			if (of_device_is_available(i2c_np)) {
				id = of_alias_get_id(i2c_np, "i2c");
				if (id < 4) {
					tmp = readl(EXYNOS5_SYS_I2C_CFG);
					writel(tmp & ~(0x1 << id),
							EXYNOS5_SYS_I2C_CFG);
				}
			}
		}
	}

	exynos_cpuidle_init();
	exynos_cpufreq_init();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

static char const *exynos_dt_compat[] __initconst = {
	"samsung,exynos4",
	"samsung,exynos4210",
	"samsung,exynos4212",
	"samsung,exynos4412",
	"samsung,exynos5",
	"samsung,exynos5250",
	"samsung,exynos5420",
	"samsung,exynos5440",
	NULL
};

static void __init exynos_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
	int i;
	char *mfc_mem[] = {
		"samsung,mfc-v5",
		"samsung,mfc-v6",
		"samsung,mfc-v7",
	};

	for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
		if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
			break;
#endif
}

DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
	/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	.smp		= smp_ops(exynos_smp_ops),
	.map_io		= exynos_init_io,
	.init_early	= exynos_firmware_init,
	.init_machine	= exynos_dt_machine_init,
	.init_late	= exynos_init_late,
	.dt_compat	= exynos_dt_compat,
	.restart	= exynos_restart,
	.reserve	= exynos_reserve,
MACHINE_END
Commit	Line	Data
cc511b8d	1	/*
cbf08b9e	2	* SAMSUNG EXYNOS Flattened Device Tree enabled machine
cc511b8d	3	*
cbf08b9e SK	4	* Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
cbf08b9e SK	5	* http://www.samsung.com
cc511b8d KK	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
cbf08b9e	12	#include <linux/init.h>
cc511b8d	13	#include <linux/io.h>
cbf08b9e	14	#include <linux/kernel.h>
334a1c70	15	#include <linux/serial_s3c.h>
237c78be	16	#include <linux/of.h>
e873a47c	17	#include <linux/of_address.h>
cbf08b9e SK	18	#include <linux/of_fdt.h>
cbf08b9e SK	19	#include <linux/of_platform.h>
35baa336	20	#include <linux/platform_device.h>
cbf08b9e	21	#include <linux/pm_domain.h>
cc511b8d	22
cbf08b9e	23	#include <asm/cacheflush.h>
cc511b8d	24	#include <asm/hardware/cache-l2x0.h>
cbf08b9e	25	#include <asm/mach/arch.h>
cc511b8d	26	#include <asm/mach/map.h>
cbf08b9e	27	#include <asm/memory.h>
cc511b8d	28
cc511b8d	29	#include <plat/cpu.h>
cc511b8d KK	30
cc511b8d KK	31	#include "common.h"
cbf08b9e	32	#include "mfc.h"
65c9a853 KK	33	#include "regs-pmu.h"
65c9a853 KK	34
94c7ca71 KK	35	static struct map_desc exynos4_iodesc[] __initdata = {
94c7ca71 KK	36	{
cc511b8d KK	37	.virtual = (unsigned long)S3C_VA_SYS,
	38	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
	39	.length = SZ_64K,
	40	.type = MT_DEVICE,
	41	}, {
	42	.virtual = (unsigned long)S3C_VA_TIMER,
	43	.pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
	44	.length = SZ_16K,
	45	.type = MT_DEVICE,
	46	}, {
	47	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	48	.pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
	49	.length = SZ_4K,
	50	.type = MT_DEVICE,
	51	}, {
	52	.virtual = (unsigned long)S5P_VA_SROMC,
	53	.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
	54	.length = SZ_4K,
	55	.type = MT_DEVICE,
	56	}, {
	57	.virtual = (unsigned long)S5P_VA_SYSTIMER,
	58	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
	59	.length = SZ_4K,
	60	.type = MT_DEVICE,
	61	}, {
	62	.virtual = (unsigned long)S5P_VA_PMU,
	63	.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
	64	.length = SZ_64K,
	65	.type = MT_DEVICE,
	66	}, {
	67	.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
	68	.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
	69	.length = SZ_4K,
	70	.type = MT_DEVICE,
	71	}, {
	72	.virtual = (unsigned long)S5P_VA_GIC_CPU,
	73	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
	74	.length = SZ_64K,
	75	.type = MT_DEVICE,
	76	}, {
	77	.virtual = (unsigned long)S5P_VA_GIC_DIST,
	78	.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
	79	.length = SZ_64K,
	80	.type = MT_DEVICE,
94c7ca71	81	}, {
cc511b8d KK	82	.virtual = (unsigned long)S5P_VA_CMU,
	83	.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
	84	.length = SZ_128K,
	85	.type = MT_DEVICE,
	86	}, {
	87	.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
	88	.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
	89	.length = SZ_8K,
	90	.type = MT_DEVICE,
	91	}, {
	92	.virtual = (unsigned long)S5P_VA_L2CC,
	93	.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
	94	.length = SZ_4K,
	95	.type = MT_DEVICE,
cc511b8d KK	96	}, {
	97	.virtual = (unsigned long)S5P_VA_DMC0,
	98	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
2bde0b08 MH	99	.length = SZ_64K,
	100	.type = MT_DEVICE,
	101	}, {
	102	.virtual = (unsigned long)S5P_VA_DMC1,
	103	.pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
	104	.length = SZ_64K,
cc511b8d	105	.type = MT_DEVICE,
cc511b8d KK	106	}, {
	107	.virtual = (unsigned long)S3C_VA_USB_HSPHY,
	108	.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
	109	.length = SZ_4K,
	110	.type = MT_DEVICE,
	111	},
	112	};
	113
	114	static struct map_desc exynos4_iodesc0[] __initdata = {
	115	{
	116	.virtual = (unsigned long)S5P_VA_SYSRAM,
	117	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
	118	.length = SZ_4K,
	119	.type = MT_DEVICE,
	120	},
	121	};
	122
	123	static struct map_desc exynos4_iodesc1[] __initdata = {
	124	{
	125	.virtual = (unsigned long)S5P_VA_SYSRAM,
	126	.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
	127	.length = SZ_4K,
	128	.type = MT_DEVICE,
	129	},
	130	};
	131
41de8986 TF	132	static struct map_desc exynos4210_iodesc[] __initdata = {
	133	{
	134	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	135	.pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
	136	.length = SZ_4K,
	137	.type = MT_DEVICE,
	138	},
	139	};
	140
	141	static struct map_desc exynos4x12_iodesc[] __initdata = {
	142	{
	143	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	144	.pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
	145	.length = SZ_4K,
	146	.type = MT_DEVICE,
	147	},
	148	};
	149
	150	static struct map_desc exynos5250_iodesc[] __initdata = {
	151	{
	152	.virtual = (unsigned long)S5P_VA_SYSRAM_NS,
	153	.pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
	154	.length = SZ_4K,
	155	.type = MT_DEVICE,
	156	},
	157	};
	158
94c7ca71 KK	159	static struct map_desc exynos5_iodesc[] __initdata = {
	160	{
	161	.virtual = (unsigned long)S3C_VA_SYS,
	162	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
	163	.length = SZ_64K,
	164	.type = MT_DEVICE,
	165	}, {
	166	.virtual = (unsigned long)S3C_VA_TIMER,
	167	.pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
	168	.length = SZ_16K,
	169	.type = MT_DEVICE,
	170	}, {
	171	.virtual = (unsigned long)S3C_VA_WATCHDOG,
	172	.pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
	173	.length = SZ_4K,
	174	.type = MT_DEVICE,
	175	}, {
	176	.virtual = (unsigned long)S5P_VA_SROMC,
	177	.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
	178	.length = SZ_4K,
	179	.type = MT_DEVICE,
94c7ca71 KK	180	}, {
	181	.virtual = (unsigned long)S5P_VA_SYSRAM,
	182	.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
	183	.length = SZ_4K,
	184	.type = MT_DEVICE,
	185	}, {
	186	.virtual = (unsigned long)S5P_VA_CMU,
	187	.pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
	188	.length = 144 * SZ_1K,
	189	.type = MT_DEVICE,
	190	}, {
	191	.virtual = (unsigned long)S5P_VA_PMU,
	192	.pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
	193	.length = SZ_64K,
	194	.type = MT_DEVICE,
2edb36c4 KK	195	},
	196	};
	197
cbf08b9e	198	void exynos_restart(enum reboot_mode mode, const char *cmd)
94c7ca71	199	{
60db7e5f	200	struct device_node *np;
cbf08b9e SK	201	u32 val = 0x1;
cbf08b9e SK	202	void __iomem *addr = EXYNOS_SWRESET;
eff4e7c7 CK	203
eff4e7c7 CK	204	if (of_machine_is_compatible("samsung,exynos5440")) {
1ba830c9	205	u32 status;
60db7e5f	206	np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
1ba830c9 JL	207
	208	addr = of_iomap(np, 0) + 0xbc;
	209	status = __raw_readl(addr);
	210
60db7e5f	211	addr = of_iomap(np, 0) + 0xcc;
1ba830c9 JL	212	val = __raw_readl(addr);
	213
	214	val = (val & 0xffff0000) \| (status & 0xffff);
2edb36c4 KK	215	}
	216
	217	__raw_writel(val, addr);
94c7ca71 KK	218	}
94c7ca71 KK	219
35baa336 BZ	220	static struct platform_device exynos_cpuidle = {
	221	.name = "exynos_cpuidle",
	222	.id = -1,
	223	};
	224
	225	void __init exynos_cpuidle_init(void)
	226	{
	227	platform_device_register(&exynos_cpuidle);
	228	}
	229
d568b6f7 LM	230	void __init exynos_cpufreq_init(void)
	231	{
	232	platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
	233	}
	234
bb13fabc SG	235	void __init exynos_init_late(void)
bb13fabc SG	236	{
2edb36c4 KK	237	if (of_machine_is_compatible("samsung,exynos5440"))
	238	/* to be supported later */
	239	return;
	240
1fd3cbcc	241	pm_genpd_poweroff_unused();
559ba237	242	exynos_pm_init();
bb13fabc SG	243	}
bb13fabc SG	244
564d06b1	245	static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
f5f83c71 TA	246	int depth, void *data)
	247	{
	248	struct map_desc iodesc;
	249	__be32 *reg;
	250	unsigned long len;
	251
	252	if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
	253	!of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
	254	return 0;
	255
	256	reg = of_get_flat_dt_prop(node, "reg", &len);
	257	if (reg == NULL \|\| len != (sizeof(unsigned long) * 2))
	258	return 0;
	259
	260	iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
	261	iodesc.length = be32_to_cpu(reg[1]) - 1;
	262	iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
	263	iodesc.type = MT_DEVICE;
	264	iotable_init(&iodesc, 1);
	265	return 1;
	266	}
f5f83c71	267
cc511b8d KK	268	/*
	269	* exynos_map_io
	270	*
	271	* register the standard cpu IO areas
	272	*/
6eb84669 SK	273	static void __init exynos_map_io(void)
6eb84669 SK	274	{
cbf08b9e	275	if (soc_is_exynos4())
6eb84669 SK	276	iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
6eb84669 SK	277
cbf08b9e	278	if (soc_is_exynos5())
6eb84669 SK	279	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
	280
	281	if (soc_is_exynos4210()) {
	282	if (samsung_rev() == EXYNOS4210_REV_0)
	283	iotable_init(exynos4_iodesc0,
	284	ARRAY_SIZE(exynos4_iodesc0));
	285	else
	286	iotable_init(exynos4_iodesc1,
	287	ARRAY_SIZE(exynos4_iodesc1));
	288	iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
	289	}
	290	if (soc_is_exynos4212() \|\| soc_is_exynos4412())
	291	iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
	292	if (soc_is_exynos5250())
	293	iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
	294	}
cc511b8d	295
0e2238ec	296	void __init exynos_init_io(void)
cc511b8d	297	{
9c1fcdcc DA	298	debug_ll_io_init();
9c1fcdcc DA	299
04fae596	300	of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
2edb36c4	301
cc511b8d KK	302	/* detect cpu id and rev. */
	303	s5p_init_cpu(S5P_VA_CHIPID);
	304
6eb84669	305	exynos_map_io();
94c7ca71 KK	306	}
94c7ca71 KK	307
9ee6af9c TA	308	struct bus_type exynos_subsys = {
	309	.name = "exynos-core",
	310	.dev_name = "exynos-core",
94c7ca71 KK	311	};
94c7ca71 KK	312
94c7ca71	313	static int __init exynos_core_init(void)
cc511b8d	314	{
9ee6af9c	315	return subsys_system_register(&exynos_subsys, NULL);
cc511b8d	316	}
94c7ca71	317	core_initcall(exynos_core_init);
cc511b8d	318
cc511b8d KK	319	static int __init exynos4_l2x0_cache_init(void)
cc511b8d KK	320	{
25a9ef63	321	return l2x0_of_init(0x3c400001, 0xc20fffff);
cc511b8d	322	}
cc511b8d	323	early_initcall(exynos4_l2x0_cache_init);
cc511b8d	324
cbf08b9e	325	static void __init exynos_dt_machine_init(void)
cc511b8d	326	{
cbf08b9e SK	327	struct device_node *i2c_np;
	328	const char *i2c_compat = "samsung,s3c2440-i2c";
	329	unsigned int tmp;
	330	int id;
	331
	332	/*
	333	* Exynos5's legacy i2c controller and new high speed i2c
	334	* controller have muxed interrupt sources. By default the
	335	* interrupts for 4-channel HS-I2C controller are enabled.
	336	* If node for first four channels of legacy i2c controller
	337	* are available then re-configure the interrupts via the
	338	* system register.
	339	*/
	340	if (soc_is_exynos5()) {
	341	for_each_compatible_node(i2c_np, NULL, i2c_compat) {
	342	if (of_device_is_available(i2c_np)) {
	343	id = of_alias_get_id(i2c_np, "i2c");
	344	if (id < 4) {
	345	tmp = readl(EXYNOS5_SYS_I2C_CFG);
	346	writel(tmp & ~(0x1 << id),
	347	EXYNOS5_SYS_I2C_CFG);
	348	}
	349	}
	350	}
	351	}
94c7ca71	352
cbf08b9e SK	353	exynos_cpuidle_init();
	354	exynos_cpufreq_init();
	355
	356	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
cc511b8d	357	}
cbf08b9e SK	358
cbf08b9e SK	359	static char const *exynos_dt_compat[] __initconst = {
4868123c	360	"samsung,exynos4",
cbf08b9e SK	361	"samsung,exynos4210",
	362	"samsung,exynos4212",
	363	"samsung,exynos4412",
4868123c	364	"samsung,exynos5",
cbf08b9e SK	365	"samsung,exynos5250",
	366	"samsung,exynos5420",
	367	"samsung,exynos5440",
	368	NULL
	369	};
	370
	371	static void __init exynos_reserve(void)
	372	{
	373	#ifdef CONFIG_S5P_DEV_MFC
	374	int i;
	375	char *mfc_mem[] = {
	376	"samsung,mfc-v5",
	377	"samsung,mfc-v6",
	378	"samsung,mfc-v7",
	379	};
	380
	381	for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
	382	if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
	383	break;
	384	#endif
	385	}
	386
	387	DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
	388	/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
	389	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	390	.smp = smp_ops(exynos_smp_ops),
	391	.map_io = exynos_init_io,
	392	.init_early = exynos_firmware_init,
	393	.init_machine = exynos_dt_machine_init,
	394	.init_late = exynos_init_late,
	395	.dt_compat = exynos_dt_compat,
	396	.restart = exynos_restart,
	397	.reserve = exynos_reserve,
	398	MACHINE_END