projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| bb19a751 KK |
1 | /* |
| 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. | |
| c81a24ff | 3 | * http://www.samsung.com |
| 84bbc16c | 4 | * |
| bb19a751 | 5 | * EXYNOS - IRQ definitions |
| 84bbc16c CY |
6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ASM_ARCH_IRQS_H | |
| 13 | #define __ASM_ARCH_IRQS_H __FILE__ | |
| 14 | ||
| 15 | #include <plat/irqs.h> | |
| 16 | ||
| 35fc950b KK |
17 | /* PPI: Private Peripheral Interrupt */ |
| 18 | ||
| bb19a751 | 19 | #define IRQ_PPI(x) (x + 16) |
| 3a062281 | 20 | |
| 35fc950b KK |
21 | /* SPI: Shared Peripheral Interrupt */ |
| 22 | ||
| bb19a751 | 23 | #define IRQ_SPI(x) (x + 32) |
| 1fb3726c | 24 | |
| bb19a751 KK |
25 | /* COMBINER */ |
| 26 | ||
| 27 | #define MAX_IRQ_IN_COMBINER 8 | |
| 28 | #define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128)) | |
| 29 | #define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) | |
| 30 | ||
| 31 | /* For EXYNOS4 and EXYNOS5 */ | |
| 32 | ||
| 33 | #define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) | |
| 34 | ||
| 35 | #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) | |
| 36 | ||
| 37 | /* For EXYNOS4 SoCs */ | |
| 38 | ||
| 39 | #define EXYNOS4_IRQ_EINT0 IRQ_SPI(16) | |
| 40 | #define EXYNOS4_IRQ_EINT1 IRQ_SPI(17) | |
| 41 | #define EXYNOS4_IRQ_EINT2 IRQ_SPI(18) | |
| 42 | #define EXYNOS4_IRQ_EINT3 IRQ_SPI(19) | |
| 43 | #define EXYNOS4_IRQ_EINT4 IRQ_SPI(20) | |
| 44 | #define EXYNOS4_IRQ_EINT5 IRQ_SPI(21) | |
| 45 | #define EXYNOS4_IRQ_EINT6 IRQ_SPI(22) | |
| 46 | #define EXYNOS4_IRQ_EINT7 IRQ_SPI(23) | |
| 47 | #define EXYNOS4_IRQ_EINT8 IRQ_SPI(24) | |
| 48 | #define EXYNOS4_IRQ_EINT9 IRQ_SPI(25) | |
| 49 | #define EXYNOS4_IRQ_EINT10 IRQ_SPI(26) | |
| 50 | #define EXYNOS4_IRQ_EINT11 IRQ_SPI(27) | |
| 51 | #define EXYNOS4_IRQ_EINT12 IRQ_SPI(28) | |
| 52 | #define EXYNOS4_IRQ_EINT13 IRQ_SPI(29) | |
| 53 | #define EXYNOS4_IRQ_EINT14 IRQ_SPI(30) | |
| 54 | #define EXYNOS4_IRQ_EINT15 IRQ_SPI(31) | |
| 55 | ||
| 56 | #define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33) | |
| 57 | #define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34) | |
| 58 | #define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35) | |
| 59 | #define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36) | |
| 60 | #define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37) | |
| 61 | #define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38) | |
| 62 | #define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39) | |
| 63 | #define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40) | |
| 64 | #define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41) | |
| 65 | #define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42) | |
| 66 | #define EXYNOS4_IRQ_WDT IRQ_SPI(43) | |
| 67 | #define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44) | |
| 68 | #define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45) | |
| 69 | #define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46) | |
| 70 | #define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47) | |
| 71 | #define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48) | |
| 84bbc16c | 72 | |
| 171c067c KK |
73 | #define EXYNOS4_IRQ_UART0 IRQ_SPI(52) |
| 74 | #define EXYNOS4_IRQ_UART1 IRQ_SPI(53) | |
| 75 | #define EXYNOS4_IRQ_UART2 IRQ_SPI(54) | |
| 76 | #define EXYNOS4_IRQ_UART3 IRQ_SPI(55) | |
| 77 | #define EXYNOS4_IRQ_UART4 IRQ_SPI(56) | |
| bb19a751 KK |
78 | #define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57) |
| 79 | #define EXYNOS4_IRQ_IIC IRQ_SPI(58) | |
| 80 | #define EXYNOS4_IRQ_IIC1 IRQ_SPI(59) | |
| 81 | #define EXYNOS4_IRQ_IIC2 IRQ_SPI(60) | |
| 82 | #define EXYNOS4_IRQ_IIC3 IRQ_SPI(61) | |
| 83 | #define EXYNOS4_IRQ_IIC4 IRQ_SPI(62) | |
| 84 | #define EXYNOS4_IRQ_IIC5 IRQ_SPI(63) | |
| 85 | #define EXYNOS4_IRQ_IIC6 IRQ_SPI(64) | |
| 86 | #define EXYNOS4_IRQ_IIC7 IRQ_SPI(65) | |
| 87 | #define EXYNOS4_IRQ_SPI0 IRQ_SPI(66) | |
| 88 | #define EXYNOS4_IRQ_SPI1 IRQ_SPI(67) | |
| 89 | #define EXYNOS4_IRQ_SPI2 IRQ_SPI(68) | |
| 90 | ||
| 91 | #define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70) | |
| 92 | #define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71) | |
| 93 | #define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72) | |
| 94 | #define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73) | |
| 95 | #define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74) | |
| 96 | #define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75) | |
| 97 | #define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76) | |
| 98 | #define EXYNOS4_IRQ_DWMCI IRQ_SPI(77) | |
| 99 | ||
| 100 | #define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78) | |
| 101 | #define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80) | |
| 102 | ||
| 103 | #define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82) | |
| 104 | #define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83) | |
| 105 | #define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84) | |
| 106 | #define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85) | |
| 107 | #define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86) | |
| 108 | #define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87) | |
| 109 | #define EXYNOS4_IRQ_JPEG IRQ_SPI(88) | |
| 110 | #define EXYNOS4_IRQ_2D IRQ_SPI(89) | |
| 111 | #define EXYNOS4_IRQ_PCIE IRQ_SPI(90) | |
| 112 | ||
| 113 | #define EXYNOS4_IRQ_MIXER IRQ_SPI(91) | |
| 114 | #define EXYNOS4_IRQ_HDMI IRQ_SPI(92) | |
| 115 | #define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93) | |
| 116 | #define EXYNOS4_IRQ_MFC IRQ_SPI(94) | |
| 117 | #define EXYNOS4_IRQ_SDO IRQ_SPI(95) | |
| 118 | ||
| 119 | #define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96) | |
| 120 | #define EXYNOS4_IRQ_I2S0 IRQ_SPI(97) | |
| 121 | #define EXYNOS4_IRQ_I2S1 IRQ_SPI(98) | |
| 122 | #define EXYNOS4_IRQ_I2S2 IRQ_SPI(99) | |
| 123 | #define EXYNOS4_IRQ_AC97 IRQ_SPI(100) | |
| 124 | ||
| 125 | #define EXYNOS4_IRQ_SPDIF IRQ_SPI(104) | |
| 126 | #define EXYNOS4_IRQ_ADC0 IRQ_SPI(105) | |
| 127 | #define EXYNOS4_IRQ_PEN0 IRQ_SPI(106) | |
| 128 | #define EXYNOS4_IRQ_ADC1 IRQ_SPI(107) | |
| 129 | #define EXYNOS4_IRQ_PEN1 IRQ_SPI(108) | |
| 130 | #define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109) | |
| 131 | #define EXYNOS4_IRQ_PMU IRQ_SPI(110) | |
| 132 | #define EXYNOS4_IRQ_GPS IRQ_SPI(111) | |
| 133 | #define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | |
| 134 | #define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113) | |
| 135 | ||
| 136 | #define EXYNOS4_IRQ_TSI IRQ_SPI(115) | |
| 137 | #define EXYNOS4_IRQ_SATA IRQ_SPI(116) | |
| 138 | ||
| 139 | #define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) | |
| 140 | #define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1) | |
| 141 | #define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2) | |
| 142 | #define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3) | |
| 143 | #define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4) | |
| 144 | #define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5) | |
| 145 | #define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6) | |
| 146 | #define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7) | |
| 147 | ||
| 148 | #define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0) | |
| 149 | #define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1) | |
| 150 | #define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2) | |
| 151 | #define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3) | |
| 152 | #define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4) | |
| 153 | #define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5) | |
| 154 | #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) | |
| 155 | #define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) | |
| 156 | ||
| bca10b90 KC |
157 | #define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0) |
| 158 | #define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1) | |
| 159 | #define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2) | |
| 160 | #define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3) | |
| 161 | #define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4) | |
| 162 | #define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5) | |
| 163 | ||
| bb19a751 KK |
164 | #define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0) |
| 165 | #define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) | |
| 166 | #define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) | |
| 167 | ||
| 168 | #define EXYNOS4_MAX_COMBINER_NR 16 | |
| 169 | ||
| 170 | #define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 | |
| 171 | #define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9 | |
| 172 | ||
| 173 | /* | |
| 174 | * For Compatibility: | |
| 175 | * the default is for EXYNOS4, and | |
| 176 | * for exynos5, should be re-mapped at function | |
| 177 | */ | |
| 178 | ||
| 179 | #define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC | |
| 180 | #define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC | |
| 181 | #define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC | |
| 182 | #define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC | |
| 183 | #define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC | |
| 184 | ||
| 185 | #define IRQ_WDT EXYNOS4_IRQ_WDT | |
| 186 | #define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM | |
| 187 | #define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC | |
| 188 | #define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB | |
| 189 | #define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA | |
| 190 | ||
| 191 | #define IRQ_IIC EXYNOS4_IRQ_IIC | |
| 192 | #define IRQ_IIC1 EXYNOS4_IRQ_IIC1 | |
| 193 | #define IRQ_IIC3 EXYNOS4_IRQ_IIC3 | |
| 194 | #define IRQ_IIC5 EXYNOS4_IRQ_IIC5 | |
| 195 | #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 | |
| 196 | #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 | |
| 197 | ||
| d40af365 TA |
198 | #define IRQ_SPI0 EXYNOS4_IRQ_SPI0 |
| 199 | #define IRQ_SPI1 EXYNOS4_IRQ_SPI1 | |
| 200 | #define IRQ_SPI2 EXYNOS4_IRQ_SPI2 | |
| 201 | ||
| bb19a751 | 202 | #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST |
| 8ea2d9e7 | 203 | #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG |
| bb19a751 KK |
204 | |
| 205 | #define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0 | |
| 206 | #define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1 | |
| 207 | #define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2 | |
| 208 | #define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3 | |
| 209 | ||
| 210 | #define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0 | |
| 211 | ||
| 212 | #define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI | |
| 213 | ||
| 214 | #define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0 | |
| 215 | #define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1 | |
| 216 | #define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2 | |
| 217 | #define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3 | |
| 218 | #define IRQ_JPEG EXYNOS4_IRQ_JPEG | |
| 219 | #define IRQ_2D EXYNOS4_IRQ_2D | |
| 220 | ||
| 221 | #define IRQ_MIXER EXYNOS4_IRQ_MIXER | |
| 222 | #define IRQ_HDMI EXYNOS4_IRQ_HDMI | |
| 223 | #define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY | |
| 224 | #define IRQ_MFC EXYNOS4_IRQ_MFC | |
| 225 | #define IRQ_SDO EXYNOS4_IRQ_SDO | |
| 226 | ||
| 0d923490 TB |
227 | #define IRQ_I2S0 EXYNOS4_IRQ_I2S0 |
| 228 | ||
| bb19a751 KK |
229 | #define IRQ_ADC EXYNOS4_IRQ_ADC0 |
| 230 | #define IRQ_TC EXYNOS4_IRQ_PEN0 | |
| 231 | ||
| 232 | #define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD | |
| 233 | #define IRQ_PMU EXYNOS4_IRQ_PMU | |
| 234 | ||
| bb19a751 KK |
235 | #define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO |
| 236 | #define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC | |
| 237 | #define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM | |
| 238 | ||
| 239 | #define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS | |
| 240 | #define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS | |
| 241 | ||
| 242 | /* For EXYNOS5 SoCs */ | |
| 243 | ||
| 244 | #define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33) | |
| 245 | #define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34) | |
| 246 | #define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35) | |
| 247 | #define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36) | |
| 248 | #define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37) | |
| 249 | #define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38) | |
| 250 | #define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39) | |
| 251 | #define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40) | |
| 252 | #define EXYNOS5_IRQ_RTIC IRQ_SPI(41) | |
| 253 | #define EXYNOS5_IRQ_WDT IRQ_SPI(42) | |
| 254 | #define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43) | |
| 255 | #define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44) | |
| 256 | #define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45) | |
| 257 | #define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46) | |
| 258 | #define EXYNOS5_IRQ_GPIO IRQ_SPI(47) | |
| 259 | #define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48) | |
| 260 | #define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49) | |
| 261 | #define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50) | |
| 171c067c KK |
262 | #define EXYNOS5_IRQ_UART0 IRQ_SPI(51) |
| 263 | #define EXYNOS5_IRQ_UART1 IRQ_SPI(52) | |
| 264 | #define EXYNOS5_IRQ_UART2 IRQ_SPI(53) | |
| 265 | #define EXYNOS5_IRQ_UART3 IRQ_SPI(54) | |
| 266 | #define EXYNOS5_IRQ_UART4 IRQ_SPI(55) | |
| bb19a751 KK |
267 | #define EXYNOS5_IRQ_IIC IRQ_SPI(56) |
| 268 | #define EXYNOS5_IRQ_IIC1 IRQ_SPI(57) | |
| 269 | #define EXYNOS5_IRQ_IIC2 IRQ_SPI(58) | |
| 270 | #define EXYNOS5_IRQ_IIC3 IRQ_SPI(59) | |
| 271 | #define EXYNOS5_IRQ_IIC4 IRQ_SPI(60) | |
| 272 | #define EXYNOS5_IRQ_IIC5 IRQ_SPI(61) | |
| 273 | #define EXYNOS5_IRQ_IIC6 IRQ_SPI(62) | |
| 274 | #define EXYNOS5_IRQ_IIC7 IRQ_SPI(63) | |
| 275 | #define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64) | |
| 276 | #define EXYNOS5_IRQ_TMU IRQ_SPI(65) | |
| 277 | #define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66) | |
| 278 | #define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67) | |
| 279 | #define EXYNOS5_IRQ_SPI0 IRQ_SPI(68) | |
| 280 | #define EXYNOS5_IRQ_SPI1 IRQ_SPI(69) | |
| 281 | #define EXYNOS5_IRQ_SPI2 IRQ_SPI(70) | |
| 282 | #define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71) | |
| 283 | #define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72) | |
| 284 | #define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73) | |
| 285 | #define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74) | |
| 286 | #define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75) | |
| 287 | #define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76) | |
| 288 | #define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77) | |
| 289 | #define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78) | |
| 290 | #define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79) | |
| 291 | #define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80) | |
| 292 | #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81) | |
| 293 | #define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82) | |
| 3a08f7f8 | 294 | #define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83) |
| bb19a751 KK |
295 | #define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84) |
| 296 | #define EXYNOS5_IRQ_GSC0 IRQ_SPI(85) | |
| 297 | #define EXYNOS5_IRQ_GSC1 IRQ_SPI(86) | |
| 298 | #define EXYNOS5_IRQ_GSC2 IRQ_SPI(87) | |
| 299 | #define EXYNOS5_IRQ_GSC3 IRQ_SPI(88) | |
| 300 | #define EXYNOS5_IRQ_JPEG IRQ_SPI(89) | |
| 301 | #define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90) | |
| 302 | #define EXYNOS5_IRQ_2D IRQ_SPI(91) | |
| 3a08f7f8 KK |
303 | #define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92) |
| 304 | #define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93) | |
| bb19a751 KK |
305 | #define EXYNOS5_IRQ_MIXER IRQ_SPI(94) |
| 306 | #define EXYNOS5_IRQ_HDMI IRQ_SPI(95) | |
| 307 | #define EXYNOS5_IRQ_MFC IRQ_SPI(96) | |
| 308 | #define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97) | |
| 309 | #define EXYNOS5_IRQ_I2S0 IRQ_SPI(98) | |
| 310 | #define EXYNOS5_IRQ_I2S1 IRQ_SPI(99) | |
| 311 | #define EXYNOS5_IRQ_I2S2 IRQ_SPI(100) | |
| 312 | #define EXYNOS5_IRQ_AC97 IRQ_SPI(101) | |
| 313 | #define EXYNOS5_IRQ_PCM0 IRQ_SPI(102) | |
| 314 | #define EXYNOS5_IRQ_PCM1 IRQ_SPI(103) | |
| 315 | #define EXYNOS5_IRQ_PCM2 IRQ_SPI(104) | |
| 316 | #define EXYNOS5_IRQ_SPDIF IRQ_SPI(105) | |
| 317 | #define EXYNOS5_IRQ_ADC0 IRQ_SPI(106) | |
| 3a08f7f8 | 318 | #define EXYNOS5_IRQ_ADC1 IRQ_SPI(107) |
| bb19a751 KK |
319 | #define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108) |
| 320 | #define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109) | |
| 321 | #define EXYNOS5_IRQ_CAM_C IRQ_SPI(110) | |
| 322 | #define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111) | |
| 323 | #define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112) | |
| 324 | #define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113) | |
| 325 | #define EXYNOS5_IRQ_CEC IRQ_SPI(114) | |
| 326 | #define EXYNOS5_IRQ_SATA IRQ_SPI(115) | |
| bb19a751 | 327 | |
| eeed66e3 CY |
328 | #define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) |
| 329 | #define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) | |
| bb19a751 KK |
330 | #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) |
| 331 | #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) | |
| 332 | #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) | |
| 333 | #define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126) | |
| 334 | #define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127) | |
| 335 | ||
| 336 | #define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2) | |
| bb19a751 KK |
337 | |
| 338 | #define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0) | |
| 339 | #define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1) | |
| 340 | #define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2) | |
| 341 | #define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3) | |
| 342 | #define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4) | |
| 343 | #define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5) | |
| 344 | #define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6) | |
| 345 | #define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7) | |
| 346 | ||
| 3a08f7f8 KK |
347 | #define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0) |
| 348 | #define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1) | |
| bb19a751 KK |
349 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2) |
| 350 | #define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3) | |
| 351 | #define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4) | |
| 352 | #define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5) | |
| 353 | #define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6) | |
| 354 | #define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7) | |
| 355 | ||
| 356 | #define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0) | |
| 357 | #define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1) | |
| 358 | #define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2) | |
| 359 | #define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3) | |
| 360 | ||
| 361 | #define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0) | |
| 362 | #define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1) | |
| 363 | #define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2) | |
| 364 | #define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3) | |
| 365 | #define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4) | |
| 366 | #define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5) | |
| 367 | #define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6) | |
| 368 | #define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7) | |
| 369 | ||
| 370 | #define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0) | |
| 371 | #define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1) | |
| 3a08f7f8 KK |
372 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2) |
| 373 | #define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3) | |
| bb19a751 KK |
374 | #define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4) |
| 375 | #define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5) | |
| 376 | #define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6) | |
| 377 | #define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7) | |
| 378 | ||
| 379 | #define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0) | |
| 380 | #define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1) | |
| 381 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2) | |
| 382 | #define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3) | |
| 383 | #define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4) | |
| 384 | #define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5) | |
| bb19a751 | 385 | |
| 3a08f7f8 KK |
386 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5) |
| 387 | #define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6) | |
| bb19a751 KK |
388 | |
| 389 | #define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4) | |
| 390 | #define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5) | |
| 391 | ||
| 392 | #define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3) | |
| 393 | #define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4) | |
| 394 | #define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5) | |
| 395 | #define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6) | |
| 396 | #define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7) | |
| 397 | ||
| 398 | #define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0) | |
| 399 | #define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1) | |
| 400 | #define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6) | |
| 401 | #define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7) | |
| 402 | ||
| 3a08f7f8 KK |
403 | #define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1) |
| 404 | ||
| 405 | #define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3) | |
| 406 | ||
| bb19a751 KK |
407 | #define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4) |
| 408 | #define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5) | |
| 409 | #define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6) | |
| 410 | ||
| 3a08f7f8 KK |
411 | #define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0) |
| 412 | #define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1) | |
| 413 | #define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3) | |
| 414 | #define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4) | |
| 415 | ||
| 416 | #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) | |
| 417 | ||
| bb19a751 | 418 | #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) |
| bb19a751 KK |
419 | #define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) |
| 420 | #define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) | |
| bb19a751 KK |
421 | |
| 422 | #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) | |
| 423 | #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) | |
| 424 | #define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2) | |
| 425 | #define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5) | |
| 426 | #define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6) | |
| 427 | ||
| 428 | #define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0) | |
| 429 | #define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1) | |
| 430 | ||
| 431 | #define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0) | |
| 432 | #define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1) | |
| 433 | ||
| 434 | #define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0) | |
| 435 | #define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1) | |
| 436 | ||
| 437 | #define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0) | |
| 438 | #define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1) | |
| 439 | ||
| 440 | #define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0) | |
| 441 | #define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1) | |
| 442 | ||
| 443 | #define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0) | |
| 444 | #define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1) | |
| 445 | ||
| 446 | #define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0) | |
| 447 | #define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1) | |
| 448 | ||
| 449 | #define EXYNOS5_MAX_COMBINER_NR 32 | |
| 450 | ||
| f10590c9 | 451 | #define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14 |
| bb19a751 KK |
452 | #define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9 |
| 453 | #define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5 | |
| 454 | #define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1 | |
| 455 | ||
| 456 | #define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \ | |
| 457 | EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR) | |
| 458 | ||
| 459 | #define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0) | |
| 460 | #define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16) | |
| 461 | #define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32) | |
| 462 | #define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) | |
| 463 | #define IRQ_TIMER_BASE (IRQ_GPIO_END + 64) | |
| 464 | ||
| 465 | /* Set the default NR_IRQS */ | |
| 466 | ||
| 467 | #define NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT) | |
| 171c067c | 468 | |
| 35fc950b | 469 | #endif /* __ASM_ARCH_IRQS_H */ |