[deliverable/linux.git] / arch / arm / mach-exynos / mach-armlex4210.c

/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/smsc911x.h>

#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>

#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/sdhci.h>

#include <mach/map.h>

#include "common.h"

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define ARMLEX4210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
				 S3C2410_UCON_RXILEVEL |	\
				 S3C2410_UCON_TXIRQMODE |	\
				 S3C2410_UCON_RXIRQMODE |	\
				 S3C2410_UCON_RXFIFO_TOI |	\
				 S3C2443_UCON_RXERR_IRQEN)

#define ARMLEX4210_ULCON_DEFAULT	S3C2410_LCON_CS8

#define ARMLEX4210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
				 S5PV210_UFCON_TXTRIG4 |	\
				 S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
	[0] = {
		.hwport		= 0,
		.flags		= 0,
		.ucon		= ARMLEX4210_UCON_DEFAULT,
		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
	},
	[1] = {
		.hwport		= 1,
		.flags		= 0,
		.ucon		= ARMLEX4210_UCON_DEFAULT,
		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
	},
	[2] = {
		.hwport		= 2,
		.flags		= 0,
		.ucon		= ARMLEX4210_UCON_DEFAULT,
		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
	},
	[3] = {
		.hwport		= 3,
		.flags		= 0,
		.ucon		= ARMLEX4210_UCON_DEFAULT,
		.ulcon		= ARMLEX4210_ULCON_DEFAULT,
		.ufcon		= ARMLEX4210_UFCON_DEFAULT,
	},
};

static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_PERMANENT,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPX2(5),
	.ext_cd_gpio_invert	= 1,
	.max_width		= 4,
};

static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_PERMANENT,
	.max_width		= 4,
};

static void __init armlex4210_sdhci_init(void)
{
	s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
	s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
	s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
}

static void __init armlex4210_wlan_init(void)
{
	/* enable */
	s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
	s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);

	/* reset */
	s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
	s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);

	/* wakeup */
	s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
	s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
}

static struct resource armlex4210_smsc911x_resources[] = {
	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
	[1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
					| IRQF_TRIGGER_HIGH),
};

static struct smsc911x_platform_config smsc9215_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};

static struct platform_device armlex4210_smsc911x = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(armlex4210_smsc911x_resources),
	.resource	= armlex4210_smsc911x_resources,
	.dev		= {
		.platform_data	= &smsc9215_config,
	},
};

static struct platform_device *armlex4210_devices[] __initdata = {
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc2,
	&s3c_device_hsmmc3,
	&s3c_device_rtc,
	&s3c_device_wdt,
	&armlex4210_smsc911x,
	&exynos4_device_ahci,
};

static void __init armlex4210_smsc911x_init(void)
{
	u32 cs1;

	/* configure nCS1 width to 16 bits */
	cs1 = __raw_readl(S5P_SROM_BW) &
		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
		(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
		S5P_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S5P_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */
	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}

static void __init armlex4210_map_io(void)
{
	exynos_init_io(NULL, 0);
	s3c24xx_init_clocks(24000000);
	s3c24xx_init_uarts(armlex4210_uartcfgs,
			   ARRAY_SIZE(armlex4210_uartcfgs));
}

static void __init armlex4210_machine_init(void)
{
	armlex4210_smsc911x_init();

	armlex4210_sdhci_init();

	armlex4210_wlan_init();

	platform_add_devices(armlex4210_devices,
			     ARRAY_SIZE(armlex4210_devices));
}

MACHINE_START(ARMLEX4210, "ARMLEX4210")
	/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
	.atag_offset	= 0x100,
	.smp		= smp_ops(exynos_smp_ops),
	.init_irq	= exynos4_init_irq,
	.map_io		= armlex4210_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= armlex4210_machine_init,
	.init_late	= exynos_init_late,
	.timer		= &exynos4_timer,
	.restart	= exynos4_restart,
MACHINE_END
Commit	Line	Data
af6ec5a2 AA	1	/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/gpio.h>
	12	#include <linux/io.h>
	13	#include <linux/mmc/host.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/serial_core.h>
	16	#include <linux/smsc911x.h>
	17
	18	#include <asm/mach/arch.h>
4e44d2cb	19	#include <asm/hardware/gic.h>
af6ec5a2 AA	20	#include <asm/mach-types.h>
	21
	22	#include <plat/cpu.h>
	23	#include <plat/devs.h>
af6ec5a2 AA	24	#include <plat/gpio-cfg.h>
	25	#include <plat/regs-serial.h>
	26	#include <plat/regs-srom.h>
	27	#include <plat/sdhci.h>
	28
	29	#include <mach/map.h>
	30
cc511b8d KK	31	#include "common.h"
cc511b8d KK	32
af6ec5a2 AA	33	/* Following are default values for UCON, ULCON and UFCON UART registers */
	34	#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
	35	S3C2410_UCON_RXILEVEL \| \
	36	S3C2410_UCON_TXIRQMODE \| \
	37	S3C2410_UCON_RXIRQMODE \| \
	38	S3C2410_UCON_RXFIFO_TOI \| \
	39	S3C2443_UCON_RXERR_IRQEN)
	40
	41	#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
	42
	43	#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
	44	S5PV210_UFCON_TXTRIG4 \| \
	45	S5PV210_UFCON_RXTRIG4)
	46
	47	static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
	48	[0] = {
	49	.hwport = 0,
	50	.flags = 0,
	51	.ucon = ARMLEX4210_UCON_DEFAULT,
	52	.ulcon = ARMLEX4210_ULCON_DEFAULT,
	53	.ufcon = ARMLEX4210_UFCON_DEFAULT,
	54	},
	55	[1] = {
	56	.hwport = 1,
	57	.flags = 0,
	58	.ucon = ARMLEX4210_UCON_DEFAULT,
	59	.ulcon = ARMLEX4210_ULCON_DEFAULT,
	60	.ufcon = ARMLEX4210_UFCON_DEFAULT,
	61	},
	62	[2] = {
	63	.hwport = 2,
	64	.flags = 0,
	65	.ucon = ARMLEX4210_UCON_DEFAULT,
	66	.ulcon = ARMLEX4210_ULCON_DEFAULT,
	67	.ufcon = ARMLEX4210_UFCON_DEFAULT,
	68	},
	69	[3] = {
	70	.hwport = 3,
	71	.flags = 0,
	72	.ucon = ARMLEX4210_UCON_DEFAULT,
	73	.ulcon = ARMLEX4210_ULCON_DEFAULT,
	74	.ufcon = ARMLEX4210_UFCON_DEFAULT,
	75	},
	76	};
	77
	78	static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
	79	.cd_type = S3C_SDHCI_CD_PERMANENT,
af6ec5a2 AA	80	#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
	81	.max_width = 8,
	82	.host_caps = MMC_CAP_8_BIT_DATA,
	83	#endif
	84	};
	85
	86	static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
	87	.cd_type = S3C_SDHCI_CD_GPIO,
	88	.ext_cd_gpio = EXYNOS4_GPX2(5),
	89	.ext_cd_gpio_invert = 1,
af6ec5a2 AA	90	.max_width = 4,
	91	};
	92
	93	static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
	94	.cd_type = S3C_SDHCI_CD_PERMANENT,
af6ec5a2 AA	95	.max_width = 4,
	96	};
	97
	98	static void __init armlex4210_sdhci_init(void)
	99	{
	100	s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
	101	s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
	102	s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
	103	}
	104
	105	static void __init armlex4210_wlan_init(void)
	106	{
	107	/* enable */
	108	s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
	109	s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
	110
	111	/* reset */
	112	s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
	113	s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
	114
	115	/* wakeup */
	116	s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
	117	s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
	118	}
	119
	120	static struct resource armlex4210_smsc911x_resources[] = {
f9b08c6d TB	121	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
	122	[1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
	123	\| IRQF_TRIGGER_HIGH),
af6ec5a2 AA	124	};
	125
	126	static struct smsc911x_platform_config smsc9215_config = {
	127	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
	128	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	129	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	130	.phy_interface = PHY_INTERFACE_MODE_MII,
	131	.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
	132	};
	133
	134	static struct platform_device armlex4210_smsc911x = {
	135	.name = "smsc911x",
	136	.id = -1,
	137	.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
	138	.resource = armlex4210_smsc911x_resources,
	139	.dev = {
	140	.platform_data = &smsc9215_config,
	141	},
	142	};
	143
	144	static struct platform_device *armlex4210_devices[] __initdata = {
	145	&s3c_device_hsmmc0,
	146	&s3c_device_hsmmc2,
	147	&s3c_device_hsmmc3,
	148	&s3c_device_rtc,
	149	&s3c_device_wdt,
af6ec5a2	150	&armlex4210_smsc911x,
40360217	151	&exynos4_device_ahci,
af6ec5a2 AA	152	};
	153
	154	static void __init armlex4210_smsc911x_init(void)
	155	{
	156	u32 cs1;
	157
	158	/* configure nCS1 width to 16 bits */
	159	cs1 = __raw_readl(S5P_SROM_BW) &
	160	~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	161	cs1 \|= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) \|
	162	(0 << S5P_SROM_BW__WAITENABLE__SHIFT) \|
	163	(1 << S5P_SROM_BW__ADDRMODE__SHIFT) \|
	164	(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
	165	S5P_SROM_BW__NCS1__SHIFT;
	166	__raw_writel(cs1, S5P_SROM_BW);
	167
	168	/* set timing for nCS1 suitable for ethernet chip */
	169	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) \|
	170	(0x9 << S5P_SROM_BCX__TACP__SHIFT) \|
	171	(0xc << S5P_SROM_BCX__TCAH__SHIFT) \|
	172	(0x1 << S5P_SROM_BCX__TCOH__SHIFT) \|
	173	(0x6 << S5P_SROM_BCX__TACC__SHIFT) \|
	174	(0x1 << S5P_SROM_BCX__TCOS__SHIFT) \|
	175	(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
	176	}
	177
	178	static void __init armlex4210_map_io(void)
	179	{
cc511b8d	180	exynos_init_io(NULL, 0);
af6ec5a2 AA	181	s3c24xx_init_clocks(24000000);
	182	s3c24xx_init_uarts(armlex4210_uartcfgs,
	183	ARRAY_SIZE(armlex4210_uartcfgs));
	184	}
	185
	186	static void __init armlex4210_machine_init(void)
	187	{
	188	armlex4210_smsc911x_init();
	189
	190	armlex4210_sdhci_init();
	191
	192	armlex4210_wlan_init();
	193
	194	platform_add_devices(armlex4210_devices,
	195	ARRAY_SIZE(armlex4210_devices));
	196	}
	197
	198	MACHINE_START(ARMLEX4210, "ARMLEX4210")
	199	/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
2be5a4a7	200	.atag_offset = 0x100,
06853ae4	201	.smp = smp_ops(exynos_smp_ops),
af6ec5a2 AA	202	.init_irq = exynos4_init_irq,
af6ec5a2 AA	203	.map_io = armlex4210_map_io,
4e44d2cb	204	.handle_irq = gic_handle_irq,
af6ec5a2	205	.init_machine = armlex4210_machine_init,
bb13fabc	206	.init_late = exynos_init_late,
af6ec5a2	207	.timer = &exynos4_timer,
9eb48595	208	.restart = exynos4_restart,
af6ec5a2	209	MACHINE_END