[deliverable/linux.git] / arch / arm / mach-exynos / mach-smdk4x12.c

/*
 * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/lcd.h>
#include <linux/mfd/max8997.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/pwm_backlight.h>
#include <linux/regulator/machine.h>
#include <linux/serial_core.h>
#include <linux/platform_data/s3c-hsotg.h>

#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>

#include <plat/backlight.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
#include <linux/platform_data/i2c-s3c2410.h>
#include <plat/keypad.h>
#include <plat/mfc.h>
#include <plat/regs-fb.h>
#include <plat/regs-serial.h>
#include <plat/sdhci.h>

#include <mach/map.h>

#include <drm/exynos_drm.h>
#include "common.h"

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDK4X12_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
				 S3C2410_UCON_RXILEVEL |	\
				 S3C2410_UCON_TXIRQMODE |	\
				 S3C2410_UCON_RXIRQMODE |	\
				 S3C2410_UCON_RXFIFO_TOI |	\
				 S3C2443_UCON_RXERR_IRQEN)

#define SMDK4X12_ULCON_DEFAULT	S3C2410_LCON_CS8

#define SMDK4X12_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
				 S5PV210_UFCON_TXTRIG4 |	\
				 S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
	[0] = {
		.hwport		= 0,
		.flags		= 0,
		.ucon		= SMDK4X12_UCON_DEFAULT,
		.ulcon		= SMDK4X12_ULCON_DEFAULT,
		.ufcon		= SMDK4X12_UFCON_DEFAULT,
	},
	[1] = {
		.hwport		= 1,
		.flags		= 0,
		.ucon		= SMDK4X12_UCON_DEFAULT,
		.ulcon		= SMDK4X12_ULCON_DEFAULT,
		.ufcon		= SMDK4X12_UFCON_DEFAULT,
	},
	[2] = {
		.hwport		= 2,
		.flags		= 0,
		.ucon		= SMDK4X12_UCON_DEFAULT,
		.ulcon		= SMDK4X12_ULCON_DEFAULT,
		.ufcon		= SMDK4X12_UFCON_DEFAULT,
	},
	[3] = {
		.hwport		= 3,
		.flags		= 0,
		.ucon		= SMDK4X12_UCON_DEFAULT,
		.ulcon		= SMDK4X12_ULCON_DEFAULT,
		.ufcon		= SMDK4X12_UFCON_DEFAULT,
	},
};

static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
};

static struct regulator_consumer_supply max8997_buck1 =
	REGULATOR_SUPPLY("vdd_arm", NULL);

static struct regulator_consumer_supply max8997_buck2 =
	REGULATOR_SUPPLY("vdd_int", NULL);

static struct regulator_consumer_supply max8997_buck3 =
	REGULATOR_SUPPLY("vdd_g3d", NULL);

static struct regulator_init_data max8997_buck1_data = {
	.constraints	= {
		.name		= "VDD_ARM_SMDK4X12",
		.min_uV		= 925000,
		.max_uV		= 1350000,
		.always_on	= 1,
		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
		.state_mem	= {
			.disabled	= 1,
		},
	},
	.num_consumer_supplies	= 1,
	.consumer_supplies	= &max8997_buck1,
};

static struct regulator_init_data max8997_buck2_data = {
	.constraints	= {
		.name		= "VDD_INT_SMDK4X12",
		.min_uV		= 950000,
		.max_uV		= 1150000,
		.always_on	= 1,
		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
		.state_mem	= {
			.disabled	= 1,
		},
	},
	.num_consumer_supplies	= 1,
	.consumer_supplies	= &max8997_buck2,
};

static struct regulator_init_data max8997_buck3_data = {
	.constraints	= {
		.name		= "VDD_G3D_SMDK4X12",
		.min_uV		= 950000,
		.max_uV		= 1150000,
		.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_STATUS,
		.state_mem	= {
			.disabled	= 1,
		},
	},
	.num_consumer_supplies	= 1,
	.consumer_supplies	= &max8997_buck3,
};

static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
	{ MAX8997_BUCK1, &max8997_buck1_data },
	{ MAX8997_BUCK2, &max8997_buck2_data },
	{ MAX8997_BUCK3, &max8997_buck3_data },
};

static struct max8997_platform_data smdk4x12_max8997_pdata = {
	.num_regulators	= ARRAY_SIZE(smdk4x12_max8997_regulators),
	.regulators	= smdk4x12_max8997_regulators,

	.buck1_voltage[0] = 1100000,	/* 1.1V */
	.buck1_voltage[1] = 1100000,	/* 1.1V */
	.buck1_voltage[2] = 1100000,	/* 1.1V */
	.buck1_voltage[3] = 1100000,	/* 1.1V */
	.buck1_voltage[4] = 1100000,	/* 1.1V */
	.buck1_voltage[5] = 1100000,	/* 1.1V */
	.buck1_voltage[6] = 1000000,	/* 1.0V */
	.buck1_voltage[7] = 950000,	/* 0.95V */

	.buck2_voltage[0] = 1100000,	/* 1.1V */
	.buck2_voltage[1] = 1000000,	/* 1.0V */
	.buck2_voltage[2] = 950000,	/* 0.95V */
	.buck2_voltage[3] = 900000,	/* 0.9V */
	.buck2_voltage[4] = 1100000,	/* 1.1V */
	.buck2_voltage[5] = 1000000,	/* 1.0V */
	.buck2_voltage[6] = 950000,	/* 0.95V */
	.buck2_voltage[7] = 900000,	/* 0.9V */

	.buck5_voltage[0] = 1100000,	/* 1.1V */
	.buck5_voltage[1] = 1100000,	/* 1.1V */
	.buck5_voltage[2] = 1100000,	/* 1.1V */
	.buck5_voltage[3] = 1100000,	/* 1.1V */
	.buck5_voltage[4] = 1100000,	/* 1.1V */
	.buck5_voltage[5] = 1100000,	/* 1.1V */
	.buck5_voltage[6] = 1100000,	/* 1.1V */
	.buck5_voltage[7] = 1100000,	/* 1.1V */
};

static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
	{
		I2C_BOARD_INFO("max8997", 0x66),
		.platform_data	= &smdk4x12_max8997_pdata,
	}
};

static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
	{ I2C_BOARD_INFO("wm8994", 0x1a), }
};

static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
	/* nothing here yet */
};

static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
	/* nothing here yet */
};

static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
	.no = EXYNOS4_GPD0(1),
	.func = S3C_GPIO_SFN(2),
};

static struct platform_pwm_backlight_data smdk4x12_bl_data = {
	.pwm_id = 1,
	.pwm_period_ns  = 1000,
};

static uint32_t smdk4x12_keymap[] __initdata = {
	/* KEY(row, col, keycode) */
	KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
	KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
	KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
	KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
};

static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
	.keymap		= smdk4x12_keymap,
	.keymap_size	= ARRAY_SIZE(smdk4x12_keymap),
};

static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
	.keymap_data	= &smdk4x12_keymap_data,
	.rows		= 3,
	.cols		= 8,
};

#ifdef CONFIG_DRM_EXYNOS
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	.panel	= {
		.timing	= {
			.left_margin	= 8,
			.right_margin	= 8,
			.upper_margin	= 6,
			.lower_margin	= 6,
			.hsync_len	= 6,
			.vsync_len	= 4,
			.xres		= 480,
			.yres		= 800,
		},
	},
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.default_win	= 0,
	.bpp		= 32,
};
#else
static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
	.xres		= 480,
	.yres		= 800,
	.virtual_x	= 480,
	.virtual_y	= 800 * 2,
	.max_bpp	= 32,
	.default_bpp	= 24,
};

static struct fb_videomode smdk4x12_lcd_timing = {
	.left_margin	= 8,
	.right_margin	= 8,
	.upper_margin	= 6,
	.lower_margin	= 6,
	.hsync_len	= 6,
	.vsync_len	= 4,
	.xres		= 480,
	.yres		= 800,
};

static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
	.win[0]		= &smdk4x12_fb_win0,
	.vtiming	= &smdk4x12_lcd_timing,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
};
#endif

/* USB OTG */
static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;

static struct platform_device *smdk4x12_devices[] __initdata = {
	&s3c_device_hsmmc2,
	&s3c_device_hsmmc3,
	&s3c_device_i2c0,
	&s3c_device_i2c1,
	&s3c_device_i2c3,
	&s3c_device_i2c7,
	&s3c_device_rtc,
	&s3c_device_usb_hsotg,
	&s3c_device_wdt,
	&s5p_device_fimc0,
	&s5p_device_fimc1,
	&s5p_device_fimc2,
	&s5p_device_fimc3,
	&s5p_device_fimc_md,
	&s5p_device_fimd0,
	&s5p_device_mfc,
	&s5p_device_mfc_l,
	&s5p_device_mfc_r,
#ifdef CONFIG_DRM_EXYNOS
	&exynos_device_drm,
#endif
	&samsung_device_keypad,
};

static void __init smdk4x12_map_io(void)
{
	exynos_init_io(NULL, 0);
	s3c24xx_init_clocks(clk_xusbxti.rate);
	s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
}

static void __init smdk4x12_reserve(void)
{
	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}

static void __init smdk4x12_machine_init(void)
{
	s3c_i2c0_set_platdata(NULL);
	i2c_register_board_info(0, smdk4x12_i2c_devs0,
				ARRAY_SIZE(smdk4x12_i2c_devs0));

	s3c_i2c1_set_platdata(NULL);
	i2c_register_board_info(1, smdk4x12_i2c_devs1,
				ARRAY_SIZE(smdk4x12_i2c_devs1));

	s3c_i2c3_set_platdata(NULL);
	i2c_register_board_info(3, smdk4x12_i2c_devs3,
				ARRAY_SIZE(smdk4x12_i2c_devs3));

	s3c_i2c7_set_platdata(NULL);
	i2c_register_board_info(7, smdk4x12_i2c_devs7,
				ARRAY_SIZE(smdk4x12_i2c_devs7));

	samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);

	samsung_keypad_set_platdata(&smdk4x12_keypad_data);

	s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
	s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);

	s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);

#ifdef CONFIG_DRM_EXYNOS
	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	exynos4_fimd0_gpio_setup_24bpp();
#else
	s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
#endif

	platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
}

MACHINE_START(SMDK4212, "SMDK4212")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	.atag_offset	= 0x100,
	.smp		= smp_ops(exynos_smp_ops),
	.init_irq	= exynos4_init_irq,
	.map_io		= smdk4x12_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdk4x12_machine_init,
	.timer		= &exynos4_timer,
	.restart	= exynos4_restart,
	.reserve	= &smdk4x12_reserve,
MACHINE_END

MACHINE_START(SMDK4412, "SMDK4412")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
	.atag_offset	= 0x100,
	.smp		= smp_ops(exynos_smp_ops),
	.init_irq	= exynos4_init_irq,
	.map_io		= smdk4x12_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdk4x12_machine_init,
	.init_late	= exynos_init_late,
	.timer		= &exynos4_timer,
	.restart	= exynos4_restart,
	.reserve	= &smdk4x12_reserve,
MACHINE_END
Commit	Line	Data
be4ab361	1	/*
31451afd	2	* linux/arch/arm/mach-exynos4/mach-smdk4x12.c
be4ab361 KK	3	*
	4	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/gpio.h>
	13	#include <linux/i2c.h>
	14	#include <linux/input.h>
	15	#include <linux/io.h>
6bba0caf	16	#include <linux/lcd.h>
be4ab361 KK	17	#include <linux/mfd/max8997.h>
	18	#include <linux/mmc/host.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/pwm_backlight.h>
	21	#include <linux/regulator/machine.h>
	22	#include <linux/serial_core.h>
a17b9855	23	#include <linux/platform_data/s3c-hsotg.h>
be4ab361 KK	24
be4ab361 KK	25	#include <asm/mach/arch.h>
4e44d2cb	26	#include <asm/hardware/gic.h>
be4ab361 KK	27	#include <asm/mach-types.h>
	28
	29	#include <plat/backlight.h>
	30	#include <plat/clock.h>
	31	#include <plat/cpu.h>
	32	#include <plat/devs.h>
6bba0caf	33	#include <plat/fb.h>
be4ab361	34	#include <plat/gpio-cfg.h>
436d42c6	35	#include <linux/platform_data/i2c-s3c2410.h>
be4ab361	36	#include <plat/keypad.h>
691bcb31	37	#include <plat/mfc.h>
6bba0caf	38	#include <plat/regs-fb.h>
be4ab361 KK	39	#include <plat/regs-serial.h>
	40	#include <plat/sdhci.h>
	41
	42	#include <mach/map.h>
	43
b96db04a	44	#include <drm/exynos_drm.h>
cc511b8d KK	45	#include "common.h"
cc511b8d KK	46
be4ab361	47	/* Following are default values for UCON, ULCON and UFCON UART registers */
31451afd	48	#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
be4ab361 KK	49	S3C2410_UCON_RXILEVEL \| \
	50	S3C2410_UCON_TXIRQMODE \| \
	51	S3C2410_UCON_RXIRQMODE \| \
	52	S3C2410_UCON_RXFIFO_TOI \| \
	53	S3C2443_UCON_RXERR_IRQEN)
	54
31451afd	55	#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
be4ab361	56
31451afd	57	#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
be4ab361 KK	58	S5PV210_UFCON_TXTRIG4 \| \
	59	S5PV210_UFCON_RXTRIG4)
	60
31451afd	61	static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
be4ab361 KK	62	[0] = {
	63	.hwport = 0,
	64	.flags = 0,
31451afd CY	65	.ucon = SMDK4X12_UCON_DEFAULT,
	66	.ulcon = SMDK4X12_ULCON_DEFAULT,
	67	.ufcon = SMDK4X12_UFCON_DEFAULT,
be4ab361 KK	68	},
	69	[1] = {
	70	.hwport = 1,
	71	.flags = 0,
31451afd CY	72	.ucon = SMDK4X12_UCON_DEFAULT,
	73	.ulcon = SMDK4X12_ULCON_DEFAULT,
	74	.ufcon = SMDK4X12_UFCON_DEFAULT,
be4ab361 KK	75	},
	76	[2] = {
	77	.hwport = 2,
	78	.flags = 0,
31451afd CY	79	.ucon = SMDK4X12_UCON_DEFAULT,
	80	.ulcon = SMDK4X12_ULCON_DEFAULT,
	81	.ufcon = SMDK4X12_UFCON_DEFAULT,
be4ab361 KK	82	},
	83	[3] = {
	84	.hwport = 3,
	85	.flags = 0,
31451afd CY	86	.ucon = SMDK4X12_UCON_DEFAULT,
	87	.ulcon = SMDK4X12_ULCON_DEFAULT,
	88	.ufcon = SMDK4X12_UFCON_DEFAULT,
be4ab361 KK	89	},
	90	};
	91
31451afd	92	static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
be4ab361	93	.cd_type = S3C_SDHCI_CD_INTERNAL,
be4ab361 KK	94	#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
	95	.max_width = 8,
	96	.host_caps = MMC_CAP_8_BIT_DATA,
	97	#endif
	98	};
	99
31451afd	100	static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
be4ab361	101	.cd_type = S3C_SDHCI_CD_INTERNAL,
be4ab361 KK	102	};
	103
	104	static struct regulator_consumer_supply max8997_buck1 =
	105	REGULATOR_SUPPLY("vdd_arm", NULL);
	106
	107	static struct regulator_consumer_supply max8997_buck2 =
	108	REGULATOR_SUPPLY("vdd_int", NULL);
	109
	110	static struct regulator_consumer_supply max8997_buck3 =
	111	REGULATOR_SUPPLY("vdd_g3d", NULL);
	112
	113	static struct regulator_init_data max8997_buck1_data = {
	114	.constraints = {
31451afd	115	.name = "VDD_ARM_SMDK4X12",
be4ab361 KK	116	.min_uV = 925000,
	117	.max_uV = 1350000,
	118	.always_on = 1,
	119	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	120	.state_mem = {
	121	.disabled = 1,
	122	},
	123	},
	124	.num_consumer_supplies = 1,
	125	.consumer_supplies = &max8997_buck1,
	126	};
	127
	128	static struct regulator_init_data max8997_buck2_data = {
	129	.constraints = {
31451afd	130	.name = "VDD_INT_SMDK4X12",
be4ab361 KK	131	.min_uV = 950000,
	132	.max_uV = 1150000,
	133	.always_on = 1,
	134	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
	135	.state_mem = {
	136	.disabled = 1,
	137	},
	138	},
	139	.num_consumer_supplies = 1,
	140	.consumer_supplies = &max8997_buck2,
	141	};
	142
	143	static struct regulator_init_data max8997_buck3_data = {
	144	.constraints = {
31451afd	145	.name = "VDD_G3D_SMDK4X12",
be4ab361 KK	146	.min_uV = 950000,
	147	.max_uV = 1150000,
	148	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	149	REGULATOR_CHANGE_STATUS,
	150	.state_mem = {
	151	.disabled = 1,
	152	},
	153	},
	154	.num_consumer_supplies = 1,
	155	.consumer_supplies = &max8997_buck3,
	156	};
	157
31451afd	158	static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
be4ab361 KK	159	{ MAX8997_BUCK1, &max8997_buck1_data },
	160	{ MAX8997_BUCK2, &max8997_buck2_data },
	161	{ MAX8997_BUCK3, &max8997_buck3_data },
	162	};
	163
31451afd CY	164	static struct max8997_platform_data smdk4x12_max8997_pdata = {
	165	.num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
	166	.regulators = smdk4x12_max8997_regulators,
be4ab361 KK	167
	168	.buck1_voltage[0] = 1100000, /* 1.1V */
	169	.buck1_voltage[1] = 1100000, /* 1.1V */
	170	.buck1_voltage[2] = 1100000, /* 1.1V */
	171	.buck1_voltage[3] = 1100000, /* 1.1V */
	172	.buck1_voltage[4] = 1100000, /* 1.1V */
	173	.buck1_voltage[5] = 1100000, /* 1.1V */
	174	.buck1_voltage[6] = 1000000, /* 1.0V */
	175	.buck1_voltage[7] = 950000, /* 0.95V */
	176
	177	.buck2_voltage[0] = 1100000, /* 1.1V */
	178	.buck2_voltage[1] = 1000000, /* 1.0V */
	179	.buck2_voltage[2] = 950000, /* 0.95V */
	180	.buck2_voltage[3] = 900000, /* 0.9V */
	181	.buck2_voltage[4] = 1100000, /* 1.1V */
	182	.buck2_voltage[5] = 1000000, /* 1.0V */
	183	.buck2_voltage[6] = 950000, /* 0.95V */
	184	.buck2_voltage[7] = 900000, /* 0.9V */
	185
	186	.buck5_voltage[0] = 1100000, /* 1.1V */
	187	.buck5_voltage[1] = 1100000, /* 1.1V */
	188	.buck5_voltage[2] = 1100000, /* 1.1V */
	189	.buck5_voltage[3] = 1100000, /* 1.1V */
	190	.buck5_voltage[4] = 1100000, /* 1.1V */
	191	.buck5_voltage[5] = 1100000, /* 1.1V */
	192	.buck5_voltage[6] = 1100000, /* 1.1V */
	193	.buck5_voltage[7] = 1100000, /* 1.1V */
	194	};
	195
31451afd	196	static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
be4ab361 KK	197	{
be4ab361 KK	198	I2C_BOARD_INFO("max8997", 0x66),
31451afd	199	.platform_data = &smdk4x12_max8997_pdata,
be4ab361 KK	200	}
	201	};
	202
31451afd	203	static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
be4ab361 KK	204	{ I2C_BOARD_INFO("wm8994", 0x1a), }
	205	};
	206
31451afd	207	static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
be4ab361 KK	208	/* nothing here yet */
	209	};
	210
31451afd	211	static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
be4ab361 KK	212	/* nothing here yet */
	213	};
	214
31451afd	215	static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
be4ab361 KK	216	.no = EXYNOS4_GPD0(1),
	217	.func = S3C_GPIO_SFN(2),
	218	};
	219
31451afd	220	static struct platform_pwm_backlight_data smdk4x12_bl_data = {
be4ab361 KK	221	.pwm_id = 1,
	222	.pwm_period_ns = 1000,
	223	};
	224
31451afd	225	static uint32_t smdk4x12_keymap[] __initdata = {
be4ab361	226	/* KEY(row, col, keycode) */
33fe1a49 SK	227	KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
	228	KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
	229	KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
	230	KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
be4ab361 KK	231	};
be4ab361 KK	232
31451afd CY	233	static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
	234	.keymap = smdk4x12_keymap,
	235	.keymap_size = ARRAY_SIZE(smdk4x12_keymap),
be4ab361 KK	236	};
be4ab361 KK	237
31451afd CY	238	static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
31451afd CY	239	.keymap_data = &smdk4x12_keymap_data,
33fe1a49 SK	240	.rows = 3,
33fe1a49 SK	241	.cols = 8,
be4ab361 KK	242	};
be4ab361 KK	243
b96db04a SK	244	#ifdef CONFIG_DRM_EXYNOS
	245	static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	246	.panel = {
	247	.timing = {
	248	.left_margin = 8,
	249	.right_margin = 8,
	250	.upper_margin = 6,
	251	.lower_margin = 6,
	252	.hsync_len = 6,
	253	.vsync_len = 4,
	254	.xres = 480,
	255	.yres = 800,
	256	},
	257	},
	258	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	259	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	260	.default_win = 0,
	261	.bpp = 32,
	262	};
	263	#else
6bba0caf SK	264	static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
	265	.xres = 480,
	266	.yres = 800,
	267	.virtual_x = 480,
	268	.virtual_y = 800 * 2,
	269	.max_bpp = 32,
	270	.default_bpp = 24,
	271	};
	272
	273	static struct fb_videomode smdk4x12_lcd_timing = {
	274	.left_margin = 8,
	275	.right_margin = 8,
	276	.upper_margin = 6,
	277	.lower_margin = 6,
	278	.hsync_len = 6,
	279	.vsync_len = 4,
	280	.xres = 480,
	281	.yres = 800,
	282	};
	283
	284	static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
	285	.win[0] = &smdk4x12_fb_win0,
	286	.vtiming = &smdk4x12_lcd_timing,
	287	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	288	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	289	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
	290	};
b96db04a	291	#endif
6bba0caf	292
a17b9855 SK	293	/* USB OTG */
	294	static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
	295
31451afd	296	static struct platform_device *smdk4x12_devices[] __initdata = {
be4ab361 KK	297	&s3c_device_hsmmc2,
	298	&s3c_device_hsmmc3,
	299	&s3c_device_i2c0,
	300	&s3c_device_i2c1,
	301	&s3c_device_i2c3,
	302	&s3c_device_i2c7,
	303	&s3c_device_rtc,
a17b9855	304	&s3c_device_usb_hsotg,
be4ab361	305	&s3c_device_wdt,
8e84e7d5 SK	306	&s5p_device_fimc0,
	307	&s5p_device_fimc1,
	308	&s5p_device_fimc2,
	309	&s5p_device_fimc3,
	310	&s5p_device_fimc_md,
6bba0caf	311	&s5p_device_fimd0,
691bcb31 SK	312	&s5p_device_mfc,
	313	&s5p_device_mfc_l,
	314	&s5p_device_mfc_r,
b96db04a SK	315	#ifdef CONFIG_DRM_EXYNOS
	316	&exynos_device_drm,
	317	#endif
be4ab361 KK	318	&samsung_device_keypad,
	319	};
	320
31451afd	321	static void __init smdk4x12_map_io(void)
be4ab361	322	{
cc511b8d	323	exynos_init_io(NULL, 0);
be4ab361	324	s3c24xx_init_clocks(clk_xusbxti.rate);
31451afd	325	s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
be4ab361 KK	326	}
be4ab361 KK	327
691bcb31 SK	328	static void __init smdk4x12_reserve(void)
	329	{
	330	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
	331	}
	332
31451afd	333	static void __init smdk4x12_machine_init(void)
be4ab361 KK	334	{
be4ab361 KK	335	s3c_i2c0_set_platdata(NULL);
31451afd CY	336	i2c_register_board_info(0, smdk4x12_i2c_devs0,
31451afd CY	337	ARRAY_SIZE(smdk4x12_i2c_devs0));
be4ab361 KK	338
be4ab361 KK	339	s3c_i2c1_set_platdata(NULL);
31451afd CY	340	i2c_register_board_info(1, smdk4x12_i2c_devs1,
31451afd CY	341	ARRAY_SIZE(smdk4x12_i2c_devs1));
be4ab361 KK	342
be4ab361 KK	343	s3c_i2c3_set_platdata(NULL);
31451afd CY	344	i2c_register_board_info(3, smdk4x12_i2c_devs3,
31451afd CY	345	ARRAY_SIZE(smdk4x12_i2c_devs3));
be4ab361 KK	346
be4ab361 KK	347	s3c_i2c7_set_platdata(NULL);
31451afd CY	348	i2c_register_board_info(7, smdk4x12_i2c_devs7,
31451afd CY	349	ARRAY_SIZE(smdk4x12_i2c_devs7));
be4ab361	350
31451afd	351	samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
be4ab361	352
31451afd	353	samsung_keypad_set_platdata(&smdk4x12_keypad_data);
be4ab361	354
31451afd CY	355	s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
31451afd CY	356	s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
be4ab361	357
a17b9855 SK	358	s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
a17b9855 SK	359
b96db04a SK	360	#ifdef CONFIG_DRM_EXYNOS
	361	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	362	exynos4_fimd0_gpio_setup_24bpp();
	363	#else
6bba0caf	364	s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
b96db04a	365	#endif
6bba0caf	366
31451afd	367	platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
be4ab361 KK	368	}
	369
	370	MACHINE_START(SMDK4212, "SMDK4212")
	371	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
31451afd	372	.atag_offset = 0x100,
06853ae4	373	.smp = smp_ops(exynos_smp_ops),
be4ab361	374	.init_irq = exynos4_init_irq,
31451afd	375	.map_io = smdk4x12_map_io,
4e44d2cb	376	.handle_irq = gic_handle_irq,
31451afd CY	377	.init_machine = smdk4x12_machine_init,
31451afd CY	378	.timer = &exynos4_timer,
9eb48595	379	.restart = exynos4_restart,
691bcb31	380	.reserve = &smdk4x12_reserve,
31451afd CY	381	MACHINE_END
	382
	383	MACHINE_START(SMDK4412, "SMDK4412")
	384	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	385	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
	386	.atag_offset = 0x100,
06853ae4	387	.smp = smp_ops(exynos_smp_ops),
31451afd CY	388	.init_irq = exynos4_init_irq,
31451afd CY	389	.map_io = smdk4x12_map_io,
4e44d2cb	390	.handle_irq = gic_handle_irq,
31451afd	391	.init_machine = smdk4x12_machine_init,
bb13fabc	392	.init_late = exynos_init_late,
be4ab361	393	.timer = &exynos4_timer,
9eb48595	394	.restart = exynos4_restart,
691bcb31	395	.reserve = &smdk4x12_reserve,
be4ab361	396	MACHINE_END