[deliverable/linux.git] / arch / arm / mach-exynos / mach-smdkv310.c

/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/pwm_backlight.h>

#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>

#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/keypad.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/gpio-cfg.h>
#include <plat/backlight.h>
#include <plat/mfc.h>
#include <plat/ehci.h>
#include <plat/clock.h>

#include <mach/map.h>
#include <mach/ohci.h>

#include <drm/exynos_drm.h>
#include "common.h"

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
				 S3C2410_UCON_RXILEVEL |	\
				 S3C2410_UCON_TXIRQMODE |	\
				 S3C2410_UCON_RXIRQMODE |	\
				 S3C2410_UCON_RXFIFO_TOI |	\
				 S3C2443_UCON_RXERR_IRQEN)

#define SMDKV310_ULCON_DEFAULT	S3C2410_LCON_CS8

#define SMDKV310_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
				 S5PV210_UFCON_TXTRIG4 |	\
				 S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
	[0] = {
		.hwport		= 0,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[1] = {
		.hwport		= 1,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[2] = {
		.hwport		= 2,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[3] = {
		.hwport		= 3,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
};

static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK0(2),
	.ext_cd_gpio_invert	= 1,
};

static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK2(2),
	.ext_cd_gpio_invert	= 1,
};

static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
		gpio_free(EXYNOS4_GPD0(1));
#endif
		/* fire nRESET on power up */
		gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
		mdelay(100);

		gpio_set_value(EXYNOS4_GPX0(6), 0);
		mdelay(10);

		gpio_set_value(EXYNOS4_GPX0(6), 1);
		mdelay(10);

		gpio_free(EXYNOS4_GPX0(6));
	} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
		gpio_free(EXYNOS4_GPD0(1));
#endif
	}
}

static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
	.set_power		= lcd_lte480wv_set_power,
};

static struct platform_device smdkv310_lcd_lte480wv = {
	.name			= "platform-lcd",
	.dev.parent		= &s5p_device_fimd0.dev,
	.dev.platform_data	= &smdkv310_lcd_lte480wv_data,
};

#ifdef CONFIG_DRM_EXYNOS
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	.panel	= {
		.timing	= {
			.left_margin	= 13,
			.right_margin	= 8,
			.upper_margin	= 7,
			.lower_margin	= 5,
			.hsync_len	= 3,
			.vsync_len	= 1,
			.xres		= 800,
			.yres		= 480,
		},
	},
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.default_win	= 0,
	.bpp		= 32,
};
#else
static struct s3c_fb_pd_win smdkv310_fb_win0 = {
	.max_bpp	= 32,
	.default_bpp	= 24,
	.xres		= 800,
	.yres		= 480,
};

static struct fb_videomode smdkv310_lcd_timing = {
	.left_margin	= 13,
	.right_margin	= 8,
	.upper_margin	= 7,
	.lower_margin	= 5,
	.hsync_len	= 3,
	.vsync_len	= 1,
	.xres		= 800,
	.yres		= 480,
};

static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
	.win[0]		= &smdkv310_fb_win0,
	.vtiming	= &smdkv310_lcd_timing,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
};
#endif

static struct resource smdkv310_smsc911x_resources[] = {
	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
	[1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
						| IRQF_TRIGGER_LOW),
};

static struct smsc911x_platform_config smsc9215_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};

static struct platform_device smdkv310_smsc911x = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smdkv310_smsc911x_resources),
	.resource	= smdkv310_smsc911x_resources,
	.dev		= {
		.platform_data	= &smsc9215_config,
	},
};

static uint32_t smdkv310_keymap[] __initdata = {
	/* KEY(row, col, keycode) */
	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
};

static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
	.keymap		= smdkv310_keymap,
	.keymap_size	= ARRAY_SIZE(smdkv310_keymap),
};

static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
	.keymap_data	= &smdkv310_keymap_data,
	.rows		= 2,
	.cols		= 8,
};

static struct i2c_board_info i2c_devs1[] __initdata = {
	{I2C_BOARD_INFO("wm8994", 0x1a),},
};

/* USB EHCI */
static struct s5p_ehci_platdata smdkv310_ehci_pdata;

static void __init smdkv310_ehci_init(void)
{
	struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;

	s5p_ehci_set_platdata(pdata);
}

/* USB OHCI */
static struct exynos4_ohci_platdata smdkv310_ohci_pdata;

static void __init smdkv310_ohci_init(void)
{
	struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;

	exynos4_ohci_set_platdata(pdata);
}

static struct platform_device *smdkv310_devices[] __initdata = {
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_hsmmc2,
	&s3c_device_hsmmc3,
	&s3c_device_i2c1,
	&s5p_device_i2c_hdmiphy,
	&s3c_device_rtc,
	&s3c_device_wdt,
	&s5p_device_ehci,
	&s5p_device_fimc0,
	&s5p_device_fimc1,
	&s5p_device_fimc2,
	&s5p_device_fimc3,
	&s5p_device_fimc_md,
	&s5p_device_g2d,
	&s5p_device_jpeg,
#ifdef CONFIG_DRM_EXYNOS
	&exynos_device_drm,
#endif
	&exynos4_device_ac97,
	&exynos4_device_i2s0,
	&exynos4_device_ohci,
	&samsung_device_keypad,
	&s5p_device_mfc,
	&s5p_device_mfc_l,
	&s5p_device_mfc_r,
	&exynos4_device_spdif,
	&samsung_asoc_dma,
	&samsung_asoc_idma,
	&s5p_device_fimd0,
	&smdkv310_lcd_lte480wv,
	&smdkv310_smsc911x,
	&exynos4_device_ahci,
	&s5p_device_hdmi,
	&s5p_device_mixer,
};

static void __init smdkv310_smsc911x_init(void)
{
	u32 cs1;

	/* configure nCS1 width to 16 bits */
	cs1 = __raw_readl(S5P_SROM_BW) &
		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
		S5P_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S5P_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */
	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}

/* LCD Backlight data */
static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
	.no = EXYNOS4_GPD0(1),
	.func = S3C_GPIO_SFN(2),
};

static struct platform_pwm_backlight_data smdkv310_bl_data = {
	.pwm_id = 1,
	.pwm_period_ns  = 1000,
};

static void s5p_tv_setup(void)
{
	/* direct HPD to HDMI chip */
	WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
	s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
	s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
}

static void __init smdkv310_map_io(void)
{
	exynos_init_io(NULL, 0);
	s3c24xx_init_clocks(24000000);
	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}

static void __init smdkv310_reserve(void)
{
	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}

static void __init smdkv310_machine_init(void)
{
	s3c_i2c1_set_platdata(NULL);
	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

	smdkv310_smsc911x_init();

	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);

	s5p_tv_setup();
	s5p_i2c_hdmiphy_set_platdata(NULL);

	samsung_keypad_set_platdata(&smdkv310_keypad_data);

	samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
#ifdef CONFIG_DRM_EXYNOS
	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	exynos4_fimd0_gpio_setup_24bpp();
#else
	s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
#endif

	smdkv310_ehci_init();
	smdkv310_ohci_init();
	clk_xusbxti.rate = 24000000;

	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
}

MACHINE_START(SMDKV310, "SMDKV310")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
	.atag_offset	= 0x100,
	.init_irq	= exynos4_init_irq,
	.map_io		= smdkv310_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdkv310_machine_init,
	.timer		= &exynos4_timer,
	.reserve	= &smdkv310_reserve,
	.restart	= exynos4_restart,
MACHINE_END

MACHINE_START(SMDKC210, "SMDKC210")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	.atag_offset	= 0x100,
	.init_irq	= exynos4_init_irq,
	.map_io		= smdkv310_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdkv310_machine_init,
	.init_late	= exynos_init_late,
	.timer		= &exynos4_timer,
	.restart	= exynos4_restart,
MACHINE_END
Commit	Line	Data
d11135ca	1	/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
b1d69cc6	2	*
d11135ca KK	3	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
d11135ca KK	4	* http://www.samsung.com
b1d69cc6 CY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/serial_core.h>
42c0d26d	12	#include <linux/delay.h>
2b11148a	13	#include <linux/gpio.h>
42c0d26d	14	#include <linux/lcd.h>
2b11148a HL	15	#include <linux/mmc/host.h>
2b11148a HL	16	#include <linux/platform_device.h>
cbff3eb3 DM	17	#include <linux/smsc911x.h>
cbff3eb3 DM	18	#include <linux/io.h>
6f5c11c5	19	#include <linux/i2c.h>
be4c33be	20	#include <linux/input.h>
8689de73	21	#include <linux/pwm_backlight.h>
b1d69cc6 CY	22
b1d69cc6 CY	23	#include <asm/mach/arch.h>
4e44d2cb	24	#include <asm/hardware/gic.h>
b1d69cc6	25	#include <asm/mach-types.h>
b1d69cc6	26
42c0d26d	27	#include <video/platform_lcd.h>
b1d69cc6	28	#include <plat/regs-serial.h>
8cf460a5	29	#include <plat/regs-srom.h>
42c0d26d	30	#include <plat/regs-fb-v4.h>
b1d69cc6	31	#include <plat/cpu.h>
cdff6e6f	32	#include <plat/devs.h>
42c0d26d	33	#include <plat/fb.h>
be4c33be	34	#include <plat/keypad.h>
2b11148a	35	#include <plat/sdhci.h>
6f5c11c5	36	#include <plat/iic.h>
8689de73 BG	37	#include <plat/gpio-cfg.h>
8689de73 BG	38	#include <plat/backlight.h>
95727e1f	39	#include <plat/mfc.h>
9830f6a2 JH	40	#include <plat/ehci.h>
9830f6a2 JH	41	#include <plat/clock.h>
b1d69cc6 CY	42
b1d69cc6 CY	43	#include <mach/map.h>
744f20f2	44	#include <mach/ohci.h>
b1d69cc6	45
ab25a8d3	46	#include <drm/exynos_drm.h>
cc511b8d KK	47	#include "common.h"
cc511b8d KK	48
b1d69cc6 CY	49	/* Following are default values for UCON, ULCON and UFCON UART registers */
	50	#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
	51	S3C2410_UCON_RXILEVEL \| \
	52	S3C2410_UCON_TXIRQMODE \| \
	53	S3C2410_UCON_RXIRQMODE \| \
	54	S3C2410_UCON_RXFIFO_TOI \| \
	55	S3C2443_UCON_RXERR_IRQEN)
	56
	57	#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
	58
	59	#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
	60	S5PV210_UFCON_TXTRIG4 \| \
	61	S5PV210_UFCON_RXTRIG4)
	62
	63	static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
	64	[0] = {
	65	.hwport = 0,
	66	.flags = 0,
	67	.ucon = SMDKV310_UCON_DEFAULT,
	68	.ulcon = SMDKV310_ULCON_DEFAULT,
	69	.ufcon = SMDKV310_UFCON_DEFAULT,
	70	},
	71	[1] = {
	72	.hwport = 1,
	73	.flags = 0,
	74	.ucon = SMDKV310_UCON_DEFAULT,
	75	.ulcon = SMDKV310_ULCON_DEFAULT,
	76	.ufcon = SMDKV310_UFCON_DEFAULT,
	77	},
	78	[2] = {
	79	.hwport = 2,
	80	.flags = 0,
	81	.ucon = SMDKV310_UCON_DEFAULT,
	82	.ulcon = SMDKV310_ULCON_DEFAULT,
	83	.ufcon = SMDKV310_UFCON_DEFAULT,
	84	},
	85	[3] = {
	86	.hwport = 3,
	87	.flags = 0,
	88	.ucon = SMDKV310_UCON_DEFAULT,
	89	.ulcon = SMDKV310_ULCON_DEFAULT,
	90	.ufcon = SMDKV310_UFCON_DEFAULT,
	91	},
	92	};
	93
2b11148a	94	static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
a0d8efed	95	.cd_type = S3C_SDHCI_CD_INTERNAL,
d11135ca	96	#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
2b11148a HL	97	.max_width = 8,
	98	.host_caps = MMC_CAP_8_BIT_DATA,
	99	#endif
	100	};
	101
	102	static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
	103	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	104	.ext_cd_gpio = EXYNOS4_GPK0(2),
2b11148a HL	105	.ext_cd_gpio_invert = 1,
	106	};
	107
	108	static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
a0d8efed	109	.cd_type = S3C_SDHCI_CD_INTERNAL,
d11135ca	110	#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
2b11148a HL	111	.max_width = 8,
	112	.host_caps = MMC_CAP_8_BIT_DATA,
	113	#endif
	114	};
	115
	116	static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
	117	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	118	.ext_cd_gpio = EXYNOS4_GPK2(2),
2b11148a HL	119	.ext_cd_gpio_invert = 1,
	120	};
	121
42c0d26d KK	122	static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
	123	unsigned int power)
	124	{
	125	if (power) {
	126	#if !defined(CONFIG_BACKLIGHT_PWM)
	127	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
	128	gpio_free(EXYNOS4_GPD0(1));
	129	#endif
	130	/* fire nRESET on power up */
321655ef	131	gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
42c0d26d KK	132	mdelay(100);
	133
	134	gpio_set_value(EXYNOS4_GPX0(6), 0);
	135	mdelay(10);
	136
	137	gpio_set_value(EXYNOS4_GPX0(6), 1);
	138	mdelay(10);
	139
	140	gpio_free(EXYNOS4_GPX0(6));
	141	} else {
	142	#if !defined(CONFIG_BACKLIGHT_PWM)
	143	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
	144	gpio_free(EXYNOS4_GPD0(1));
	145	#endif
	146	}
	147	}
	148
	149	static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
	150	.set_power = lcd_lte480wv_set_power,
	151	};
	152
	153	static struct platform_device smdkv310_lcd_lte480wv = {
	154	.name = "platform-lcd",
	155	.dev.parent = &s5p_device_fimd0.dev,
	156	.dev.platform_data = &smdkv310_lcd_lte480wv_data,
	157	};
	158
ab25a8d3 SK	159	#ifdef CONFIG_DRM_EXYNOS
	160	static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	161	.panel = {
	162	.timing = {
	163	.left_margin = 13,
	164	.right_margin = 8,
	165	.upper_margin = 7,
	166	.lower_margin = 5,
	167	.hsync_len = 3,
	168	.vsync_len = 1,
	169	.xres = 800,
	170	.yres = 480,
	171	},
	172	},
	173	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	174	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	175	.default_win = 0,
	176	.bpp = 32,
	177	};
	178	#else
42c0d26d	179	static struct s3c_fb_pd_win smdkv310_fb_win0 = {
79d3c41a TA	180	.max_bpp = 32,
	181	.default_bpp = 24,
	182	.xres = 800,
	183	.yres = 480,
	184	};
	185
	186	static struct fb_videomode smdkv310_lcd_timing = {
	187	.left_margin = 13,
	188	.right_margin = 8,
	189	.upper_margin = 7,
	190	.lower_margin = 5,
	191	.hsync_len = 3,
	192	.vsync_len = 1,
	193	.xres = 800,
	194	.yres = 480,
42c0d26d KK	195	};
	196
	197	static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
	198	.win[0] = &smdkv310_fb_win0,
79d3c41a	199	.vtiming = &smdkv310_lcd_timing,
42c0d26d KK	200	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	201	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	202	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
	203	};
ab25a8d3	204	#endif
42c0d26d	205
cbff3eb3	206	static struct resource smdkv310_smsc911x_resources[] = {
f7f145e7 TB	207	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
	208	[1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
	209	\| IRQF_TRIGGER_LOW),
cbff3eb3 DM	210	};
	211
	212	static struct smsc911x_platform_config smsc9215_config = {
cd0527c2	213	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
cbff3eb3 DM	214	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	215	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	216	.phy_interface = PHY_INTERFACE_MODE_MII,
	217	.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
	218	};
	219
	220	static struct platform_device smdkv310_smsc911x = {
	221	.name = "smsc911x",
	222	.id = -1,
	223	.num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
	224	.resource = smdkv310_smsc911x_resources,
	225	.dev = {
	226	.platform_data = &smsc9215_config,
	227	},
	228	};
	229
be4c33be NKC	230	static uint32_t smdkv310_keymap[] __initdata = {
	231	/* KEY(row, col, keycode) */
	232	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
	233	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
	234	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
	235	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
	236	};
	237
	238	static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
	239	.keymap = smdkv310_keymap,
	240	.keymap_size = ARRAY_SIZE(smdkv310_keymap),
	241	};
	242
	243	static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
	244	.keymap_data = &smdkv310_keymap_data,
	245	.rows = 2,
	246	.cols = 8,
	247	};
	248
6f5c11c5 JB	249	static struct i2c_board_info i2c_devs1[] __initdata = {
	250	{I2C_BOARD_INFO("wm8994", 0x1a),},
	251	};
	252
9830f6a2 JH	253	/* USB EHCI */
	254	static struct s5p_ehci_platdata smdkv310_ehci_pdata;
	255
	256	static void __init smdkv310_ehci_init(void)
	257	{
	258	struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
	259
	260	s5p_ehci_set_platdata(pdata);
	261	}
	262
744f20f2 JH	263	/* USB OHCI */
	264	static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
	265
	266	static void __init smdkv310_ohci_init(void)
	267	{
	268	struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
	269
	270	exynos4_ohci_set_platdata(pdata);
	271	}
	272
cdff6e6f	273	static struct platform_device *smdkv310_devices[] __initdata = {
2b11148a HL	274	&s3c_device_hsmmc0,
	275	&s3c_device_hsmmc1,
	276	&s3c_device_hsmmc2,
	277	&s3c_device_hsmmc3,
285dee7f	278	&s3c_device_i2c1,
c0735c85	279	&s5p_device_i2c_hdmiphy,
cdff6e6f	280	&s3c_device_rtc,
8d75c912	281	&s3c_device_wdt,
9830f6a2	282	&s5p_device_ehci,
568f0e27 SK	283	&s5p_device_fimc0,
	284	&s5p_device_fimc1,
	285	&s5p_device_fimc2,
	286	&s5p_device_fimc3,
e0d49c70	287	&s5p_device_fimc_md,
b3421f97	288	&s5p_device_g2d,
9fbe8c7a	289	&s5p_device_jpeg,
ab25a8d3 SK	290	#ifdef CONFIG_DRM_EXYNOS
	291	&exynos_device_drm,
	292	#endif
d11135ca KK	293	&exynos4_device_ac97,
d11135ca KK	294	&exynos4_device_i2s0,
744f20f2	295	&exynos4_device_ohci,
be4c33be	296	&samsung_device_keypad,
95727e1f SK	297	&s5p_device_mfc,
	298	&s5p_device_mfc_l,
	299	&s5p_device_mfc_r,
2ba707ac	300	&exynos4_device_spdif,
fbcb44de	301	&samsung_asoc_dma,
2839cc1e	302	&samsung_asoc_idma,
42c0d26d KK	303	&s5p_device_fimd0,
42c0d26d KK	304	&smdkv310_lcd_lte480wv,
fbcb44de	305	&smdkv310_smsc911x,
0d855f40	306	&exynos4_device_ahci,
c0735c85 HA	307	&s5p_device_hdmi,
c0735c85 HA	308	&s5p_device_mixer,
cdff6e6f CY	309	};
cdff6e6f CY	310
cbff3eb3 DM	311	static void __init smdkv310_smsc911x_init(void)
	312	{
	313	u32 cs1;
	314
	315	/* configure nCS1 width to 16 bits */
8cf460a5 KK	316	cs1 = __raw_readl(S5P_SROM_BW) &
	317	~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	318	cs1 \|= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) \|
	319	(1 << S5P_SROM_BW__WAITENABLE__SHIFT) \|
	320	(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
	321	S5P_SROM_BW__NCS1__SHIFT;
	322	__raw_writel(cs1, S5P_SROM_BW);
cbff3eb3 DM	323
cbff3eb3 DM	324	/* set timing for nCS1 suitable for ethernet chip */
8cf460a5 KK	325	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) \|
	326	(0x9 << S5P_SROM_BCX__TACP__SHIFT) \|
	327	(0xc << S5P_SROM_BCX__TCAH__SHIFT) \|
	328	(0x1 << S5P_SROM_BCX__TCOH__SHIFT) \|
	329	(0x6 << S5P_SROM_BCX__TACC__SHIFT) \|
	330	(0x1 << S5P_SROM_BCX__TCOS__SHIFT) \|
	331	(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
cbff3eb3 DM	332	}
cbff3eb3 DM	333
8689de73 BG	334	/* LCD Backlight data */
	335	static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
	336	.no = EXYNOS4_GPD0(1),
	337	.func = S3C_GPIO_SFN(2),
	338	};
	339
	340	static struct platform_pwm_backlight_data smdkv310_bl_data = {
	341	.pwm_id = 1,
	342	.pwm_period_ns = 1000,
	343	};
	344
c0735c85 HA	345	static void s5p_tv_setup(void)
	346	{
	347	/* direct HPD to HDMI chip */
	348	WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
	349	s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
	350	s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
c0735c85 HA	351	}
c0735c85 HA	352
b1d69cc6 CY	353	static void __init smdkv310_map_io(void)
b1d69cc6 CY	354	{
cc511b8d	355	exynos_init_io(NULL, 0);
b1d69cc6 CY	356	s3c24xx_init_clocks(24000000);
	357	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
	358	}
	359
95727e1f SK	360	static void __init smdkv310_reserve(void)
	361	{
	362	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
	363	}
	364
b1d69cc6 CY	365	static void __init smdkv310_machine_init(void)
b1d69cc6 CY	366	{
6f5c11c5 JB	367	s3c_i2c1_set_platdata(NULL);
	368	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
	369
cbff3eb3 DM	370	smdkv310_smsc911x_init();
cbff3eb3 DM	371
2b11148a HL	372	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
	373	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
	374	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
	375	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
	376
c0735c85 HA	377	s5p_tv_setup();
	378	s5p_i2c_hdmiphy_set_platdata(NULL);
	379
be4c33be NKC	380	samsung_keypad_set_platdata(&smdkv310_keypad_data);
be4c33be NKC	381
8689de73	382	samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
ab25a8d3 SK	383	#ifdef CONFIG_DRM_EXYNOS
	384	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	385	exynos4_fimd0_gpio_setup_24bpp();
	386	#else
42c0d26d	387	s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
ab25a8d3	388	#endif
8689de73	389
9830f6a2	390	smdkv310_ehci_init();
744f20f2	391	smdkv310_ohci_init();
9830f6a2 JH	392	clk_xusbxti.rate = 24000000;
9830f6a2 JH	393
cdff6e6f	394	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
b1d69cc6 CY	395	}
	396
	397	MACHINE_START(SMDKV310, "SMDKV310")
	398	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	399	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
1abd328e	400	.atag_offset = 0x100,
d11135ca	401	.init_irq = exynos4_init_irq,
b1d69cc6	402	.map_io = smdkv310_map_io,
4e44d2cb	403	.handle_irq = gic_handle_irq,
b1d69cc6	404	.init_machine = smdkv310_machine_init,
d11135ca	405	.timer = &exynos4_timer,
95727e1f	406	.reserve = &smdkv310_reserve,
9eb48595	407	.restart = exynos4_restart,
b1d69cc6	408	MACHINE_END
42c0d26d KK	409
	410	MACHINE_START(SMDKC210, "SMDKC210")
	411	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1abd328e	412	.atag_offset = 0x100,
42c0d26d KK	413	.init_irq = exynos4_init_irq,
42c0d26d KK	414	.map_io = smdkv310_map_io,
4e44d2cb	415	.handle_irq = gic_handle_irq,
42c0d26d	416	.init_machine = smdkv310_machine_init,
bb13fabc	417	.init_late = exynos_init_late,
42c0d26d	418	.timer = &exynos4_timer,
9eb48595	419	.restart = exynos4_restart,
42c0d26d	420	MACHINE_END