[deliverable/linux.git] / arch / arm / mach-exynos / mach-smdkv310.c

/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
 *
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/pwm_backlight.h>
#include <linux/platform_data/s3c-hsotg.h>

#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>

#include <video/platform_lcd.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/regs-fb-v4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/keypad.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
#include <plat/gpio-cfg.h>
#include <plat/backlight.h>
#include <plat/mfc.h>
#include <plat/ehci.h>
#include <plat/clock.h>

#include <mach/map.h>
#include <mach/ohci.h>

#include <drm/exynos_drm.h>
#include "common.h"

/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV310_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
				 S3C2410_UCON_RXILEVEL |	\
				 S3C2410_UCON_TXIRQMODE |	\
				 S3C2410_UCON_RXIRQMODE |	\
				 S3C2410_UCON_RXFIFO_TOI |	\
				 S3C2443_UCON_RXERR_IRQEN)

#define SMDKV310_ULCON_DEFAULT	S3C2410_LCON_CS8

#define SMDKV310_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
				 S5PV210_UFCON_TXTRIG4 |	\
				 S5PV210_UFCON_RXTRIG4)

static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
	[0] = {
		.hwport		= 0,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[1] = {
		.hwport		= 1,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[2] = {
		.hwport		= 2,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
	[3] = {
		.hwport		= 3,
		.flags		= 0,
		.ucon		= SMDKV310_UCON_DEFAULT,
		.ulcon		= SMDKV310_ULCON_DEFAULT,
		.ufcon		= SMDKV310_UFCON_DEFAULT,
	},
};

static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK0(2),
	.ext_cd_gpio_invert	= 1,
};

static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_INTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
	.max_width		= 8,
	.host_caps		= MMC_CAP_8_BIT_DATA,
#endif
};

static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
	.cd_type		= S3C_SDHCI_CD_GPIO,
	.ext_cd_gpio		= EXYNOS4_GPK2(2),
	.ext_cd_gpio_invert	= 1,
};

static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
				   unsigned int power)
{
	if (power) {
#if !defined(CONFIG_BACKLIGHT_PWM)
		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
		gpio_free(EXYNOS4_GPD0(1));
#endif
		/* fire nRESET on power up */
		gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
		mdelay(100);

		gpio_set_value(EXYNOS4_GPX0(6), 0);
		mdelay(10);

		gpio_set_value(EXYNOS4_GPX0(6), 1);
		mdelay(10);

		gpio_free(EXYNOS4_GPX0(6));
	} else {
#if !defined(CONFIG_BACKLIGHT_PWM)
		gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
		gpio_free(EXYNOS4_GPD0(1));
#endif
	}
}

static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
	.set_power		= lcd_lte480wv_set_power,
};

static struct platform_device smdkv310_lcd_lte480wv = {
	.name			= "platform-lcd",
	.dev.parent		= &s5p_device_fimd0.dev,
	.dev.platform_data	= &smdkv310_lcd_lte480wv_data,
};

#ifdef CONFIG_DRM_EXYNOS
static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	.panel	= {
		.timing	= {
			.left_margin	= 13,
			.right_margin	= 8,
			.upper_margin	= 7,
			.lower_margin	= 5,
			.hsync_len	= 3,
			.vsync_len	= 1,
			.xres		= 800,
			.yres		= 480,
		},
	},
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.default_win	= 0,
	.bpp		= 32,
};
#else
static struct s3c_fb_pd_win smdkv310_fb_win0 = {
	.max_bpp	= 32,
	.default_bpp	= 24,
	.xres		= 800,
	.yres		= 480,
};

static struct fb_videomode smdkv310_lcd_timing = {
	.left_margin	= 13,
	.right_margin	= 8,
	.upper_margin	= 7,
	.lower_margin	= 5,
	.hsync_len	= 3,
	.vsync_len	= 1,
	.xres		= 800,
	.yres		= 480,
};

static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
	.win[0]		= &smdkv310_fb_win0,
	.vtiming	= &smdkv310_lcd_timing,
	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
	.setup_gpio	= exynos4_fimd0_gpio_setup_24bpp,
};
#endif

static struct resource smdkv310_smsc911x_resources[] = {
	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
	[1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
						| IRQF_TRIGGER_LOW),
};

static struct smsc911x_platform_config smsc9215_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
	.mac		= {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};

static struct platform_device smdkv310_smsc911x = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smdkv310_smsc911x_resources),
	.resource	= smdkv310_smsc911x_resources,
	.dev		= {
		.platform_data	= &smsc9215_config,
	},
};

static uint32_t smdkv310_keymap[] __initdata = {
	/* KEY(row, col, keycode) */
	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
};

static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
	.keymap		= smdkv310_keymap,
	.keymap_size	= ARRAY_SIZE(smdkv310_keymap),
};

static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
	.keymap_data	= &smdkv310_keymap_data,
	.rows		= 2,
	.cols		= 8,
};

static struct i2c_board_info i2c_devs1[] __initdata = {
	{I2C_BOARD_INFO("wm8994", 0x1a),},
};

/* USB EHCI */
static struct s5p_ehci_platdata smdkv310_ehci_pdata;

static void __init smdkv310_ehci_init(void)
{
	struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;

	s5p_ehci_set_platdata(pdata);
}

/* USB OHCI */
static struct exynos4_ohci_platdata smdkv310_ohci_pdata;

static void __init smdkv310_ohci_init(void)
{
	struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;

	exynos4_ohci_set_platdata(pdata);
}

/* USB OTG */
static struct s3c_hsotg_plat smdkv310_hsotg_pdata;

/* Audio device */
static struct platform_device smdkv310_device_audio = {
	.name = "smdk-audio",
	.id = -1,
};

static struct platform_device *smdkv310_devices[] __initdata = {
	&s3c_device_hsmmc0,
	&s3c_device_hsmmc1,
	&s3c_device_hsmmc2,
	&s3c_device_hsmmc3,
	&s3c_device_i2c1,
	&s5p_device_i2c_hdmiphy,
	&s3c_device_rtc,
	&s3c_device_usb_hsotg,
	&s3c_device_wdt,
	&s5p_device_ehci,
	&s5p_device_fimc0,
	&s5p_device_fimc1,
	&s5p_device_fimc2,
	&s5p_device_fimc3,
	&s5p_device_fimc_md,
	&s5p_device_g2d,
	&s5p_device_jpeg,
#ifdef CONFIG_DRM_EXYNOS
	&exynos_device_drm,
#endif
	&exynos4_device_ac97,
	&exynos4_device_i2s0,
	&exynos4_device_ohci,
	&samsung_device_keypad,
	&s5p_device_mfc,
	&s5p_device_mfc_l,
	&s5p_device_mfc_r,
	&exynos4_device_spdif,
	&samsung_asoc_dma,
	&samsung_asoc_idma,
	&s5p_device_fimd0,
	&smdkv310_device_audio,
	&smdkv310_lcd_lte480wv,
	&smdkv310_smsc911x,
	&exynos4_device_ahci,
	&s5p_device_hdmi,
	&s5p_device_mixer,
};

static void __init smdkv310_smsc911x_init(void)
{
	u32 cs1;

	/* configure nCS1 width to 16 bits */
	cs1 = __raw_readl(S5P_SROM_BW) &
		~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
		(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
		(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
		S5P_SROM_BW__NCS1__SHIFT;
	__raw_writel(cs1, S5P_SROM_BW);

	/* set timing for nCS1 suitable for ethernet chip */
	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
		     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
		     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
		     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
		     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}

/* LCD Backlight data */
static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
	.no = EXYNOS4_GPD0(1),
	.func = S3C_GPIO_SFN(2),
};

static struct platform_pwm_backlight_data smdkv310_bl_data = {
	.pwm_id = 1,
	.pwm_period_ns  = 1000,
};

static void s5p_tv_setup(void)
{
	/* direct HPD to HDMI chip */
	WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
	s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
	s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
}

static void __init smdkv310_map_io(void)
{
	exynos_init_io(NULL, 0);
	s3c24xx_init_clocks(24000000);
	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}

static void __init smdkv310_reserve(void)
{
	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
}

static void __init smdkv310_machine_init(void)
{
	s3c_i2c1_set_platdata(NULL);
	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

	smdkv310_smsc911x_init();

	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);

	s5p_tv_setup();
	s5p_i2c_hdmiphy_set_platdata(NULL);

	samsung_keypad_set_platdata(&smdkv310_keypad_data);

	samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
#ifdef CONFIG_DRM_EXYNOS
	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	exynos4_fimd0_gpio_setup_24bpp();
#else
	s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
#endif

	smdkv310_ehci_init();
	smdkv310_ohci_init();
	s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
	clk_xusbxti.rate = 24000000;

	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
}

MACHINE_START(SMDKV310, "SMDKV310")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
	.atag_offset	= 0x100,
	.init_irq	= exynos4_init_irq,
	.map_io		= smdkv310_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdkv310_machine_init,
	.timer		= &exynos4_timer,
	.reserve	= &smdkv310_reserve,
	.restart	= exynos4_restart,
MACHINE_END

MACHINE_START(SMDKC210, "SMDKC210")
	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	.atag_offset	= 0x100,
	.init_irq	= exynos4_init_irq,
	.map_io		= smdkv310_map_io,
	.handle_irq	= gic_handle_irq,
	.init_machine	= smdkv310_machine_init,
	.init_late	= exynos_init_late,
	.timer		= &exynos4_timer,
	.restart	= exynos4_restart,
MACHINE_END
Commit	Line	Data
d11135ca	1	/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
b1d69cc6	2	*
d11135ca KK	3	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
d11135ca KK	4	* http://www.samsung.com
b1d69cc6 CY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/serial_core.h>
42c0d26d	12	#include <linux/delay.h>
2b11148a	13	#include <linux/gpio.h>
42c0d26d	14	#include <linux/lcd.h>
2b11148a HL	15	#include <linux/mmc/host.h>
2b11148a HL	16	#include <linux/platform_device.h>
cbff3eb3 DM	17	#include <linux/smsc911x.h>
cbff3eb3 DM	18	#include <linux/io.h>
6f5c11c5	19	#include <linux/i2c.h>
be4c33be	20	#include <linux/input.h>
8689de73	21	#include <linux/pwm_backlight.h>
fb395c39	22	#include <linux/platform_data/s3c-hsotg.h>
b1d69cc6 CY	23
b1d69cc6 CY	24	#include <asm/mach/arch.h>
4e44d2cb	25	#include <asm/hardware/gic.h>
b1d69cc6	26	#include <asm/mach-types.h>
b1d69cc6	27
42c0d26d	28	#include <video/platform_lcd.h>
b1d69cc6	29	#include <plat/regs-serial.h>
8cf460a5	30	#include <plat/regs-srom.h>
42c0d26d	31	#include <plat/regs-fb-v4.h>
b1d69cc6	32	#include <plat/cpu.h>
cdff6e6f	33	#include <plat/devs.h>
42c0d26d	34	#include <plat/fb.h>
be4c33be	35	#include <plat/keypad.h>
2b11148a	36	#include <plat/sdhci.h>
6f5c11c5	37	#include <plat/iic.h>
d6d8b481	38	#include <plat/pd.h>
8689de73 BG	39	#include <plat/gpio-cfg.h>
8689de73 BG	40	#include <plat/backlight.h>
95727e1f	41	#include <plat/mfc.h>
9830f6a2 JH	42	#include <plat/ehci.h>
9830f6a2 JH	43	#include <plat/clock.h>
b1d69cc6 CY	44
b1d69cc6 CY	45	#include <mach/map.h>
744f20f2	46	#include <mach/ohci.h>
b1d69cc6	47
ab25a8d3	48	#include <drm/exynos_drm.h>
cc511b8d KK	49	#include "common.h"
cc511b8d KK	50
b1d69cc6 CY	51	/* Following are default values for UCON, ULCON and UFCON UART registers */
	52	#define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL \| \
	53	S3C2410_UCON_RXILEVEL \| \
	54	S3C2410_UCON_TXIRQMODE \| \
	55	S3C2410_UCON_RXIRQMODE \| \
	56	S3C2410_UCON_RXFIFO_TOI \| \
	57	S3C2443_UCON_RXERR_IRQEN)
	58
	59	#define SMDKV310_ULCON_DEFAULT S3C2410_LCON_CS8
	60
	61	#define SMDKV310_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE \| \
	62	S5PV210_UFCON_TXTRIG4 \| \
	63	S5PV210_UFCON_RXTRIG4)
	64
	65	static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
	66	[0] = {
	67	.hwport = 0,
	68	.flags = 0,
	69	.ucon = SMDKV310_UCON_DEFAULT,
	70	.ulcon = SMDKV310_ULCON_DEFAULT,
	71	.ufcon = SMDKV310_UFCON_DEFAULT,
	72	},
	73	[1] = {
	74	.hwport = 1,
	75	.flags = 0,
	76	.ucon = SMDKV310_UCON_DEFAULT,
	77	.ulcon = SMDKV310_ULCON_DEFAULT,
	78	.ufcon = SMDKV310_UFCON_DEFAULT,
	79	},
	80	[2] = {
	81	.hwport = 2,
	82	.flags = 0,
	83	.ucon = SMDKV310_UCON_DEFAULT,
	84	.ulcon = SMDKV310_ULCON_DEFAULT,
	85	.ufcon = SMDKV310_UFCON_DEFAULT,
	86	},
	87	[3] = {
	88	.hwport = 3,
	89	.flags = 0,
	90	.ucon = SMDKV310_UCON_DEFAULT,
	91	.ulcon = SMDKV310_ULCON_DEFAULT,
	92	.ufcon = SMDKV310_UFCON_DEFAULT,
	93	},
	94	};
	95
2b11148a	96	static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
a0d8efed	97	.cd_type = S3C_SDHCI_CD_INTERNAL,
d11135ca	98	#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
2b11148a HL	99	.max_width = 8,
	100	.host_caps = MMC_CAP_8_BIT_DATA,
	101	#endif
	102	};
	103
	104	static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
	105	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	106	.ext_cd_gpio = EXYNOS4_GPK0(2),
2b11148a HL	107	.ext_cd_gpio_invert = 1,
	108	};
	109
	110	static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
a0d8efed	111	.cd_type = S3C_SDHCI_CD_INTERNAL,
d11135ca	112	#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
2b11148a HL	113	.max_width = 8,
	114	.host_caps = MMC_CAP_8_BIT_DATA,
	115	#endif
	116	};
	117
	118	static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
	119	.cd_type = S3C_SDHCI_CD_GPIO,
d11135ca	120	.ext_cd_gpio = EXYNOS4_GPK2(2),
2b11148a HL	121	.ext_cd_gpio_invert = 1,
	122	};
	123
42c0d26d KK	124	static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
	125	unsigned int power)
	126	{
	127	if (power) {
	128	#if !defined(CONFIG_BACKLIGHT_PWM)
	129	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
	130	gpio_free(EXYNOS4_GPD0(1));
	131	#endif
	132	/* fire nRESET on power up */
321655ef	133	gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
42c0d26d KK	134	mdelay(100);
	135
	136	gpio_set_value(EXYNOS4_GPX0(6), 0);
	137	mdelay(10);
	138
	139	gpio_set_value(EXYNOS4_GPX0(6), 1);
	140	mdelay(10);
	141
	142	gpio_free(EXYNOS4_GPX0(6));
	143	} else {
	144	#if !defined(CONFIG_BACKLIGHT_PWM)
	145	gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
	146	gpio_free(EXYNOS4_GPD0(1));
	147	#endif
	148	}
	149	}
	150
	151	static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
	152	.set_power = lcd_lte480wv_set_power,
	153	};
	154
	155	static struct platform_device smdkv310_lcd_lte480wv = {
	156	.name = "platform-lcd",
	157	.dev.parent = &s5p_device_fimd0.dev,
	158	.dev.platform_data = &smdkv310_lcd_lte480wv_data,
	159	};
	160
ab25a8d3 SK	161	#ifdef CONFIG_DRM_EXYNOS
	162	static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
	163	.panel = {
	164	.timing = {
	165	.left_margin = 13,
	166	.right_margin = 8,
	167	.upper_margin = 7,
	168	.lower_margin = 5,
	169	.hsync_len = 3,
	170	.vsync_len = 1,
	171	.xres = 800,
	172	.yres = 480,
	173	},
	174	},
	175	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	176	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	177	.default_win = 0,
	178	.bpp = 32,
	179	};
	180	#else
42c0d26d	181	static struct s3c_fb_pd_win smdkv310_fb_win0 = {
79d3c41a TA	182	.max_bpp = 32,
	183	.default_bpp = 24,
	184	.xres = 800,
	185	.yres = 480,
	186	};
	187
	188	static struct fb_videomode smdkv310_lcd_timing = {
	189	.left_margin = 13,
	190	.right_margin = 8,
	191	.upper_margin = 7,
	192	.lower_margin = 5,
	193	.hsync_len = 3,
	194	.vsync_len = 1,
	195	.xres = 800,
	196	.yres = 480,
42c0d26d KK	197	};
	198
	199	static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
	200	.win[0] = &smdkv310_fb_win0,
79d3c41a	201	.vtiming = &smdkv310_lcd_timing,
42c0d26d KK	202	.vidcon0 = VIDCON0_VIDOUT_RGB \| VIDCON0_PNRMODE_RGB,
	203	.vidcon1 = VIDCON1_INV_HSYNC \| VIDCON1_INV_VSYNC,
	204	.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
	205	};
ab25a8d3	206	#endif
42c0d26d	207
cbff3eb3	208	static struct resource smdkv310_smsc911x_resources[] = {
f7f145e7 TB	209	[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
	210	[1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
	211	\| IRQF_TRIGGER_LOW),
cbff3eb3 DM	212	};
	213
	214	static struct smsc911x_platform_config smsc9215_config = {
cd0527c2	215	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
cbff3eb3 DM	216	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	217	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	218	.phy_interface = PHY_INTERFACE_MODE_MII,
	219	.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
	220	};
	221
	222	static struct platform_device smdkv310_smsc911x = {
	223	.name = "smsc911x",
	224	.id = -1,
	225	.num_resources = ARRAY_SIZE(smdkv310_smsc911x_resources),
	226	.resource = smdkv310_smsc911x_resources,
	227	.dev = {
	228	.platform_data = &smsc9215_config,
	229	},
	230	};
	231
be4c33be NKC	232	static uint32_t smdkv310_keymap[] __initdata = {
	233	/* KEY(row, col, keycode) */
	234	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
	235	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
	236	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
	237	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
	238	};
	239
	240	static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
	241	.keymap = smdkv310_keymap,
	242	.keymap_size = ARRAY_SIZE(smdkv310_keymap),
	243	};
	244
	245	static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
	246	.keymap_data = &smdkv310_keymap_data,
	247	.rows = 2,
	248	.cols = 8,
	249	};
	250
6f5c11c5 JB	251	static struct i2c_board_info i2c_devs1[] __initdata = {
	252	{I2C_BOARD_INFO("wm8994", 0x1a),},
	253	};
	254
9830f6a2 JH	255	/* USB EHCI */
	256	static struct s5p_ehci_platdata smdkv310_ehci_pdata;
	257
	258	static void __init smdkv310_ehci_init(void)
	259	{
	260	struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
	261
	262	s5p_ehci_set_platdata(pdata);
	263	}
	264
744f20f2 JH	265	/* USB OHCI */
	266	static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
	267
	268	static void __init smdkv310_ohci_init(void)
	269	{
	270	struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
	271
	272	exynos4_ohci_set_platdata(pdata);
	273	}
	274
fb395c39 SK	275	/* USB OTG */
	276	static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
	277
1b1ce356 SK	278	/* Audio device */
	279	static struct platform_device smdkv310_device_audio = {
	280	.name = "smdk-audio",
	281	.id = -1,
	282	};
	283
cdff6e6f	284	static struct platform_device *smdkv310_devices[] __initdata = {
2b11148a HL	285	&s3c_device_hsmmc0,
	286	&s3c_device_hsmmc1,
	287	&s3c_device_hsmmc2,
	288	&s3c_device_hsmmc3,
285dee7f	289	&s3c_device_i2c1,
c0735c85	290	&s5p_device_i2c_hdmiphy,
cdff6e6f	291	&s3c_device_rtc,
fb395c39	292	&s3c_device_usb_hsotg,
8d75c912	293	&s3c_device_wdt,
9830f6a2	294	&s5p_device_ehci,
568f0e27 SK	295	&s5p_device_fimc0,
	296	&s5p_device_fimc1,
	297	&s5p_device_fimc2,
	298	&s5p_device_fimc3,
e0d49c70	299	&s5p_device_fimc_md,
b3421f97	300	&s5p_device_g2d,
9fbe8c7a	301	&s5p_device_jpeg,
ab25a8d3 SK	302	#ifdef CONFIG_DRM_EXYNOS
	303	&exynos_device_drm,
	304	#endif
d11135ca KK	305	&exynos4_device_ac97,
d11135ca KK	306	&exynos4_device_i2s0,
744f20f2	307	&exynos4_device_ohci,
be4c33be	308	&samsung_device_keypad,
95727e1f SK	309	&s5p_device_mfc,
	310	&s5p_device_mfc_l,
	311	&s5p_device_mfc_r,
2ba707ac	312	&exynos4_device_spdif,
fbcb44de	313	&samsung_asoc_dma,
2839cc1e	314	&samsung_asoc_idma,
42c0d26d	315	&s5p_device_fimd0,
1b1ce356	316	&smdkv310_device_audio,
42c0d26d	317	&smdkv310_lcd_lte480wv,
fbcb44de	318	&smdkv310_smsc911x,
0d855f40	319	&exynos4_device_ahci,
c0735c85 HA	320	&s5p_device_hdmi,
c0735c85 HA	321	&s5p_device_mixer,
cdff6e6f CY	322	};
cdff6e6f CY	323
cbff3eb3 DM	324	static void __init smdkv310_smsc911x_init(void)
	325	{
	326	u32 cs1;
	327
	328	/* configure nCS1 width to 16 bits */
8cf460a5 KK	329	cs1 = __raw_readl(S5P_SROM_BW) &
	330	~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
	331	cs1 \|= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) \|
	332	(1 << S5P_SROM_BW__WAITENABLE__SHIFT) \|
	333	(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
	334	S5P_SROM_BW__NCS1__SHIFT;
	335	__raw_writel(cs1, S5P_SROM_BW);
cbff3eb3 DM	336
cbff3eb3 DM	337	/* set timing for nCS1 suitable for ethernet chip */
8cf460a5 KK	338	__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) \|
	339	(0x9 << S5P_SROM_BCX__TACP__SHIFT) \|
	340	(0xc << S5P_SROM_BCX__TCAH__SHIFT) \|
	341	(0x1 << S5P_SROM_BCX__TCOH__SHIFT) \|
	342	(0x6 << S5P_SROM_BCX__TACC__SHIFT) \|
	343	(0x1 << S5P_SROM_BCX__TCOS__SHIFT) \|
	344	(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
cbff3eb3 DM	345	}
cbff3eb3 DM	346
8689de73 BG	347	/* LCD Backlight data */
	348	static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
	349	.no = EXYNOS4_GPD0(1),
	350	.func = S3C_GPIO_SFN(2),
	351	};
	352
	353	static struct platform_pwm_backlight_data smdkv310_bl_data = {
	354	.pwm_id = 1,
	355	.pwm_period_ns = 1000,
	356	};
	357
c0735c85 HA	358	static void s5p_tv_setup(void)
	359	{
	360	/* direct HPD to HDMI chip */
	361	WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
	362	s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
	363	s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
c0735c85 HA	364	}
c0735c85 HA	365
b1d69cc6 CY	366	static void __init smdkv310_map_io(void)
b1d69cc6 CY	367	{
cc511b8d	368	exynos_init_io(NULL, 0);
b1d69cc6 CY	369	s3c24xx_init_clocks(24000000);
	370	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
	371	}
	372
95727e1f SK	373	static void __init smdkv310_reserve(void)
	374	{
	375	s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
	376	}
	377
b1d69cc6 CY	378	static void __init smdkv310_machine_init(void)
b1d69cc6 CY	379	{
6f5c11c5 JB	380	s3c_i2c1_set_platdata(NULL);
	381	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
	382
cbff3eb3 DM	383	smdkv310_smsc911x_init();
cbff3eb3 DM	384
2b11148a HL	385	s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
	386	s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
	387	s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
	388	s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
	389
c0735c85 HA	390	s5p_tv_setup();
	391	s5p_i2c_hdmiphy_set_platdata(NULL);
	392
be4c33be NKC	393	samsung_keypad_set_platdata(&smdkv310_keypad_data);
be4c33be NKC	394
8689de73	395	samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
ab25a8d3 SK	396	#ifdef CONFIG_DRM_EXYNOS
	397	s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
	398	exynos4_fimd0_gpio_setup_24bpp();
	399	#else
42c0d26d	400	s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
ab25a8d3	401	#endif
8689de73	402
9830f6a2	403	smdkv310_ehci_init();
744f20f2	404	smdkv310_ohci_init();
fb395c39	405	s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
9830f6a2 JH	406	clk_xusbxti.rate = 24000000;
9830f6a2 JH	407
cdff6e6f	408	platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
b1d69cc6 CY	409	}
	410
	411	MACHINE_START(SMDKV310, "SMDKV310")
	412	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
	413	/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
1abd328e	414	.atag_offset = 0x100,
d11135ca	415	.init_irq = exynos4_init_irq,
b1d69cc6	416	.map_io = smdkv310_map_io,
4e44d2cb	417	.handle_irq = gic_handle_irq,
b1d69cc6	418	.init_machine = smdkv310_machine_init,
d11135ca	419	.timer = &exynos4_timer,
95727e1f	420	.reserve = &smdkv310_reserve,
9eb48595	421	.restart = exynos4_restart,
b1d69cc6	422	MACHINE_END
42c0d26d KK	423
	424	MACHINE_START(SMDKC210, "SMDKC210")
	425	/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
1abd328e	426	.atag_offset = 0x100,
42c0d26d KK	427	.init_irq = exynos4_init_irq,
42c0d26d KK	428	.map_io = smdkv310_map_io,
4e44d2cb	429	.handle_irq = gic_handle_irq,
42c0d26d	430	.init_machine = smdkv310_machine_init,
bb13fabc	431	.init_late = exynos_init_late,
42c0d26d	432	.timer = &exynos4_timer,
9eb48595	433	.restart = exynos4_restart,
42c0d26d	434	MACHINE_END