projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: 7262/1: restart: EXYNOS: use new restart hook
[deliverable/linux.git] / arch / arm / mach-exynos / mach-universal_c210.c
CommitLineData
d11135ca 1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
516607d6
KP		 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
34d79315 10#include <linux/platform_device.h>
516607d6 11#include <linux/serial_core.h>
34d79315 12#include <linux/input.h>
3b7998f5 13#include <linux/i2c.h>
34d79315
KP		 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
f3f5bfe2 16#include <linux/fb.h>
4d838ec0 17#include <linux/mfd/max8998.h>
a8928ce7
KP		 18#include <linux/regulator/machine.h>
19#include <linux/regulator/fixed.h>
4d838ec0 20#include <linux/regulator/max8952.h>
a8928ce7 21#include <linux/mmc/host.h>
b908af44
MS		 22#include <linux/i2c-gpio.h>
23#include <linux/i2c/mcs.h>
0b398b69 24#include <linux/i2c/atmel_mxt_ts.h>
516607d6
KP		 25
26#include <asm/mach/arch.h>
27#include <asm/mach-types.h>
516607d6
KP		 28
29#include <plat/regs-serial.h>
516607d6 30#include <plat/cpu.h>
acf5eda9 31#include <plat/devs.h>
4d838ec0 32#include <plat/iic.h>
0b398b69 33#include <plat/gpio-cfg.h>
f3f5bfe2 34#include <plat/fb.h>
b14f04db 35#include <plat/mfc.h>
a8928ce7 36#include <plat/sdhci.h>
b14f04db 37#include <plat/pd.h>
f3f5bfe2 38#include <plat/regs-fb-v4.h>
05132182
SN		 39#include <plat/fimc-core.h>
40#include <plat/camport.h>
41#include <plat/mipi_csis.h>
516607d6
KP		 42
43#include <mach/map.h>
44
05132182
SN		 45#include <media/v4l2-mediabus.h>
46#include <media/s5p_fimc.h>
47#include <media/m5mols.h>
48
cc511b8d
KK		 49#include "common.h"
50
516607d6
KP		 51/* Following are default values for UCON, ULCON and UFCON UART registers */
52#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
53 S3C2410_UCON_RXILEVEL | \
54 S3C2410_UCON_TXIRQMODE | \
55 S3C2410_UCON_RXIRQMODE | \
56 S3C2410_UCON_RXFIFO_TOI | \
57 S3C2443_UCON_RXERR_IRQEN)
58
59#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
60
61#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
62 S5PV210_UFCON_TXTRIG256 | \
63 S5PV210_UFCON_RXTRIG256)
64
65static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
66 [0] = {
67 .hwport = 0,
68 .ucon = UNIVERSAL_UCON_DEFAULT,
69 .ulcon = UNIVERSAL_ULCON_DEFAULT,
70 .ufcon = UNIVERSAL_UFCON_DEFAULT,
71 },
72 [1] = {
73 .hwport = 1,
74 .ucon = UNIVERSAL_UCON_DEFAULT,
75 .ulcon = UNIVERSAL_ULCON_DEFAULT,
76 .ufcon = UNIVERSAL_UFCON_DEFAULT,
77 },
78 [2] = {
79 .hwport = 2,
80 .ucon = UNIVERSAL_UCON_DEFAULT,
81 .ulcon = UNIVERSAL_ULCON_DEFAULT,
82 .ufcon = UNIVERSAL_UFCON_DEFAULT,
83 },
84 [3] = {
85 .hwport = 3,
86 .ucon = UNIVERSAL_UCON_DEFAULT,
87 .ulcon = UNIVERSAL_ULCON_DEFAULT,
88 .ufcon = UNIVERSAL_UFCON_DEFAULT,
89 },
90};
91
4d838ec0 92static struct regulator_consumer_supply max8952_consumer =
c1a238aa 93 REGULATOR_SUPPLY("vdd_arm", NULL);
4d838ec0
MS		 94
95static struct max8952_platform_data universal_max8952_pdata __initdata = {
96 .gpio_vid0 = EXYNOS4_GPX0(3),
97 .gpio_vid1 = EXYNOS4_GPX0(4),
98 .gpio_en = -1, /* Not controllable, set "Always High" */
99 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
100 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
101 .sync_freq = 0, /* default: fastest */
102 .ramp_speed = 0, /* default: fastest */
103
104 .reg_data = {
105 .constraints = {
106 .name = "VARM_1.2V",
107 .min_uV = 770000,
108 .max_uV = 1400000,
109 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
110 .always_on = 1,
111 .boot_on = 1,
112 },
113 .num_consumer_supplies = 1,
114 .consumer_supplies = &max8952_consumer,
115 },
116};
117
118static struct regulator_consumer_supply lp3974_buck1_consumer =
c1a238aa 119 REGULATOR_SUPPLY("vdd_int", NULL);
4d838ec0
MS		 120
121static struct regulator_consumer_supply lp3974_buck2_consumer =
122 REGULATOR_SUPPLY("vddg3d", NULL);
123
d737cf29
TS		 124static struct regulator_consumer_supply lp3974_buck3_consumer =
125 REGULATOR_SUPPLY("vdet", "s5p-sdo");
126
4d838ec0
MS		 127static struct regulator_init_data lp3974_buck1_data = {
128 .constraints = {
129 .name = "VINT_1.1V",
130 .min_uV = 750000,
131 .max_uV = 1500000,
132 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
133 REGULATOR_CHANGE_STATUS,
134 .boot_on = 1,
135 .state_mem = {
136 .disabled = 1,
137 },
138 },
139 .num_consumer_supplies = 1,
140 .consumer_supplies = &lp3974_buck1_consumer,
141};
142
143static struct regulator_init_data lp3974_buck2_data = {
144 .constraints = {
145 .name = "VG3D_1.1V",
146 .min_uV = 750000,
147 .max_uV = 1500000,
148 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
149 REGULATOR_CHANGE_STATUS,
150 .boot_on = 1,
151 .state_mem = {
152 .disabled = 1,
153 },
154 },
155 .num_consumer_supplies = 1,
156 .consumer_supplies = &lp3974_buck2_consumer,
157};
158
159static struct regulator_init_data lp3974_buck3_data = {
160 .constraints = {
161 .name = "VCC_1.8V",
162 .min_uV = 1800000,
163 .max_uV = 1800000,
164 .apply_uV = 1,
165 .always_on = 1,
166 .state_mem = {
167 .enabled = 1,
168 },
169 },
d737cf29
TS		 170 .num_consumer_supplies = 1,
171 .consumer_supplies = &lp3974_buck3_consumer,
4d838ec0
MS		 172};
173
174static struct regulator_init_data lp3974_buck4_data = {
175 .constraints = {
176 .name = "VMEM_1.2V",
177 .min_uV = 1200000,
178 .max_uV = 1200000,
179 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
180 .apply_uV = 1,
181 .state_mem = {
182 .disabled = 1,
183 },
184 },
185};
186
187static struct regulator_init_data lp3974_ldo2_data = {
188 .constraints = {
189 .name = "VALIVE_1.2V",
190 .min_uV = 1200000,
191 .max_uV = 1200000,
192 .apply_uV = 1,
193 .always_on = 1,
194 .state_mem = {
195 .enabled = 1,
196 },
197 },
198};
199
d737cf29
TS		 200static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
201 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
202 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
05132182 203 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
d737cf29
TS		 204};
205
4d838ec0
MS		 206static struct regulator_init_data lp3974_ldo3_data = {
207 .constraints = {
208 .name = "VUSB+MIPI_1.1V",
209 .min_uV = 1100000,
210 .max_uV = 1100000,
211 .apply_uV = 1,
212 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
213 .state_mem = {
214 .disabled = 1,
215 },
216 },
d737cf29
TS		 217 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
218 .consumer_supplies = lp3974_ldo3_consumer,
219};
220
221static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
222 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
4d838ec0
MS		 223};
224
225static struct regulator_init_data lp3974_ldo4_data = {
226 .constraints = {
227 .name = "VADC_3.3V",
228 .min_uV = 3300000,
229 .max_uV = 3300000,
230 .apply_uV = 1,
231 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
232 .state_mem = {
233 .disabled = 1,
234 },
235 },
d737cf29
TS		 236 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
237 .consumer_supplies = lp3974_ldo4_consumer,
4d838ec0
MS		 238};
239
240static struct regulator_init_data lp3974_ldo5_data = {
241 .constraints = {
242 .name = "VTF_2.8V",
243 .min_uV = 2800000,
244 .max_uV = 2800000,
245 .apply_uV = 1,
246 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
247 .state_mem = {
248 .disabled = 1,
249 },
250 },
251};
252
253static struct regulator_init_data lp3974_ldo6_data = {
254 .constraints = {
255 .name = "LDO6",
256 .min_uV = 2000000,
257 .max_uV = 2000000,
258 .apply_uV = 1,
259 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
260 .state_mem = {
261 .disabled = 1,
262 },
263 },
264};
265
05132182
SN		 266static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
267 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
268};
269
4d838ec0
MS		 270static struct regulator_init_data lp3974_ldo7_data = {
271 .constraints = {
272 .name = "VLCD+VMIPI_1.8V",
273 .min_uV = 1800000,
274 .max_uV = 1800000,
275 .apply_uV = 1,
276 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
277 .state_mem = {
278 .disabled = 1,
279 },
280 },
05132182
SN		 281 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
282 .consumer_supplies = lp3974_ldo7_consumer,
4d838ec0
MS		 283};
284
d737cf29
TS		 285static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
286 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
287};
288
4d838ec0
MS		 289static struct regulator_init_data lp3974_ldo8_data = {
290 .constraints = {
291 .name = "VUSB+VDAC_3.3V",
292 .min_uV = 3300000,
293 .max_uV = 3300000,
294 .apply_uV = 1,
295 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
296 .state_mem = {
297 .disabled = 1,
298 },
299 },
d737cf29
TS		 300 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
301 .consumer_supplies = lp3974_ldo8_consumer,
4d838ec0
MS		 302};
303
304static struct regulator_init_data lp3974_ldo9_data = {
305 .constraints = {
306 .name = "VCC_2.8V",
307 .min_uV = 2800000,
308 .max_uV = 2800000,
309 .apply_uV = 1,
310 .always_on = 1,
311 .state_mem = {
312 .enabled = 1,
313 },
314 },
315};
316
317static struct regulator_init_data lp3974_ldo10_data = {
318 .constraints = {
319 .name = "VPLL_1.1V",
320 .min_uV = 1100000,
321 .max_uV = 1100000,
322 .boot_on = 1,
323 .apply_uV = 1,
324 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
325 .state_mem = {
326 .disabled = 1,
327 },
328 },
329};
330
05132182
SN		 331static struct regulator_consumer_supply lp3974_ldo11_consumer =
332 REGULATOR_SUPPLY("dig_28", "0-001f");
333
4d838ec0
MS		 334static struct regulator_init_data lp3974_ldo11_data = {
335 .constraints = {
336 .name = "CAM_AF_3.3V",
337 .min_uV = 3300000,
338 .max_uV = 3300000,
339 .apply_uV = 1,
340 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
341 .state_mem = {
342 .disabled = 1,
343 },
344 },
05132182
SN		 345 .num_consumer_supplies = 1,
346 .consumer_supplies = &lp3974_ldo11_consumer,
4d838ec0
MS		 347};
348
349static struct regulator_init_data lp3974_ldo12_data = {
350 .constraints = {
351 .name = "PS_2.8V",
352 .min_uV = 2800000,
353 .max_uV = 2800000,
354 .apply_uV = 1,
355 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
356 .state_mem = {
357 .disabled = 1,
358 },
359 },
360};
361
362static struct regulator_init_data lp3974_ldo13_data = {
363 .constraints = {
364 .name = "VHIC_1.2V",
365 .min_uV = 1200000,
366 .max_uV = 1200000,
367 .apply_uV = 1,
368 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
369 .state_mem = {
370 .disabled = 1,
371 },
372 },
373};
374
05132182
SN		 375static struct regulator_consumer_supply lp3974_ldo14_consumer =
376 REGULATOR_SUPPLY("dig_18", "0-001f");
377
4d838ec0
MS		 378static struct regulator_init_data lp3974_ldo14_data = {
379 .constraints = {
380 .name = "CAM_I_HOST_1.8V",
381 .min_uV = 1800000,
382 .max_uV = 1800000,
383 .apply_uV = 1,
384 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
385 .state_mem = {
386 .disabled = 1,
387 },
388 },
05132182
SN		 389 .num_consumer_supplies = 1,
390 .consumer_supplies = &lp3974_ldo14_consumer,
4d838ec0
MS		 391};
392
05132182
SN		 393
394static struct regulator_consumer_supply lp3974_ldo15_consumer =
395 REGULATOR_SUPPLY("dig_12", "0-001f");
396
4d838ec0
MS		 397static struct regulator_init_data lp3974_ldo15_data = {
398 .constraints = {
399 .name = "CAM_S_DIG+FM33_CORE_1.2V",
400 .min_uV = 1200000,
401 .max_uV = 1200000,
402 .apply_uV = 1,
403 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
404 .state_mem = {
405 .disabled = 1,
406 },
407 },
05132182
SN		 408 .num_consumer_supplies = 1,
409 .consumer_supplies = &lp3974_ldo15_consumer,
410};
411
412static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
413 REGULATOR_SUPPLY("a_sensor", "0-001f"),
4d838ec0
MS		 414};
415
416static struct regulator_init_data lp3974_ldo16_data = {
417 .constraints = {
418 .name = "CAM_S_ANA_2.8V",
419 .min_uV = 2800000,
420 .max_uV = 2800000,
421 .apply_uV = 1,
422 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
423 .state_mem = {
424 .disabled = 1,
425 },
426 },
05132182
SN		 427 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
428 .consumer_supplies = lp3974_ldo16_consumer,
4d838ec0
MS		 429};
430
431static struct regulator_init_data lp3974_ldo17_data = {
432 .constraints = {
433 .name = "VCC_3.0V_LCD",
434 .min_uV = 3000000,
435 .max_uV = 3000000,
436 .apply_uV = 1,
437 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
438 .boot_on = 1,
439 .state_mem = {
440 .disabled = 1,
441 },
442 },
443};
444
445static struct regulator_init_data lp3974_32khz_ap_data = {
446 .constraints = {
447 .name = "32KHz AP",
448 .always_on = 1,
449 .state_mem = {
450 .enabled = 1,
451 },
452 },
453};
454
455static struct regulator_init_data lp3974_32khz_cp_data = {
456 .constraints = {
457 .name = "32KHz CP",
458 .state_mem = {
459 .disabled = 1,
460 },
461 },
462};
463
464static struct regulator_init_data lp3974_vichg_data = {
465 .constraints = {
466 .name = "VICHG",
467 .state_mem = {
468 .disabled = 1,
469 },
470 },
471};
472
473static struct regulator_init_data lp3974_esafeout1_data = {
474 .constraints = {
475 .name = "SAFEOUT1",
476 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
477 .state_mem = {
478 .enabled = 1,
479 },
480 },
481};
482
483static struct regulator_init_data lp3974_esafeout2_data = {
484 .constraints = {
485 .name = "SAFEOUT2",
486 .boot_on = 1,
487 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
488 .state_mem = {
489 .enabled = 1,
490 },
491 },
492};
493
494static struct max8998_regulator_data lp3974_regulators[] = {
495 { MAX8998_LDO2, &lp3974_ldo2_data },
496 { MAX8998_LDO3, &lp3974_ldo3_data },
497 { MAX8998_LDO4, &lp3974_ldo4_data },
498 { MAX8998_LDO5, &lp3974_ldo5_data },
499 { MAX8998_LDO6, &lp3974_ldo6_data },
500 { MAX8998_LDO7, &lp3974_ldo7_data },
501 { MAX8998_LDO8, &lp3974_ldo8_data },
502 { MAX8998_LDO9, &lp3974_ldo9_data },
503 { MAX8998_LDO10, &lp3974_ldo10_data },
504 { MAX8998_LDO11, &lp3974_ldo11_data },
505 { MAX8998_LDO12, &lp3974_ldo12_data },
506 { MAX8998_LDO13, &lp3974_ldo13_data },
507 { MAX8998_LDO14, &lp3974_ldo14_data },
508 { MAX8998_LDO15, &lp3974_ldo15_data },
509 { MAX8998_LDO16, &lp3974_ldo16_data },
510 { MAX8998_LDO17, &lp3974_ldo17_data },
511 { MAX8998_BUCK1, &lp3974_buck1_data },
512 { MAX8998_BUCK2, &lp3974_buck2_data },
513 { MAX8998_BUCK3, &lp3974_buck3_data },
514 { MAX8998_BUCK4, &lp3974_buck4_data },
515 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
516 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
517 { MAX8998_ENVICHG, &lp3974_vichg_data },
518 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
519 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
520};
521
522static struct max8998_platform_data universal_lp3974_pdata = {
523 .num_regulators = ARRAY_SIZE(lp3974_regulators),
524 .regulators = lp3974_regulators,
525 .buck1_voltage1 = 1100000, /* INT */
526 .buck1_voltage2 = 1000000,
527 .buck1_voltage3 = 1100000,
528 .buck1_voltage4 = 1000000,
529 .buck1_set1 = EXYNOS4_GPX0(5),
530 .buck1_set2 = EXYNOS4_GPX0(6),
531 .buck2_voltage1 = 1200000, /* G3D */
532 .buck2_voltage2 = 1100000,
533 .buck1_default_idx = 0,
534 .buck2_set3 = EXYNOS4_GPE2(0),
535 .buck2_default_idx = 0,
536 .wakeup = true,
537};
538
05132182
SN		 539
540enum fixed_regulator_id {
541 FIXED_REG_ID_MMC0,
542 FIXED_REG_ID_HDMI_5V,
543 FIXED_REG_ID_CAM_S_IF,
544 FIXED_REG_ID_CAM_I_CORE,
545 FIXED_REG_ID_CAM_VT_DIO,
546};
547
d737cf29
TS		 548static struct regulator_consumer_supply hdmi_fixed_consumer =
549 REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
550
551static struct regulator_init_data hdmi_fixed_voltage_init_data = {
552 .constraints = {
553 .name = "HDMI_5V",
554 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
555 },
556 .num_consumer_supplies = 1,
557 .consumer_supplies = &hdmi_fixed_consumer,
558};
559
560static struct fixed_voltage_config hdmi_fixed_voltage_config = {
561 .supply_name = "HDMI_EN1",
562 .microvolts = 5000000,
563 .gpio = EXYNOS4_GPE0(1),
564 .enable_high = true,
565 .init_data = &hdmi_fixed_voltage_init_data,
566};
567
568static struct platform_device hdmi_fixed_voltage = {
569 .name = "reg-fixed-voltage",
05132182 570 .id = FIXED_REG_ID_HDMI_5V,
d737cf29
TS		 571 .dev = {
572 .platform_data = &hdmi_fixed_voltage_config,
573 },
574};
575
4d838ec0
MS		 576/* GPIO I2C 5 (PMIC) */
577static struct i2c_board_info i2c5_devs[] __initdata = {
578 {
579 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
580 .platform_data = &universal_max8952_pdata,
581 }, {
582 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
583 .platform_data = &universal_lp3974_pdata,
584 },
585};
586
0b398b69
MS		 587/* I2C3 (TSP) */
588static struct mxt_platform_data qt602240_platform_data = {
589 .x_line = 19,
590 .y_line = 11,
591 .x_size = 800,
592 .y_size = 480,
593 .blen = 0x11,
594 .threshold = 0x28,
595 .voltage = 2800000, /* 2.8V */
596 .orient = MXT_DIAGONAL,
597};
598
599static struct i2c_board_info i2c3_devs[] __initdata = {
600 {
601 I2C_BOARD_INFO("qt602240_ts", 0x4a),
602 .platform_data = &qt602240_platform_data,
603 },
604};
605
606static void __init universal_tsp_init(void)
607{
608 int gpio;
609
610 /* TSP_LDO_ON: XMDMADDR_11 */
611 gpio = EXYNOS4_GPE2(3);
612 gpio_request(gpio, "TSP_LDO_ON");
613 gpio_direction_output(gpio, 1);
614 gpio_export(gpio, 0);
615
616 /* TSP_INT: XMDMADDR_7 */
617 gpio = EXYNOS4_GPE1(7);
618 gpio_request(gpio, "TSP_INT");
619
620 s5p_register_gpio_interrupt(gpio);
621 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
622 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
623 i2c3_devs[0].irq = gpio_to_irq(gpio);
624}
625
626
b908af44
MS		 627/* GPIO I2C 12 (3 Touchkey) */
628static uint32_t touchkey_keymap[] = {
629 /* MCS_KEY_MAP(value, keycode) */
630 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
631 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
632};
633
634static struct mcs_platform_data touchkey_data = {
635 .keymap = touchkey_keymap,
636 .keymap_size = ARRAY_SIZE(touchkey_keymap),
637 .key_maxval = 2,
638};
639
640/* GPIO I2C 3_TOUCH 2.8V */
641#define I2C_GPIO_BUS_12 12
642static struct i2c_gpio_platform_data i2c_gpio12_data = {
643 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
644 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
645};
646
647static struct platform_device i2c_gpio12 = {
648 .name = "i2c-gpio",
649 .id = I2C_GPIO_BUS_12,
650 .dev = {
651 .platform_data = &i2c_gpio12_data,
652 },
653};
654
655static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
656 {
657 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
658 .platform_data = &touchkey_data,
659 },
660};
661
662static void __init universal_touchkey_init(void)
663{
664 int gpio;
665
666 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
667 gpio_request(gpio, "3_TOUCH_INT");
668 s5p_register_gpio_interrupt(gpio);
669 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
670 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
671
672 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
673 gpio_request(gpio, "3_TOUCH_EN");
674 gpio_direction_output(gpio, 1);
675}
676
05132182
SN		 677static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
678 .frequency = 300 * 1000,
679 .sda_delay = 200,
680};
681
4d838ec0 682/* GPIO KEYS */
34d79315
KP		 683static struct gpio_keys_button universal_gpio_keys_tables[] = {
684 {
685 .code = KEY_VOLUMEUP,
d11135ca 686 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
34d79315
KP		 687 .desc = "gpio-keys: KEY_VOLUMEUP",
688 .type = EV_KEY,
689 .active_low = 1,
690 .debounce_interval = 1,
691 }, {
692 .code = KEY_VOLUMEDOWN,
d11135ca 693 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
34d79315
KP		 694 .desc = "gpio-keys: KEY_VOLUMEDOWN",
695 .type = EV_KEY,
696 .active_low = 1,
697 .debounce_interval = 1,
698 }, {
699 .code = KEY_CONFIG,
d11135ca 700 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
34d79315
KP		 701 .desc = "gpio-keys: KEY_CONFIG",
702 .type = EV_KEY,
703 .active_low = 1,
704 .debounce_interval = 1,
705 }, {
706 .code = KEY_CAMERA,
d11135ca 707 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
34d79315
KP		 708 .desc = "gpio-keys: KEY_CAMERA",
709 .type = EV_KEY,
710 .active_low = 1,
711 .debounce_interval = 1,
712 }, {
713 .code = KEY_OK,
d11135ca 714 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
34d79315
KP		 715 .desc = "gpio-keys: KEY_OK",
716 .type = EV_KEY,
717 .active_low = 1,
718 .debounce_interval = 1,
719 },
720};
721
722static struct gpio_keys_platform_data universal_gpio_keys_data = {
723 .buttons = universal_gpio_keys_tables,
724 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
725};
726
727static struct platform_device universal_gpio_keys = {
728 .name = "gpio-keys",
729 .dev = {
730 .platform_data = &universal_gpio_keys_data,
731 },
732};
733
a8928ce7
KP		 734/* eMMC */
735static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
736 .max_width = 8,
737 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
738 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
739 MMC_CAP_DISABLE),
740 .cd_type = S3C_SDHCI_CD_PERMANENT,
741 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
742};
743
744static struct regulator_consumer_supply mmc0_supplies[] = {
745 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
746};
747
748static struct regulator_init_data mmc0_fixed_voltage_init_data = {
749 .constraints = {
750 .name = "VMEM_VDD_2.8V",
751 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
752 },
753 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
754 .consumer_supplies = mmc0_supplies,
755};
756
757static struct fixed_voltage_config mmc0_fixed_voltage_config = {
758 .supply_name = "MASSMEMORY_EN",
759 .microvolts = 2800000,
d11135ca 760 .gpio = EXYNOS4_GPE1(3),
a8928ce7
KP		 761 .enable_high = true,
762 .init_data = &mmc0_fixed_voltage_init_data,
763};
764
765static struct platform_device mmc0_fixed_voltage = {
766 .name = "reg-fixed-voltage",
05132182 767 .id = FIXED_REG_ID_MMC0,
a8928ce7
KP		 768 .dev = {
769 .platform_data = &mmc0_fixed_voltage_config,
770 },
771};
772
773/* SD */
774static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
775 .max_width = 4,
776 .host_caps = MMC_CAP_4_BIT_DATA |
777 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
778 MMC_CAP_DISABLE,
d11135ca 779 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
a8928ce7
KP		 780 .ext_cd_gpio_invert = 1,
781 .cd_type = S3C_SDHCI_CD_GPIO,
782 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
783};
784
785/* WiFi */
786static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
787 .max_width = 4,
788 .host_caps = MMC_CAP_4_BIT_DATA |
789 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
790 MMC_CAP_DISABLE,
791 .cd_type = S3C_SDHCI_CD_EXTERNAL,
792};
793
794static void __init universal_sdhci_init(void)
795{
796 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
797 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
798 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
799}
800
3b7998f5
KP		 801/* I2C1 */
802static struct i2c_board_info i2c1_devs[] __initdata = {
803 /* Gyro, To be updated */
804};
805
f3f5bfe2
MS		 806/* Frame Buffer */
807static struct s3c_fb_pd_win universal_fb_win0 = {
808 .win_mode = {
809 .left_margin = 16,
810 .right_margin = 16,
811 .upper_margin = 2,
812 .lower_margin = 28,
813 .hsync_len = 2,
814 .vsync_len = 1,
815 .xres = 480,
816 .yres = 800,
817 .refresh = 55,
818 },
819 .max_bpp = 32,
820 .default_bpp = 16,
821};
822
823static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
824 .win[0] = &universal_fb_win0,
825 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
826 VIDCON0_CLKSEL_LCD,
827 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
828 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
829 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
830};
831
05132182
SN		 832static struct regulator_consumer_supply cam_i_core_supply =
833 REGULATOR_SUPPLY("core", "0-001f");
834
835static struct regulator_init_data cam_i_core_reg_init_data = {
836 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
837 .num_consumer_supplies = 1,
838 .consumer_supplies = &cam_i_core_supply,
839};
840
841static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
842 .supply_name = "CAM_I_CORE_1.2V",
843 .microvolts = 1200000,
844 .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
845 .enable_high = 1,
846 .init_data = &cam_i_core_reg_init_data,
847};
848
849static struct platform_device cam_i_core_fixed_reg_dev = {
850 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
851 .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
852};
853
854static struct regulator_consumer_supply cam_s_if_supply =
855 REGULATOR_SUPPLY("d_sensor", "0-001f");
856
857static struct regulator_init_data cam_s_if_reg_init_data = {
858 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
859 .num_consumer_supplies = 1,
860 .consumer_supplies = &cam_s_if_supply,
861};
862
863static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
864 .supply_name = "CAM_S_IF_1.8V",
865 .microvolts = 1800000,
866 .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
867 .enable_high = 1,
868 .init_data = &cam_s_if_reg_init_data,
869};
870
871static struct platform_device cam_s_if_fixed_reg_dev = {
872 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
873 .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
874};
875
876static struct s5p_platform_mipi_csis mipi_csis_platdata = {
877 .clk_rate = 166000000UL,
878 .lanes = 2,
879 .alignment = 32,
880 .hs_settle = 12,
881 .phy_enable = s5p_csis_phy_enable,
882};
883
884#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
885#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
886#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
887
888static int m5mols_set_power(struct device *dev, int on)
889{
890 gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
891 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
892 return 0;
893}
894
895static struct m5mols_platform_data m5mols_platdata = {
896 .gpio_reset = GPIO_CAM_MEGA_nRST,
897 .reset_polarity = 0,
898 .set_power = m5mols_set_power,
899};
900
901static struct i2c_board_info m5mols_board_info = {
902 I2C_BOARD_INFO("M5MOLS", 0x1F),
903 .platform_data = &m5mols_platdata,
904};
905
906static struct s5p_fimc_isp_info universal_camera_sensors[] = {
907 {
908 .mux_id = 0,
909 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
910 V4L2_MBUS_VSYNC_ACTIVE_LOW,
911 .bus_type = FIMC_MIPI_CSI2,
912 .board_info = &m5mols_board_info,
913 .i2c_bus_num = 0,
914 .clk_frequency = 21600000UL,
915 .csi_data_align = 32,
916 },
917};
918
919static struct s5p_platform_fimc fimc_md_platdata = {
920 .isp_info = universal_camera_sensors,
921 .num_clients = ARRAY_SIZE(universal_camera_sensors),
922};
923
05132182
SN		 924static struct gpio universal_camera_gpios[] = {
925 { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
926 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
927 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
928 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
929};
930
931static void universal_camera_init(void)
932{
933 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
934 &s5p_device_mipi_csis0);
935 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
936 &s5p_device_fimc_md);
937
938 if (gpio_request_array(universal_camera_gpios,
939 ARRAY_SIZE(universal_camera_gpios))) {
940 pr_err("%s: GPIO request failed\n", __func__);
941 return;
942 }
943
944 if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
945 m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
946 else
947 pr_err("Failed to configure 8M_ISP_INT GPIO\n");
948
949 /* Free GPIOs controlled directly by the sensor drivers. */
950 gpio_free(GPIO_CAM_MEGA_nRST);
951 gpio_free(GPIO_CAM_8M_ISP_INT);
952
953 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
954 pr_err("Camera port A setup failed\n");
955}
956
34d79315 957static struct platform_device *universal_devices[] __initdata = {
a8928ce7 958 /* Samsung Platform Devices */
05132182 959 &s5p_device_mipi_csis0,
edd967b8
MS		 960 &s5p_device_fimc0,
961 &s5p_device_fimc1,
962 &s5p_device_fimc2,
963 &s5p_device_fimc3,
a8928ce7
KP		 964 &mmc0_fixed_voltage,
965 &s3c_device_hsmmc0,
966 &s3c_device_hsmmc2,
967 &s3c_device_hsmmc3,
05132182 968 &s3c_device_i2c0,
0b398b69 969 &s3c_device_i2c3,
4d838ec0 970 &s3c_device_i2c5,
d737cf29
TS		 971 &s5p_device_i2c_hdmiphy,
972 &hdmi_fixed_voltage,
973 &exynos4_device_pd[PD_TV],
974 &s5p_device_hdmi,
975 &s5p_device_sdo,
976 &s5p_device_mixer,
a8928ce7
KP		 977
978 /* Universal Devices */
b908af44 979 &i2c_gpio12,
34d79315 980 &universal_gpio_keys,
acf5eda9 981 &s5p_device_onenand,
f3f5bfe2 982 &s5p_device_fimd0,
b14f04db
KD		 983 &s5p_device_mfc,
984 &s5p_device_mfc_l,
985 &s5p_device_mfc_r,
986 &exynos4_device_pd[PD_MFC],
f3f5bfe2 987 &exynos4_device_pd[PD_LCD0],
05132182
SN		 988 &exynos4_device_pd[PD_CAM],
989 &cam_i_core_fixed_reg_dev,
990 &cam_s_if_fixed_reg_dev,
991 &s5p_device_fimc_md,
34d79315
KP		 992};
993
516607d6
KP		 994static void __init universal_map_io(void)
995{
cc511b8d 996 exynos_init_io(NULL, 0);
516607d6
KP		 997 s3c24xx_init_clocks(24000000);
998 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
999}
1000
d737cf29
TS		 1001void s5p_tv_setup(void)
1002{
1003 /* direct HPD to HDMI chip */
1004 gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
1005
1006 gpio_direction_input(EXYNOS4_GPX3(7));
1007 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1008 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1009
1010 /* setup dependencies between TV devices */
1011 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
1012 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
1013}
1014
b14f04db
KD		 1015static void __init universal_reserve(void)
1016{
1017 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1018}
1019
516607d6
KP		 1020static void __init universal_machine_init(void)
1021{
a8928ce7 1022 universal_sdhci_init();
d737cf29 1023 s5p_tv_setup();
a8928ce7 1024
05132182 1025 s3c_i2c0_set_platdata(&universal_i2c0_platdata);
3b7998f5
KP		 1026 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
1027
0b398b69
MS		 1028 universal_tsp_init();
1029 s3c_i2c3_set_platdata(NULL);
1030 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1031
4d838ec0 1032 s3c_i2c5_set_platdata(NULL);
d737cf29 1033 s5p_i2c_hdmiphy_set_platdata(NULL);
4d838ec0
MS		 1034 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1035
f3f5bfe2
MS		 1036 s5p_fimd0_set_platdata(&universal_lcd_pdata);
1037
b908af44
MS		 1038 universal_touchkey_init();
1039 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
1040 ARRAY_SIZE(i2c_gpio12_devs));
1041
05132182
SN		 1042 universal_camera_init();
1043
34d79315
KP		 1044 /* Last */
1045 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
05132182 1046
b14f04db 1047 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
f3f5bfe2 1048 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
05132182
SN		 1049
1050 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1051 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1052 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1053 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1054 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
516607d6
KP		 1055}
1056
1057MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1058 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
2be5a4a7 1059 .atag_offset = 0x100,
d11135ca 1060 .init_irq = exynos4_init_irq,
516607d6
KP		 1061 .map_io = universal_map_io,
1062 .init_machine = universal_machine_init,
d11135ca 1063 .timer = &exynos4_timer,
b14f04db 1064 .reserve = &universal_reserve,
9eb48595 1065 .restart = exynos4_restart,
516607d6 1066MACHINE_END
Linux kernel - Deliverables
This page took 0.125135 seconds and 5 git commands to generate.