[deliverable/linux.git] / arch / arm / mach-exynos / mct.c

/* linux/arch/arm/mach-exynos4/mct.c
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 MCT(Multi-Core Timer) support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>

#include <asm/hardware/gic.h>
#include <asm/localtimer.h>

#include <plat/cpu.h>

#include <mach/map.h>
#include <mach/irqs.h>
#include <mach/regs-mct.h>
#include <asm/mach/time.h>

#define TICK_BASE_CNT	1

enum {
	MCT_INT_SPI,
	MCT_INT_PPI
};

static unsigned long clk_rate;
static unsigned int mct_int_type;

struct mct_clock_event_device {
	struct clock_event_device *evt;
	void __iomem *base;
	char name[10];
};

static void exynos4_mct_write(unsigned int value, void *addr)
{
	void __iomem *stat_addr;
	u32 mask;
	u32 i;

	__raw_writel(value, addr);

	if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
		u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
		switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
		case (u32) MCT_L_TCON_OFFSET:
			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
			mask = 1 << 3;		/* L_TCON write status */
			break;
		case (u32) MCT_L_ICNTB_OFFSET:
			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
			mask = 1 << 1;		/* L_ICNTB write status */
			break;
		case (u32) MCT_L_TCNTB_OFFSET:
			stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
			mask = 1 << 0;		/* L_TCNTB write status */
			break;
		default:
			return;
		}
	} else {
		switch ((u32) addr) {
		case (u32) EXYNOS4_MCT_G_TCON:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 16;		/* G_TCON write status */
			break;
		case (u32) EXYNOS4_MCT_G_COMP0_L:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 0;		/* G_COMP0_L write status */
			break;
		case (u32) EXYNOS4_MCT_G_COMP0_U:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 1;		/* G_COMP0_U write status */
			break;
		case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
			stat_addr = EXYNOS4_MCT_G_WSTAT;
			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
			break;
		case (u32) EXYNOS4_MCT_G_CNT_L:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 0;		/* G_CNT_L write status */
			break;
		case (u32) EXYNOS4_MCT_G_CNT_U:
			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
			mask = 1 << 1;		/* G_CNT_U write status */
			break;
		default:
			return;
		}
	}

	/* Wait maximum 1 ms until written values are applied */
	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
		if (__raw_readl(stat_addr) & mask) {
			__raw_writel(mask, stat_addr);
			return;
		}

	panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
}

/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
	u32 reg;

	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);

	reg = __raw_readl(EXYNOS4_MCT_G_TCON);
	reg |= MCT_G_TCON_START;
	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}

static cycle_t exynos4_frc_read(struct clocksource *cs)
{
	unsigned int lo, hi;
	u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);

	do {
		hi = hi2;
		lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
		hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
	} while (hi != hi2);

	return ((cycle_t)hi << 32) | lo;
}

static void exynos4_frc_resume(struct clocksource *cs)
{
	exynos4_mct_frc_start(0, 0);
}

struct clocksource mct_frc = {
	.name		= "mct-frc",
	.rating		= 400,
	.read		= exynos4_frc_read,
	.mask		= CLOCKSOURCE_MASK(64),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= exynos4_frc_resume,
};

static void __init exynos4_clocksource_init(void)
{
	exynos4_mct_frc_start(0, 0);

	if (clocksource_register_hz(&mct_frc, clk_rate))
		panic("%s: can't register clocksource\n", mct_frc.name);
}

static void exynos4_mct_comp0_stop(void)
{
	unsigned int tcon;

	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);

	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}

static void exynos4_mct_comp0_start(enum clock_event_mode mode,
				    unsigned long cycles)
{
	unsigned int tcon;
	cycle_t comp_cycle;

	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);

	if (mode == CLOCK_EVT_MODE_PERIODIC) {
		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	}

	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);

	tcon |= MCT_G_TCON_COMP0_ENABLE;
	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}

static int exynos4_comp_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	exynos4_mct_comp0_start(evt->mode, cycles);

	return 0;
}

static void exynos4_comp_set_mode(enum clock_event_mode mode,
				  struct clock_event_device *evt)
{
	unsigned long cycles_per_jiffy;
	exynos4_mct_comp0_stop();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device mct_comp_device = {
	.name		= "mct-comp",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating		= 250,
	.set_next_event	= exynos4_comp_set_next_event,
	.set_mode	= exynos4_comp_set_mode,
};

static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_comp_event_irq = {
	.name		= "mct_comp_irq",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= exynos4_mct_comp_isr,
	.dev_id		= &mct_comp_device,
};

static void exynos4_clockevent_init(void)
{
	clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
	mct_comp_device.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &mct_comp_device);
	mct_comp_device.min_delta_ns =
		clockevent_delta2ns(0xf, &mct_comp_device);
	mct_comp_device.cpumask = cpumask_of(0);
	clockevents_register_device(&mct_comp_device);

	if (soc_is_exynos5250())
		setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
	else
		setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
}

#ifdef CONFIG_LOCAL_TIMERS

static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);

/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
	unsigned long tmp;
	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
	void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;

	tmp = __raw_readl(addr);
	if (tmp & mask) {
		tmp &= ~mask;
		exynos4_mct_write(tmp, addr);
	}
}

static void exynos4_mct_tick_start(unsigned long cycles,
				   struct mct_clock_event_device *mevt)
{
	unsigned long tmp;

	exynos4_mct_tick_stop(mevt);

	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */

	/* update interrupt count buffer */
	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);

	/* enable MCT tick interrupt */
	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);

	tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
	       MCT_L_TCON_INTERVAL_MODE;
	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}

static int exynos4_tick_set_next_event(unsigned long cycles,
				       struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);

	exynos4_mct_tick_start(cycles, mevt);

	return 0;
}

static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
					 struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
	unsigned long cycles_per_jiffy;

	exynos4_mct_tick_stop(mevt);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		cycles_per_jiffy =
			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
{
	struct clock_event_device *evt = mevt->evt;

	/*
	 * This is for supporting oneshot mode.
	 * Mct would generate interrupt periodically
	 * without explicit stopping.
	 */
	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
		exynos4_mct_tick_stop(mevt);

	/* Clear the MCT tick interrupt */
	if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
		return 1;
	} else {
		return 0;
	}
}

static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
	struct mct_clock_event_device *mevt = dev_id;
	struct clock_event_device *evt = mevt->evt;

	exynos4_mct_tick_clear(mevt);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mct_tick0_event_irq = {
	.name		= "mct_tick0_irq",
	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
	.handler	= exynos4_mct_tick_isr,
};

static struct irqaction mct_tick1_event_irq = {
	.name		= "mct_tick1_irq",
	.flags		= IRQF_TIMER | IRQF_NOBALANCING,
	.handler	= exynos4_mct_tick_isr,
};

static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
	struct mct_clock_event_device *mevt;
	unsigned int cpu = smp_processor_id();
	int mct_lx_irq;

	mevt = this_cpu_ptr(&percpu_mct_tick);
	mevt->evt = evt;

	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
	sprintf(mevt->name, "mct_tick%d", cpu);

	evt->name = mevt->name;
	evt->cpumask = cpumask_of(cpu);
	evt->set_next_event = exynos4_tick_set_next_event;
	evt->set_mode = exynos4_tick_set_mode;
	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	evt->rating = 450;

	clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
	evt->max_delta_ns =
		clockevent_delta2ns(0x7fffffff, evt);
	evt->min_delta_ns =
		clockevent_delta2ns(0xf, evt);

	clockevents_register_device(evt);

	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);

	if (mct_int_type == MCT_INT_SPI) {
		if (cpu == 0) {
			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
						EXYNOS5_IRQ_MCT_L0;
			mct_tick0_event_irq.dev_id = mevt;
			evt->irq = mct_lx_irq;
			setup_irq(mct_lx_irq, &mct_tick0_event_irq);
		} else {
			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
						EXYNOS5_IRQ_MCT_L1;
			mct_tick1_event_irq.dev_id = mevt;
			evt->irq = mct_lx_irq;
			setup_irq(mct_lx_irq, &mct_tick1_event_irq);
			irq_set_affinity(mct_lx_irq, cpumask_of(1));
		}
	} else {
		enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
	}

	return 0;
}

static void exynos4_local_timer_stop(struct clock_event_device *evt)
{
	unsigned int cpu = smp_processor_id();
	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
	if (mct_int_type == MCT_INT_SPI)
		if (cpu == 0)
			remove_irq(evt->irq, &mct_tick0_event_irq);
		else
			remove_irq(evt->irq, &mct_tick1_event_irq);
	else
		disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
}

static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
	.setup	= exynos4_local_timer_setup,
	.stop	= exynos4_local_timer_stop,
};
#endif /* CONFIG_LOCAL_TIMERS */

static void __init exynos4_timer_resources(void)
{
	struct clk *mct_clk;
	mct_clk = clk_get(NULL, "xtal");

	clk_rate = clk_get_rate(mct_clk);

#ifdef CONFIG_LOCAL_TIMERS
	if (mct_int_type == MCT_INT_PPI) {
		int err;

		err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
					 exynos4_mct_tick_isr, "MCT",
					 &percpu_mct_tick);
		WARN(err, "MCT: can't request IRQ %d (%d)\n",
		     EXYNOS_IRQ_MCT_LOCALTIMER, err);
	}

	local_timer_register(&exynos4_mct_tick_ops);
#endif /* CONFIG_LOCAL_TIMERS */
}

static void __init exynos4_timer_init(void)
{
	if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
		mct_int_type = MCT_INT_SPI;
	else
		mct_int_type = MCT_INT_PPI;

	exynos4_timer_resources();
	exynos4_clocksource_init();
	exynos4_clockevent_init();
}

struct sys_timer exynos4_timer = {
	.init		= exynos4_timer_init,
};
Commit	Line	Data
30d8bead CY	1	/* linux/arch/arm/mach-exynos4/mct.c
	2	*
	3	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	4	* http://www.samsung.com
	5	*
	6	* EXYNOS4 MCT(Multi-Core Timer) support
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/sched.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/platform_device.h>
	20	#include <linux/delay.h>
	21	#include <linux/percpu.h>
	22
3a062281	23	#include <asm/hardware/gic.h>
a8cb6041	24	#include <asm/localtimer.h>
3a062281 CY	25
	26	#include <plat/cpu.h>
	27
30d8bead	28	#include <mach/map.h>
3a062281	29	#include <mach/irqs.h>
30d8bead CY	30	#include <mach/regs-mct.h>
	31	#include <asm/mach/time.h>
	32
4d2e4d7f CY	33	#define TICK_BASE_CNT 1
4d2e4d7f CY	34
3a062281 CY	35	enum {
	36	MCT_INT_SPI,
	37	MCT_INT_PPI
	38	};
	39
30d8bead	40	static unsigned long clk_rate;
3a062281	41	static unsigned int mct_int_type;
30d8bead CY	42
	43	struct mct_clock_event_device {
	44	struct clock_event_device *evt;
	45	void __iomem *base;
c8987470	46	char name[10];
30d8bead CY	47	};
30d8bead CY	48
30d8bead CY	49	static void exynos4_mct_write(unsigned int value, void *addr)
	50	{
	51	void __iomem *stat_addr;
	52	u32 mask;
	53	u32 i;
	54
	55	__raw_writel(value, addr);
	56
c8987470 CY	57	if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
	58	u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
	59	switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
	60	case (u32) MCT_L_TCON_OFFSET:
	61	stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
	62	mask = 1 << 3; /* L_TCON write status */
	63	break;
	64	case (u32) MCT_L_ICNTB_OFFSET:
	65	stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
	66	mask = 1 << 1; /* L_ICNTB write status */
	67	break;
	68	case (u32) MCT_L_TCNTB_OFFSET:
	69	stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
	70	mask = 1 << 0; /* L_TCNTB write status */
	71	break;
	72	default:
	73	return;
	74	}
	75	} else {
	76	switch ((u32) addr) {
	77	case (u32) EXYNOS4_MCT_G_TCON:
	78	stat_addr = EXYNOS4_MCT_G_WSTAT;
	79	mask = 1 << 16; /* G_TCON write status */
	80	break;
	81	case (u32) EXYNOS4_MCT_G_COMP0_L:
	82	stat_addr = EXYNOS4_MCT_G_WSTAT;
	83	mask = 1 << 0; /* G_COMP0_L write status */
	84	break;
	85	case (u32) EXYNOS4_MCT_G_COMP0_U:
	86	stat_addr = EXYNOS4_MCT_G_WSTAT;
	87	mask = 1 << 1; /* G_COMP0_U write status */
	88	break;
	89	case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
	90	stat_addr = EXYNOS4_MCT_G_WSTAT;
	91	mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
	92	break;
	93	case (u32) EXYNOS4_MCT_G_CNT_L:
	94	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	95	mask = 1 << 0; /* G_CNT_L write status */
	96	break;
	97	case (u32) EXYNOS4_MCT_G_CNT_U:
	98	stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
	99	mask = 1 << 1; /* G_CNT_U write status */
	100	break;
	101	default:
	102	return;
	103	}
30d8bead CY	104	}
	105
	106	/* Wait maximum 1 ms until written values are applied */
	107	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
	108	if (__raw_readl(stat_addr) & mask) {
	109	__raw_writel(mask, stat_addr);
	110	return;
	111	}
	112
	113	panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
	114	}
	115
	116	/* Clocksource handling */
	117	static void exynos4_mct_frc_start(u32 hi, u32 lo)
	118	{
	119	u32 reg;
	120
	121	exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
	122	exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
	123
	124	reg = __raw_readl(EXYNOS4_MCT_G_TCON);
	125	reg \|= MCT_G_TCON_START;
	126	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
	127	}
	128
	129	static cycle_t exynos4_frc_read(struct clocksource *cs)
	130	{
	131	unsigned int lo, hi;
	132	u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
	133
	134	do {
	135	hi = hi2;
	136	lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
	137	hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
	138	} while (hi != hi2);
	139
	140	return ((cycle_t)hi << 32) \| lo;
	141	}
	142
aa421c13 CY	143	static void exynos4_frc_resume(struct clocksource *cs)
	144	{
	145	exynos4_mct_frc_start(0, 0);
	146	}
	147
30d8bead CY	148	struct clocksource mct_frc = {
	149	.name = "mct-frc",
	150	.rating = 400,
	151	.read = exynos4_frc_read,
	152	.mask = CLOCKSOURCE_MASK(64),
	153	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
aa421c13	154	.resume = exynos4_frc_resume,
30d8bead CY	155	};
	156
	157	static void __init exynos4_clocksource_init(void)
	158	{
	159	exynos4_mct_frc_start(0, 0);
	160
	161	if (clocksource_register_hz(&mct_frc, clk_rate))
	162	panic("%s: can't register clocksource\n", mct_frc.name);
	163	}
	164
	165	static void exynos4_mct_comp0_stop(void)
	166	{
	167	unsigned int tcon;
	168
	169	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
	170	tcon &= ~(MCT_G_TCON_COMP0_ENABLE \| MCT_G_TCON_COMP0_AUTO_INC);
	171
	172	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
	173	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
	174	}
	175
	176	static void exynos4_mct_comp0_start(enum clock_event_mode mode,
	177	unsigned long cycles)
	178	{
	179	unsigned int tcon;
	180	cycle_t comp_cycle;
	181
	182	tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
	183
	184	if (mode == CLOCK_EVT_MODE_PERIODIC) {
	185	tcon \|= MCT_G_TCON_COMP0_AUTO_INC;
	186	exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
	187	}
	188
	189	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
	190	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
	191	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
	192
	193	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
	194
	195	tcon \|= MCT_G_TCON_COMP0_ENABLE;
	196	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
	197	}
	198
	199	static int exynos4_comp_set_next_event(unsigned long cycles,
	200	struct clock_event_device *evt)
	201	{
	202	exynos4_mct_comp0_start(evt->mode, cycles);
	203
	204	return 0;
	205	}
	206
	207	static void exynos4_comp_set_mode(enum clock_event_mode mode,
	208	struct clock_event_device *evt)
	209	{
4d2e4d7f	210	unsigned long cycles_per_jiffy;
30d8bead CY	211	exynos4_mct_comp0_stop();
	212
	213	switch (mode) {
	214	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	215	cycles_per_jiffy =
	216	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	217	exynos4_mct_comp0_start(mode, cycles_per_jiffy);
30d8bead CY	218	break;
	219
	220	case CLOCK_EVT_MODE_ONESHOT:
	221	case CLOCK_EVT_MODE_UNUSED:
	222	case CLOCK_EVT_MODE_SHUTDOWN:
	223	case CLOCK_EVT_MODE_RESUME:
	224	break;
	225	}
	226	}
	227
	228	static struct clock_event_device mct_comp_device = {
	229	.name = "mct-comp",
	230	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	231	.rating = 250,
	232	.set_next_event = exynos4_comp_set_next_event,
	233	.set_mode = exynos4_comp_set_mode,
	234	};
	235
	236	static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
	237	{
	238	struct clock_event_device *evt = dev_id;
	239
	240	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
	241
	242	evt->event_handler(evt);
	243
	244	return IRQ_HANDLED;
	245	}
	246
	247	static struct irqaction mct_comp_event_irq = {
	248	.name = "mct_comp_irq",
	249	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	250	.handler = exynos4_mct_comp_isr,
	251	.dev_id = &mct_comp_device,
	252	};
	253
	254	static void exynos4_clockevent_init(void)
	255	{
4d2e4d7f	256	clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
30d8bead CY	257	mct_comp_device.max_delta_ns =
	258	clockevent_delta2ns(0xffffffff, &mct_comp_device);
	259	mct_comp_device.min_delta_ns =
	260	clockevent_delta2ns(0xf, &mct_comp_device);
	261	mct_comp_device.cpumask = cpumask_of(0);
	262	clockevents_register_device(&mct_comp_device);
	263
bb19a751 KK	264	if (soc_is_exynos5250())
	265	setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
	266	else
	267	setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
30d8bead CY	268	}
	269
	270	#ifdef CONFIG_LOCAL_TIMERS
991a6c7d KK	271
	272	static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
	273
30d8bead CY	274	/* Clock event handling */
	275	static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
	276	{
	277	unsigned long tmp;
	278	unsigned long mask = MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START;
	279	void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
	280
	281	tmp = __raw_readl(addr);
	282	if (tmp & mask) {
	283	tmp &= ~mask;
	284	exynos4_mct_write(tmp, addr);
	285	}
	286	}
	287
	288	static void exynos4_mct_tick_start(unsigned long cycles,
	289	struct mct_clock_event_device *mevt)
	290	{
	291	unsigned long tmp;
	292
	293	exynos4_mct_tick_stop(mevt);
	294
	295	tmp = (1 << 31) \| cycles; /* MCT_L_UPDATE_ICNTB */
	296
	297	/* update interrupt count buffer */
	298	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
	299
25985edc	300	/* enable MCT tick interrupt */
30d8bead CY	301	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
	302
	303	tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
	304	tmp \|= MCT_L_TCON_INT_START \| MCT_L_TCON_TIMER_START \|
	305	MCT_L_TCON_INTERVAL_MODE;
	306	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
	307	}
	308
	309	static int exynos4_tick_set_next_event(unsigned long cycles,
	310	struct clock_event_device *evt)
	311	{
e700e41d	312	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
30d8bead CY	313
	314	exynos4_mct_tick_start(cycles, mevt);
	315
	316	return 0;
	317	}
	318
	319	static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
	320	struct clock_event_device *evt)
	321	{
e700e41d	322	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
4d2e4d7f	323	unsigned long cycles_per_jiffy;
30d8bead CY	324
	325	exynos4_mct_tick_stop(mevt);
	326
	327	switch (mode) {
	328	case CLOCK_EVT_MODE_PERIODIC:
4d2e4d7f CY	329	cycles_per_jiffy =
	330	(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
	331	exynos4_mct_tick_start(cycles_per_jiffy, mevt);
30d8bead CY	332	break;
	333
	334	case CLOCK_EVT_MODE_ONESHOT:
	335	case CLOCK_EVT_MODE_UNUSED:
	336	case CLOCK_EVT_MODE_SHUTDOWN:
	337	case CLOCK_EVT_MODE_RESUME:
	338	break;
	339	}
	340	}
	341
c8987470	342	static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
30d8bead	343	{
30d8bead CY	344	struct clock_event_device *evt = mevt->evt;
	345
	346	/*
	347	* This is for supporting oneshot mode.
	348	* Mct would generate interrupt periodically
	349	* without explicit stopping.
	350	*/
	351	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
	352	exynos4_mct_tick_stop(mevt);
	353
	354	/* Clear the MCT tick interrupt */
3a062281 CY	355	if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
	356	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
	357	return 1;
	358	} else {
	359	return 0;
	360	}
	361	}
	362
	363	static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
	364	{
	365	struct mct_clock_event_device *mevt = dev_id;
	366	struct clock_event_device *evt = mevt->evt;
	367
	368	exynos4_mct_tick_clear(mevt);
30d8bead CY	369
	370	evt->event_handler(evt);
	371
	372	return IRQ_HANDLED;
	373	}
	374
	375	static struct irqaction mct_tick0_event_irq = {
	376	.name = "mct_tick0_irq",
	377	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	378	.handler = exynos4_mct_tick_isr,
	379	};
	380
	381	static struct irqaction mct_tick1_event_irq = {
	382	.name = "mct_tick1_irq",
	383	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	384	.handler = exynos4_mct_tick_isr,
	385	};
	386
a8cb6041	387	static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
30d8bead	388	{
e700e41d	389	struct mct_clock_event_device *mevt;
30d8bead	390	unsigned int cpu = smp_processor_id();
eeed66e3	391	int mct_lx_irq;
30d8bead	392
e700e41d MZ	393	mevt = this_cpu_ptr(&percpu_mct_tick);
e700e41d MZ	394	mevt->evt = evt;
30d8bead	395
e700e41d MZ	396	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
e700e41d MZ	397	sprintf(mevt->name, "mct_tick%d", cpu);
30d8bead	398
e700e41d	399	evt->name = mevt->name;
30d8bead CY	400	evt->cpumask = cpumask_of(cpu);
	401	evt->set_next_event = exynos4_tick_set_next_event;
	402	evt->set_mode = exynos4_tick_set_mode;
	403	evt->features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	404	evt->rating = 450;
	405
4d2e4d7f	406	clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5);
30d8bead CY	407	evt->max_delta_ns =
	408	clockevent_delta2ns(0x7fffffff, evt);
	409	evt->min_delta_ns =
	410	clockevent_delta2ns(0xf, evt);
	411
	412	clockevents_register_device(evt);
	413
4d2e4d7f	414	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
30d8bead	415
3a062281 CY	416	if (mct_int_type == MCT_INT_SPI) {
3a062281 CY	417	if (cpu == 0) {
eeed66e3 CY	418	mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
eeed66e3 CY	419	EXYNOS5_IRQ_MCT_L0;
e700e41d	420	mct_tick0_event_irq.dev_id = mevt;
eeed66e3 CY	421	evt->irq = mct_lx_irq;
eeed66e3 CY	422	setup_irq(mct_lx_irq, &mct_tick0_event_irq);
3a062281	423	} else {
eeed66e3 CY	424	mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
eeed66e3 CY	425	EXYNOS5_IRQ_MCT_L1;
e700e41d	426	mct_tick1_event_irq.dev_id = mevt;
eeed66e3 CY	427	evt->irq = mct_lx_irq;
	428	setup_irq(mct_lx_irq, &mct_tick1_event_irq);
	429	irq_set_affinity(mct_lx_irq, cpumask_of(1));
3a062281	430	}
30d8bead	431	} else {
bb19a751	432	enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
30d8bead	433	}
4d487d7e KK	434
4d487d7e KK	435	return 0;
30d8bead CY	436	}
30d8bead CY	437
a8cb6041	438	static void exynos4_local_timer_stop(struct clock_event_device *evt)
30d8bead	439	{
e248cd5d	440	unsigned int cpu = smp_processor_id();
28af690a	441	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
e700e41d	442	if (mct_int_type == MCT_INT_SPI)
e248cd5d ADK	443	if (cpu == 0)
	444	remove_irq(evt->irq, &mct_tick0_event_irq);
	445	else
	446	remove_irq(evt->irq, &mct_tick1_event_irq);
e700e41d	447	else
bb19a751	448	disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
30d8bead	449	}
a8cb6041 MZ	450
	451	static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
	452	.setup = exynos4_local_timer_setup,
	453	.stop = exynos4_local_timer_stop,
	454	};
30d8bead CY	455	#endif /* CONFIG_LOCAL_TIMERS */
	456
	457	static void __init exynos4_timer_resources(void)
	458	{
	459	struct clk *mct_clk;
	460	mct_clk = clk_get(NULL, "xtal");
	461
	462	clk_rate = clk_get_rate(mct_clk);
e700e41d	463
991a6c7d	464	#ifdef CONFIG_LOCAL_TIMERS
e700e41d MZ	465	if (mct_int_type == MCT_INT_PPI) {
	466	int err;
	467
bb19a751	468	err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
e700e41d MZ	469	exynos4_mct_tick_isr, "MCT",
	470	&percpu_mct_tick);
	471	WARN(err, "MCT: can't request IRQ %d (%d)\n",
bb19a751	472	EXYNOS_IRQ_MCT_LOCALTIMER, err);
e700e41d	473	}
a8cb6041 MZ	474
a8cb6041 MZ	475	local_timer_register(&exynos4_mct_tick_ops);
991a6c7d	476	#endif /* CONFIG_LOCAL_TIMERS */
30d8bead CY	477	}
	478
	479	static void __init exynos4_timer_init(void)
	480	{
eeed66e3	481	if ((soc_is_exynos4210()) \|\| (soc_is_exynos5250()))
3a062281 CY	482	mct_int_type = MCT_INT_SPI;
	483	else
	484	mct_int_type = MCT_INT_PPI;
	485
30d8bead CY	486	exynos4_timer_resources();
	487	exynos4_clocksource_init();
	488	exynos4_clockevent_init();
	489	}
	490
	491	struct sys_timer exynos4_timer = {
	492	.init = exynos4_timer_init,
	493	};