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30d8bead CY |
1 | /* linux/arch/arm/mach-exynos4/mct.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * EXYNOS4 MCT(Multi-Core Timer) support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/sched.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/clockchips.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/percpu.h> | |
2edb36c4 | 22 | #include <linux/of.h> |
30d8bead | 23 | |
2edb36c4 | 24 | #include <asm/arch_timer.h> |
a8cb6041 | 25 | #include <asm/localtimer.h> |
3a062281 CY |
26 | |
27 | #include <plat/cpu.h> | |
28 | ||
30d8bead | 29 | #include <mach/map.h> |
3a062281 | 30 | #include <mach/irqs.h> |
30d8bead CY |
31 | #include <asm/mach/time.h> |
32 | ||
a1ba7a7a TA |
33 | #define EXYNOS4_MCTREG(x) (x) |
34 | #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) | |
35 | #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) | |
36 | #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) | |
37 | #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) | |
38 | #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) | |
39 | #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) | |
40 | #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) | |
41 | #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) | |
42 | #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) | |
43 | #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) | |
44 | #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) | |
45 | #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) | |
46 | #define EXYNOS4_MCT_L_MASK (0xffffff00) | |
47 | ||
48 | #define MCT_L_TCNTB_OFFSET (0x00) | |
49 | #define MCT_L_ICNTB_OFFSET (0x08) | |
50 | #define MCT_L_TCON_OFFSET (0x20) | |
51 | #define MCT_L_INT_CSTAT_OFFSET (0x30) | |
52 | #define MCT_L_INT_ENB_OFFSET (0x34) | |
53 | #define MCT_L_WSTAT_OFFSET (0x40) | |
54 | #define MCT_G_TCON_START (1 << 8) | |
55 | #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) | |
56 | #define MCT_G_TCON_COMP0_ENABLE (1 << 0) | |
57 | #define MCT_L_TCON_INTERVAL_MODE (1 << 2) | |
58 | #define MCT_L_TCON_INT_START (1 << 1) | |
59 | #define MCT_L_TCON_TIMER_START (1 << 0) | |
60 | ||
4d2e4d7f CY |
61 | #define TICK_BASE_CNT 1 |
62 | ||
3a062281 CY |
63 | enum { |
64 | MCT_INT_SPI, | |
65 | MCT_INT_PPI | |
66 | }; | |
67 | ||
c371dc60 TA |
68 | enum { |
69 | MCT_G0_IRQ, | |
70 | MCT_G1_IRQ, | |
71 | MCT_G2_IRQ, | |
72 | MCT_G3_IRQ, | |
73 | MCT_L0_IRQ, | |
74 | MCT_L1_IRQ, | |
75 | MCT_L2_IRQ, | |
76 | MCT_L3_IRQ, | |
77 | MCT_NR_IRQS, | |
78 | }; | |
79 | ||
a1ba7a7a | 80 | static void __iomem *reg_base; |
30d8bead | 81 | static unsigned long clk_rate; |
3a062281 | 82 | static unsigned int mct_int_type; |
c371dc60 | 83 | static int mct_irqs[MCT_NR_IRQS]; |
30d8bead CY |
84 | |
85 | struct mct_clock_event_device { | |
86 | struct clock_event_device *evt; | |
a1ba7a7a | 87 | unsigned long base; |
c8987470 | 88 | char name[10]; |
30d8bead CY |
89 | }; |
90 | ||
a1ba7a7a | 91 | static void exynos4_mct_write(unsigned int value, unsigned long offset) |
30d8bead | 92 | { |
a1ba7a7a | 93 | unsigned long stat_addr; |
30d8bead CY |
94 | u32 mask; |
95 | u32 i; | |
96 | ||
a1ba7a7a | 97 | __raw_writel(value, reg_base + offset); |
30d8bead | 98 | |
a1ba7a7a TA |
99 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
100 | stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; | |
101 | switch (offset & EXYNOS4_MCT_L_MASK) { | |
102 | case MCT_L_TCON_OFFSET: | |
c8987470 CY |
103 | mask = 1 << 3; /* L_TCON write status */ |
104 | break; | |
a1ba7a7a | 105 | case MCT_L_ICNTB_OFFSET: |
c8987470 CY |
106 | mask = 1 << 1; /* L_ICNTB write status */ |
107 | break; | |
a1ba7a7a | 108 | case MCT_L_TCNTB_OFFSET: |
c8987470 CY |
109 | mask = 1 << 0; /* L_TCNTB write status */ |
110 | break; | |
111 | default: | |
112 | return; | |
113 | } | |
114 | } else { | |
a1ba7a7a TA |
115 | switch (offset) { |
116 | case EXYNOS4_MCT_G_TCON: | |
c8987470 CY |
117 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
118 | mask = 1 << 16; /* G_TCON write status */ | |
119 | break; | |
a1ba7a7a | 120 | case EXYNOS4_MCT_G_COMP0_L: |
c8987470 CY |
121 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
122 | mask = 1 << 0; /* G_COMP0_L write status */ | |
123 | break; | |
a1ba7a7a | 124 | case EXYNOS4_MCT_G_COMP0_U: |
c8987470 CY |
125 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
126 | mask = 1 << 1; /* G_COMP0_U write status */ | |
127 | break; | |
a1ba7a7a | 128 | case EXYNOS4_MCT_G_COMP0_ADD_INCR: |
c8987470 CY |
129 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
130 | mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ | |
131 | break; | |
a1ba7a7a | 132 | case EXYNOS4_MCT_G_CNT_L: |
c8987470 CY |
133 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
134 | mask = 1 << 0; /* G_CNT_L write status */ | |
135 | break; | |
a1ba7a7a | 136 | case EXYNOS4_MCT_G_CNT_U: |
c8987470 CY |
137 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
138 | mask = 1 << 1; /* G_CNT_U write status */ | |
139 | break; | |
140 | default: | |
141 | return; | |
142 | } | |
30d8bead CY |
143 | } |
144 | ||
145 | /* Wait maximum 1 ms until written values are applied */ | |
146 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) | |
a1ba7a7a TA |
147 | if (__raw_readl(reg_base + stat_addr) & mask) { |
148 | __raw_writel(mask, reg_base + stat_addr); | |
30d8bead CY |
149 | return; |
150 | } | |
151 | ||
a1ba7a7a | 152 | panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); |
30d8bead CY |
153 | } |
154 | ||
155 | /* Clocksource handling */ | |
156 | static void exynos4_mct_frc_start(u32 hi, u32 lo) | |
157 | { | |
158 | u32 reg; | |
159 | ||
160 | exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); | |
161 | exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); | |
162 | ||
a1ba7a7a | 163 | reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead CY |
164 | reg |= MCT_G_TCON_START; |
165 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); | |
166 | } | |
167 | ||
168 | static cycle_t exynos4_frc_read(struct clocksource *cs) | |
169 | { | |
170 | unsigned int lo, hi; | |
a1ba7a7a | 171 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); |
30d8bead CY |
172 | |
173 | do { | |
174 | hi = hi2; | |
a1ba7a7a TA |
175 | lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); |
176 | hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); | |
30d8bead CY |
177 | } while (hi != hi2); |
178 | ||
179 | return ((cycle_t)hi << 32) | lo; | |
180 | } | |
181 | ||
aa421c13 CY |
182 | static void exynos4_frc_resume(struct clocksource *cs) |
183 | { | |
184 | exynos4_mct_frc_start(0, 0); | |
185 | } | |
186 | ||
30d8bead CY |
187 | struct clocksource mct_frc = { |
188 | .name = "mct-frc", | |
189 | .rating = 400, | |
190 | .read = exynos4_frc_read, | |
191 | .mask = CLOCKSOURCE_MASK(64), | |
192 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
aa421c13 | 193 | .resume = exynos4_frc_resume, |
30d8bead CY |
194 | }; |
195 | ||
196 | static void __init exynos4_clocksource_init(void) | |
197 | { | |
198 | exynos4_mct_frc_start(0, 0); | |
199 | ||
200 | if (clocksource_register_hz(&mct_frc, clk_rate)) | |
201 | panic("%s: can't register clocksource\n", mct_frc.name); | |
202 | } | |
203 | ||
204 | static void exynos4_mct_comp0_stop(void) | |
205 | { | |
206 | unsigned int tcon; | |
207 | ||
a1ba7a7a | 208 | tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead CY |
209 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); |
210 | ||
211 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); | |
212 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); | |
213 | } | |
214 | ||
215 | static void exynos4_mct_comp0_start(enum clock_event_mode mode, | |
216 | unsigned long cycles) | |
217 | { | |
218 | unsigned int tcon; | |
219 | cycle_t comp_cycle; | |
220 | ||
a1ba7a7a | 221 | tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
30d8bead CY |
222 | |
223 | if (mode == CLOCK_EVT_MODE_PERIODIC) { | |
224 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; | |
225 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); | |
226 | } | |
227 | ||
228 | comp_cycle = exynos4_frc_read(&mct_frc) + cycles; | |
229 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); | |
230 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); | |
231 | ||
232 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); | |
233 | ||
234 | tcon |= MCT_G_TCON_COMP0_ENABLE; | |
235 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); | |
236 | } | |
237 | ||
238 | static int exynos4_comp_set_next_event(unsigned long cycles, | |
239 | struct clock_event_device *evt) | |
240 | { | |
241 | exynos4_mct_comp0_start(evt->mode, cycles); | |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static void exynos4_comp_set_mode(enum clock_event_mode mode, | |
247 | struct clock_event_device *evt) | |
248 | { | |
4d2e4d7f | 249 | unsigned long cycles_per_jiffy; |
30d8bead CY |
250 | exynos4_mct_comp0_stop(); |
251 | ||
252 | switch (mode) { | |
253 | case CLOCK_EVT_MODE_PERIODIC: | |
4d2e4d7f CY |
254 | cycles_per_jiffy = |
255 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); | |
256 | exynos4_mct_comp0_start(mode, cycles_per_jiffy); | |
30d8bead CY |
257 | break; |
258 | ||
259 | case CLOCK_EVT_MODE_ONESHOT: | |
260 | case CLOCK_EVT_MODE_UNUSED: | |
261 | case CLOCK_EVT_MODE_SHUTDOWN: | |
262 | case CLOCK_EVT_MODE_RESUME: | |
263 | break; | |
264 | } | |
265 | } | |
266 | ||
267 | static struct clock_event_device mct_comp_device = { | |
268 | .name = "mct-comp", | |
269 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
270 | .rating = 250, | |
271 | .set_next_event = exynos4_comp_set_next_event, | |
272 | .set_mode = exynos4_comp_set_mode, | |
273 | }; | |
274 | ||
275 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) | |
276 | { | |
277 | struct clock_event_device *evt = dev_id; | |
278 | ||
279 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); | |
280 | ||
281 | evt->event_handler(evt); | |
282 | ||
283 | return IRQ_HANDLED; | |
284 | } | |
285 | ||
286 | static struct irqaction mct_comp_event_irq = { | |
287 | .name = "mct_comp_irq", | |
288 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | |
289 | .handler = exynos4_mct_comp_isr, | |
290 | .dev_id = &mct_comp_device, | |
291 | }; | |
292 | ||
293 | static void exynos4_clockevent_init(void) | |
294 | { | |
30d8bead | 295 | mct_comp_device.cpumask = cpumask_of(0); |
838a2ae8 SG |
296 | clockevents_config_and_register(&mct_comp_device, clk_rate, |
297 | 0xf, 0xffffffff); | |
c371dc60 | 298 | setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); |
30d8bead CY |
299 | } |
300 | ||
301 | #ifdef CONFIG_LOCAL_TIMERS | |
991a6c7d KK |
302 | |
303 | static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); | |
304 | ||
30d8bead CY |
305 | /* Clock event handling */ |
306 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) | |
307 | { | |
308 | unsigned long tmp; | |
309 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; | |
a1ba7a7a | 310 | unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; |
30d8bead | 311 | |
a1ba7a7a | 312 | tmp = __raw_readl(reg_base + offset); |
30d8bead CY |
313 | if (tmp & mask) { |
314 | tmp &= ~mask; | |
a1ba7a7a | 315 | exynos4_mct_write(tmp, offset); |
30d8bead CY |
316 | } |
317 | } | |
318 | ||
319 | static void exynos4_mct_tick_start(unsigned long cycles, | |
320 | struct mct_clock_event_device *mevt) | |
321 | { | |
322 | unsigned long tmp; | |
323 | ||
324 | exynos4_mct_tick_stop(mevt); | |
325 | ||
326 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ | |
327 | ||
328 | /* update interrupt count buffer */ | |
329 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); | |
330 | ||
25985edc | 331 | /* enable MCT tick interrupt */ |
30d8bead CY |
332 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
333 | ||
a1ba7a7a | 334 | tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); |
30d8bead CY |
335 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | |
336 | MCT_L_TCON_INTERVAL_MODE; | |
337 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); | |
338 | } | |
339 | ||
340 | static int exynos4_tick_set_next_event(unsigned long cycles, | |
341 | struct clock_event_device *evt) | |
342 | { | |
e700e41d | 343 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); |
30d8bead CY |
344 | |
345 | exynos4_mct_tick_start(cycles, mevt); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | static inline void exynos4_tick_set_mode(enum clock_event_mode mode, | |
351 | struct clock_event_device *evt) | |
352 | { | |
e700e41d | 353 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); |
4d2e4d7f | 354 | unsigned long cycles_per_jiffy; |
30d8bead CY |
355 | |
356 | exynos4_mct_tick_stop(mevt); | |
357 | ||
358 | switch (mode) { | |
359 | case CLOCK_EVT_MODE_PERIODIC: | |
4d2e4d7f CY |
360 | cycles_per_jiffy = |
361 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); | |
362 | exynos4_mct_tick_start(cycles_per_jiffy, mevt); | |
30d8bead CY |
363 | break; |
364 | ||
365 | case CLOCK_EVT_MODE_ONESHOT: | |
366 | case CLOCK_EVT_MODE_UNUSED: | |
367 | case CLOCK_EVT_MODE_SHUTDOWN: | |
368 | case CLOCK_EVT_MODE_RESUME: | |
369 | break; | |
370 | } | |
371 | } | |
372 | ||
c8987470 | 373 | static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
30d8bead | 374 | { |
30d8bead CY |
375 | struct clock_event_device *evt = mevt->evt; |
376 | ||
377 | /* | |
378 | * This is for supporting oneshot mode. | |
379 | * Mct would generate interrupt periodically | |
380 | * without explicit stopping. | |
381 | */ | |
382 | if (evt->mode != CLOCK_EVT_MODE_PERIODIC) | |
383 | exynos4_mct_tick_stop(mevt); | |
384 | ||
385 | /* Clear the MCT tick interrupt */ | |
a1ba7a7a | 386 | if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { |
3a062281 CY |
387 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
388 | return 1; | |
389 | } else { | |
390 | return 0; | |
391 | } | |
392 | } | |
393 | ||
394 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) | |
395 | { | |
396 | struct mct_clock_event_device *mevt = dev_id; | |
397 | struct clock_event_device *evt = mevt->evt; | |
398 | ||
399 | exynos4_mct_tick_clear(mevt); | |
30d8bead CY |
400 | |
401 | evt->event_handler(evt); | |
402 | ||
403 | return IRQ_HANDLED; | |
404 | } | |
405 | ||
406 | static struct irqaction mct_tick0_event_irq = { | |
407 | .name = "mct_tick0_irq", | |
408 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | |
409 | .handler = exynos4_mct_tick_isr, | |
410 | }; | |
411 | ||
412 | static struct irqaction mct_tick1_event_irq = { | |
413 | .name = "mct_tick1_irq", | |
414 | .flags = IRQF_TIMER | IRQF_NOBALANCING, | |
415 | .handler = exynos4_mct_tick_isr, | |
416 | }; | |
417 | ||
a8cb6041 | 418 | static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) |
30d8bead | 419 | { |
e700e41d | 420 | struct mct_clock_event_device *mevt; |
30d8bead CY |
421 | unsigned int cpu = smp_processor_id(); |
422 | ||
e700e41d MZ |
423 | mevt = this_cpu_ptr(&percpu_mct_tick); |
424 | mevt->evt = evt; | |
30d8bead | 425 | |
e700e41d MZ |
426 | mevt->base = EXYNOS4_MCT_L_BASE(cpu); |
427 | sprintf(mevt->name, "mct_tick%d", cpu); | |
30d8bead | 428 | |
e700e41d | 429 | evt->name = mevt->name; |
30d8bead CY |
430 | evt->cpumask = cpumask_of(cpu); |
431 | evt->set_next_event = exynos4_tick_set_next_event; | |
432 | evt->set_mode = exynos4_tick_set_mode; | |
433 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | |
434 | evt->rating = 450; | |
838a2ae8 SG |
435 | clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), |
436 | 0xf, 0x7fffffff); | |
30d8bead | 437 | |
4d2e4d7f | 438 | exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); |
30d8bead | 439 | |
3a062281 CY |
440 | if (mct_int_type == MCT_INT_SPI) { |
441 | if (cpu == 0) { | |
e700e41d | 442 | mct_tick0_event_irq.dev_id = mevt; |
c371dc60 TA |
443 | evt->irq = mct_irqs[MCT_L0_IRQ]; |
444 | setup_irq(evt->irq, &mct_tick0_event_irq); | |
3a062281 | 445 | } else { |
e700e41d | 446 | mct_tick1_event_irq.dev_id = mevt; |
c371dc60 TA |
447 | evt->irq = mct_irqs[MCT_L1_IRQ]; |
448 | setup_irq(evt->irq, &mct_tick1_event_irq); | |
449 | irq_set_affinity(evt->irq, cpumask_of(1)); | |
3a062281 | 450 | } |
30d8bead | 451 | } else { |
c371dc60 | 452 | enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); |
30d8bead | 453 | } |
4d487d7e KK |
454 | |
455 | return 0; | |
30d8bead CY |
456 | } |
457 | ||
a8cb6041 | 458 | static void exynos4_local_timer_stop(struct clock_event_device *evt) |
30d8bead | 459 | { |
e248cd5d | 460 | unsigned int cpu = smp_processor_id(); |
28af690a | 461 | evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); |
e700e41d | 462 | if (mct_int_type == MCT_INT_SPI) |
e248cd5d ADK |
463 | if (cpu == 0) |
464 | remove_irq(evt->irq, &mct_tick0_event_irq); | |
465 | else | |
466 | remove_irq(evt->irq, &mct_tick1_event_irq); | |
e700e41d | 467 | else |
c371dc60 | 468 | disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); |
30d8bead | 469 | } |
a8cb6041 MZ |
470 | |
471 | static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { | |
472 | .setup = exynos4_local_timer_setup, | |
473 | .stop = exynos4_local_timer_stop, | |
474 | }; | |
30d8bead CY |
475 | #endif /* CONFIG_LOCAL_TIMERS */ |
476 | ||
477 | static void __init exynos4_timer_resources(void) | |
478 | { | |
479 | struct clk *mct_clk; | |
480 | mct_clk = clk_get(NULL, "xtal"); | |
481 | ||
482 | clk_rate = clk_get_rate(mct_clk); | |
e700e41d | 483 | |
a1ba7a7a TA |
484 | reg_base = S5P_VA_SYSTIMER; |
485 | ||
991a6c7d | 486 | #ifdef CONFIG_LOCAL_TIMERS |
e700e41d MZ |
487 | if (mct_int_type == MCT_INT_PPI) { |
488 | int err; | |
489 | ||
c371dc60 | 490 | err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], |
e700e41d MZ |
491 | exynos4_mct_tick_isr, "MCT", |
492 | &percpu_mct_tick); | |
493 | WARN(err, "MCT: can't request IRQ %d (%d)\n", | |
c371dc60 | 494 | mct_irqs[MCT_L0_IRQ], err); |
e700e41d | 495 | } |
a8cb6041 MZ |
496 | |
497 | local_timer_register(&exynos4_mct_tick_ops); | |
991a6c7d | 498 | #endif /* CONFIG_LOCAL_TIMERS */ |
30d8bead CY |
499 | } |
500 | ||
6bb27d73 | 501 | void __init exynos4_timer_init(void) |
30d8bead | 502 | { |
2edb36c4 KK |
503 | if (soc_is_exynos5440()) { |
504 | arch_timer_of_register(); | |
505 | return; | |
506 | } | |
507 | ||
c371dc60 TA |
508 | if (soc_is_exynos4210()) { |
509 | mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; | |
510 | mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0; | |
511 | mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1; | |
3a062281 | 512 | mct_int_type = MCT_INT_SPI; |
c371dc60 TA |
513 | } else if (soc_is_exynos5250()) { |
514 | mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0; | |
515 | mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0; | |
516 | mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1; | |
517 | mct_int_type = MCT_INT_SPI; | |
518 | } else { | |
519 | mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0; | |
520 | mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER; | |
3a062281 | 521 | mct_int_type = MCT_INT_PPI; |
c371dc60 | 522 | } |
3a062281 | 523 | |
30d8bead CY |
524 | exynos4_timer_resources(); |
525 | exynos4_clocksource_init(); | |
526 | exynos4_clockevent_init(); | |
527 | } |