Commit | Line | Data |
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4552386a | 1 | /* |
7d30e8b3 KK |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
2b12b5c4 CY |
4 | * |
5 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
6 | * | |
7 | * Copyright (C) 2002 ARM Ltd. | |
8 | * All Rights Reserved | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/init.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/jiffies.h> | |
20 | #include <linux/smp.h> | |
21 | #include <linux/io.h> | |
b3205dea | 22 | #include <linux/of_address.h> |
2b12b5c4 CY |
23 | |
24 | #include <asm/cacheflush.h> | |
eb50439b | 25 | #include <asm/smp_plat.h> |
2b12b5c4 | 26 | #include <asm/smp_scu.h> |
beddf63f | 27 | #include <asm/firmware.h> |
2b12b5c4 | 28 | |
2e94ac42 PD |
29 | #include <mach/map.h> |
30 | ||
06853ae4 | 31 | #include "common.h" |
65c9a853 | 32 | #include "regs-pmu.h" |
06853ae4 | 33 | |
7d30e8b3 | 34 | extern void exynos4_secondary_startup(void); |
2b12b5c4 | 35 | |
7310d99f KK |
36 | /** |
37 | * exynos_core_power_down : power down the specified cpu | |
38 | * @cpu : the cpu to power down | |
39 | * | |
40 | * Power down the specified cpu. The sequence must be finished by a | |
41 | * call to cpu_do_idle() | |
42 | * | |
43 | */ | |
44 | void exynos_cpu_power_down(int cpu) | |
45 | { | |
944483d0 | 46 | pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); |
7310d99f KK |
47 | } |
48 | ||
49 | /** | |
50 | * exynos_cpu_power_up : power up the specified cpu | |
51 | * @cpu : the cpu to power up | |
52 | * | |
53 | * Power up the specified cpu | |
54 | */ | |
55 | void exynos_cpu_power_up(int cpu) | |
56 | { | |
944483d0 AB |
57 | pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, |
58 | EXYNOS_ARM_CORE_CONFIGURATION(cpu)); | |
7310d99f KK |
59 | } |
60 | ||
61 | /** | |
62 | * exynos_cpu_power_state : returns the power state of the cpu | |
63 | * @cpu : the cpu to retrieve the power state from | |
64 | * | |
65 | */ | |
66 | int exynos_cpu_power_state(int cpu) | |
67 | { | |
944483d0 | 68 | return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & |
7310d99f KK |
69 | S5P_CORE_LOCAL_PWR_EN); |
70 | } | |
71 | ||
72 | /** | |
73 | * exynos_cluster_power_down : power down the specified cluster | |
74 | * @cluster : the cluster to power down | |
75 | */ | |
76 | void exynos_cluster_power_down(int cluster) | |
77 | { | |
944483d0 | 78 | pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); |
7310d99f KK |
79 | } |
80 | ||
81 | /** | |
82 | * exynos_cluster_power_up : power up the specified cluster | |
83 | * @cluster : the cluster to power up | |
84 | */ | |
85 | void exynos_cluster_power_up(int cluster) | |
86 | { | |
944483d0 AB |
87 | pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN, |
88 | EXYNOS_COMMON_CONFIGURATION(cluster)); | |
7310d99f KK |
89 | } |
90 | ||
91 | /** | |
92 | * exynos_cluster_power_state : returns the power state of the cluster | |
93 | * @cluster : the cluster to retrieve the power state from | |
94 | * | |
95 | */ | |
96 | int exynos_cluster_power_state(int cluster) | |
97 | { | |
944483d0 AB |
98 | return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) & |
99 | S5P_CORE_LOCAL_PWR_EN); | |
7310d99f KK |
100 | } |
101 | ||
1f054f52 TF |
102 | static inline void __iomem *cpu_boot_reg_base(void) |
103 | { | |
104 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) | |
2e94ac42 | 105 | return pmu_base_addr + S5P_INFORM5; |
b3205dea | 106 | return sysram_base_addr; |
1f054f52 TF |
107 | } |
108 | ||
109 | static inline void __iomem *cpu_boot_reg(int cpu) | |
110 | { | |
111 | void __iomem *boot_reg; | |
112 | ||
113 | boot_reg = cpu_boot_reg_base(); | |
b3205dea SK |
114 | if (!boot_reg) |
115 | return ERR_PTR(-ENODEV); | |
1f054f52 TF |
116 | if (soc_is_exynos4412()) |
117 | boot_reg += 4*cpu; | |
86c6f148 | 118 | else if (soc_is_exynos5420() || soc_is_exynos5800()) |
1580be3d | 119 | boot_reg += 4; |
1f054f52 TF |
120 | return boot_reg; |
121 | } | |
911c29b0 | 122 | |
3705ff6d RK |
123 | /* |
124 | * Write pen_release in a way that is guaranteed to be visible to all | |
125 | * observers, irrespective of whether they're taking part in coherency | |
126 | * or not. This is necessary for the hotplug code to work reliably. | |
127 | */ | |
128 | static void write_pen_release(int val) | |
129 | { | |
130 | pen_release = val; | |
131 | smp_wmb(); | |
f45913fd | 132 | sync_cache_w(&pen_release); |
3705ff6d RK |
133 | } |
134 | ||
2b12b5c4 CY |
135 | static void __iomem *scu_base_addr(void) |
136 | { | |
137 | return (void __iomem *)(S5P_VA_SCU); | |
138 | } | |
139 | ||
140 | static DEFINE_SPINLOCK(boot_lock); | |
141 | ||
8bd26e3a | 142 | static void exynos_secondary_init(unsigned int cpu) |
2b12b5c4 | 143 | { |
2b12b5c4 CY |
144 | /* |
145 | * let the primary processor know we're out of the | |
146 | * pen, then head off into the C entry point | |
147 | */ | |
3705ff6d | 148 | write_pen_release(-1); |
2b12b5c4 CY |
149 | |
150 | /* | |
151 | * Synchronise with the boot thread. | |
152 | */ | |
153 | spin_lock(&boot_lock); | |
154 | spin_unlock(&boot_lock); | |
155 | } | |
156 | ||
8bd26e3a | 157 | static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) |
2b12b5c4 CY |
158 | { |
159 | unsigned long timeout; | |
9637f30e TF |
160 | u32 mpidr = cpu_logical_map(cpu); |
161 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
b3205dea | 162 | int ret = -ENOSYS; |
2b12b5c4 CY |
163 | |
164 | /* | |
165 | * Set synchronisation state between this boot processor | |
166 | * and the secondary one | |
167 | */ | |
168 | spin_lock(&boot_lock); | |
169 | ||
170 | /* | |
171 | * The secondary processor is waiting to be released from | |
172 | * the holding pen - release it, then wait for it to flag | |
173 | * that it has been released by resetting pen_release. | |
174 | * | |
9637f30e | 175 | * Note that "pen_release" is the hardware CPU core ID, whereas |
2b12b5c4 CY |
176 | * "cpu" is Linux's internal ID. |
177 | */ | |
9637f30e | 178 | write_pen_release(core_id); |
2b12b5c4 | 179 | |
9637f30e TF |
180 | if (!exynos_cpu_power_state(core_id)) { |
181 | exynos_cpu_power_up(core_id); | |
911c29b0 JM |
182 | timeout = 10; |
183 | ||
184 | /* wait max 10 ms until cpu1 is on */ | |
9637f30e TF |
185 | while (exynos_cpu_power_state(core_id) |
186 | != S5P_CORE_LOCAL_PWR_EN) { | |
911c29b0 JM |
187 | if (timeout-- == 0) |
188 | break; | |
189 | ||
190 | mdelay(1); | |
191 | } | |
192 | ||
193 | if (timeout == 0) { | |
194 | printk(KERN_ERR "cpu1 power enable failed"); | |
195 | spin_unlock(&boot_lock); | |
196 | return -ETIMEDOUT; | |
197 | } | |
198 | } | |
2b12b5c4 CY |
199 | /* |
200 | * Send the secondary CPU a soft interrupt, thereby causing | |
201 | * the boot monitor to read the system wide flags register, | |
202 | * and branch to the address found there. | |
203 | */ | |
2b12b5c4 CY |
204 | |
205 | timeout = jiffies + (1 * HZ); | |
206 | while (time_before(jiffies, timeout)) { | |
beddf63f TF |
207 | unsigned long boot_addr; |
208 | ||
2b12b5c4 | 209 | smp_rmb(); |
911c29b0 | 210 | |
beddf63f TF |
211 | boot_addr = virt_to_phys(exynos4_secondary_startup); |
212 | ||
213 | /* | |
214 | * Try to set boot address using firmware first | |
215 | * and fall back to boot register if it fails. | |
216 | */ | |
9637f30e | 217 | ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); |
b3205dea SK |
218 | if (ret && ret != -ENOSYS) |
219 | goto fail; | |
220 | if (ret == -ENOSYS) { | |
9637f30e | 221 | void __iomem *boot_reg = cpu_boot_reg(core_id); |
b3205dea SK |
222 | |
223 | if (IS_ERR(boot_reg)) { | |
224 | ret = PTR_ERR(boot_reg); | |
225 | goto fail; | |
226 | } | |
68ba947c | 227 | __raw_writel(boot_addr, boot_reg); |
b3205dea | 228 | } |
beddf63f | 229 | |
9637f30e | 230 | call_firmware_op(cpu_boot, core_id); |
beddf63f | 231 | |
b1cffebf | 232 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
911c29b0 | 233 | |
2b12b5c4 CY |
234 | if (pen_release == -1) |
235 | break; | |
236 | ||
237 | udelay(10); | |
238 | } | |
239 | ||
240 | /* | |
241 | * now the secondary core is starting up let it run its | |
242 | * calibrations, then wait for it to finish | |
243 | */ | |
b3205dea | 244 | fail: |
2b12b5c4 CY |
245 | spin_unlock(&boot_lock); |
246 | ||
b3205dea | 247 | return pen_release != -1 ? ret : 0; |
2b12b5c4 CY |
248 | } |
249 | ||
250 | /* | |
251 | * Initialise the CPU possible map early - this describes the CPUs | |
252 | * which may be present or become present in the system. | |
253 | */ | |
254 | ||
06853ae4 | 255 | static void __init exynos_smp_init_cpus(void) |
2b12b5c4 CY |
256 | { |
257 | void __iomem *scu_base = scu_base_addr(); | |
258 | unsigned int i, ncores; | |
259 | ||
af040ffc | 260 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) |
e9bba615 | 261 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
1897d2f3 CK |
262 | else |
263 | /* | |
264 | * CPU Nodes are passed thru DT and set_cpu_possible | |
265 | * is set by "arm_dt_init_cpu_maps". | |
266 | */ | |
267 | return; | |
2b12b5c4 CY |
268 | |
269 | /* sanity check */ | |
a06f916b RK |
270 | if (ncores > nr_cpu_ids) { |
271 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
272 | ncores, nr_cpu_ids); | |
273 | ncores = nr_cpu_ids; | |
2b12b5c4 CY |
274 | } |
275 | ||
276 | for (i = 0; i < ncores; i++) | |
277 | set_cpu_possible(i, true); | |
278 | } | |
279 | ||
06853ae4 | 280 | static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 281 | { |
1f054f52 TF |
282 | int i; |
283 | ||
1754c42e OJ |
284 | exynos_sysram_init(); |
285 | ||
af040ffc | 286 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) |
e9bba615 | 287 | scu_enable(scu_base_addr()); |
05c74a6c | 288 | |
2b12b5c4 | 289 | /* |
05c74a6c RK |
290 | * Write the address of secondary startup into the |
291 | * system-wide flags register. The boot monitor waits | |
292 | * until it receives a soft interrupt, and then the | |
293 | * secondary CPU branches to this address. | |
beddf63f TF |
294 | * |
295 | * Try using firmware operation first and fall back to | |
296 | * boot register if it fails. | |
2b12b5c4 | 297 | */ |
beddf63f | 298 | for (i = 1; i < max_cpus; ++i) { |
beddf63f | 299 | unsigned long boot_addr; |
9637f30e TF |
300 | u32 mpidr; |
301 | u32 core_id; | |
b3205dea | 302 | int ret; |
beddf63f | 303 | |
9637f30e TF |
304 | mpidr = cpu_logical_map(i); |
305 | core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); | |
beddf63f TF |
306 | boot_addr = virt_to_phys(exynos4_secondary_startup); |
307 | ||
9637f30e | 308 | ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr); |
b3205dea SK |
309 | if (ret && ret != -ENOSYS) |
310 | break; | |
311 | if (ret == -ENOSYS) { | |
9637f30e | 312 | void __iomem *boot_reg = cpu_boot_reg(core_id); |
b3205dea SK |
313 | |
314 | if (IS_ERR(boot_reg)) | |
315 | break; | |
68ba947c | 316 | __raw_writel(boot_addr, boot_reg); |
b3205dea | 317 | } |
beddf63f | 318 | } |
2b12b5c4 | 319 | } |
06853ae4 MZ |
320 | |
321 | struct smp_operations exynos_smp_ops __initdata = { | |
322 | .smp_init_cpus = exynos_smp_init_cpus, | |
323 | .smp_prepare_cpus = exynos_smp_prepare_cpus, | |
324 | .smp_secondary_init = exynos_secondary_init, | |
325 | .smp_boot_secondary = exynos_boot_secondary, | |
326 | #ifdef CONFIG_HOTPLUG_CPU | |
327 | .cpu_die = exynos_cpu_die, | |
328 | #endif | |
329 | }; |