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7d30e8b3 | 1 | /* linux/arch/arm/mach-exynos4/platsmp.c |
2b12b5c4 | 2 | * |
7d30e8b3 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
2b12b5c4 CY |
5 | * |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
7 | * | |
8 | * Copyright (C) 2002 ARM Ltd. | |
9 | * All Rights Reserved | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/io.h> | |
23 | ||
24 | #include <asm/cacheflush.h> | |
0f7b332f | 25 | #include <asm/hardware/gic.h> |
2b12b5c4 | 26 | #include <asm/smp_scu.h> |
2b12b5c4 CY |
27 | |
28 | #include <mach/hardware.h> | |
29 | #include <mach/regs-clock.h> | |
911c29b0 | 30 | #include <mach/regs-pmu.h> |
2b12b5c4 | 31 | |
56b20922 KK |
32 | #include <plat/cpu.h> |
33 | ||
7d30e8b3 | 34 | extern void exynos4_secondary_startup(void); |
2b12b5c4 | 35 | |
56b20922 KK |
36 | #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ |
37 | S5P_INFORM5 : S5P_VA_SYSRAM) | |
911c29b0 | 38 | |
2b12b5c4 CY |
39 | /* |
40 | * control for which core is the next to come out of the secondary | |
41 | * boot "holding pen" | |
42 | */ | |
43 | ||
44 | volatile int __cpuinitdata pen_release = -1; | |
45 | ||
3705ff6d RK |
46 | /* |
47 | * Write pen_release in a way that is guaranteed to be visible to all | |
48 | * observers, irrespective of whether they're taking part in coherency | |
49 | * or not. This is necessary for the hotplug code to work reliably. | |
50 | */ | |
51 | static void write_pen_release(int val) | |
52 | { | |
53 | pen_release = val; | |
54 | smp_wmb(); | |
55 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
56 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
57 | } | |
58 | ||
2b12b5c4 CY |
59 | static void __iomem *scu_base_addr(void) |
60 | { | |
61 | return (void __iomem *)(S5P_VA_SCU); | |
62 | } | |
63 | ||
64 | static DEFINE_SPINLOCK(boot_lock); | |
65 | ||
66 | void __cpuinit platform_secondary_init(unsigned int cpu) | |
67 | { | |
2b12b5c4 CY |
68 | /* |
69 | * if any interrupts are already enabled for the primary | |
70 | * core (e.g. timer irq), then they will not have been enabled | |
71 | * for us: do so | |
72 | */ | |
db0d4db2 | 73 | gic_secondary_init(0); |
2b12b5c4 CY |
74 | |
75 | /* | |
76 | * let the primary processor know we're out of the | |
77 | * pen, then head off into the C entry point | |
78 | */ | |
3705ff6d | 79 | write_pen_release(-1); |
2b12b5c4 CY |
80 | |
81 | /* | |
82 | * Synchronise with the boot thread. | |
83 | */ | |
84 | spin_lock(&boot_lock); | |
85 | spin_unlock(&boot_lock); | |
86 | } | |
87 | ||
88 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
89 | { | |
90 | unsigned long timeout; | |
91 | ||
92 | /* | |
93 | * Set synchronisation state between this boot processor | |
94 | * and the secondary one | |
95 | */ | |
96 | spin_lock(&boot_lock); | |
97 | ||
98 | /* | |
99 | * The secondary processor is waiting to be released from | |
100 | * the holding pen - release it, then wait for it to flag | |
101 | * that it has been released by resetting pen_release. | |
102 | * | |
103 | * Note that "pen_release" is the hardware CPU ID, whereas | |
104 | * "cpu" is Linux's internal ID. | |
105 | */ | |
2f41c36b | 106 | write_pen_release(cpu_logical_map(cpu)); |
2b12b5c4 | 107 | |
911c29b0 JM |
108 | if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { |
109 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | |
110 | S5P_ARM_CORE1_CONFIGURATION); | |
111 | ||
112 | timeout = 10; | |
113 | ||
114 | /* wait max 10 ms until cpu1 is on */ | |
115 | while ((__raw_readl(S5P_ARM_CORE1_STATUS) | |
116 | & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { | |
117 | if (timeout-- == 0) | |
118 | break; | |
119 | ||
120 | mdelay(1); | |
121 | } | |
122 | ||
123 | if (timeout == 0) { | |
124 | printk(KERN_ERR "cpu1 power enable failed"); | |
125 | spin_unlock(&boot_lock); | |
126 | return -ETIMEDOUT; | |
127 | } | |
128 | } | |
2b12b5c4 CY |
129 | /* |
130 | * Send the secondary CPU a soft interrupt, thereby causing | |
131 | * the boot monitor to read the system wide flags register, | |
132 | * and branch to the address found there. | |
133 | */ | |
2b12b5c4 CY |
134 | |
135 | timeout = jiffies + (1 * HZ); | |
136 | while (time_before(jiffies, timeout)) { | |
137 | smp_rmb(); | |
911c29b0 | 138 | |
f7597c02 | 139 | __raw_writel(virt_to_phys(exynos4_secondary_startup), |
911c29b0 JM |
140 | CPU1_BOOT_REG); |
141 | gic_raise_softirq(cpumask_of(cpu), 1); | |
142 | ||
2b12b5c4 CY |
143 | if (pen_release == -1) |
144 | break; | |
145 | ||
146 | udelay(10); | |
147 | } | |
148 | ||
149 | /* | |
150 | * now the secondary core is starting up let it run its | |
151 | * calibrations, then wait for it to finish | |
152 | */ | |
153 | spin_unlock(&boot_lock); | |
154 | ||
155 | return pen_release != -1 ? -ENOSYS : 0; | |
156 | } | |
157 | ||
158 | /* | |
159 | * Initialise the CPU possible map early - this describes the CPUs | |
160 | * which may be present or become present in the system. | |
161 | */ | |
162 | ||
163 | void __init smp_init_cpus(void) | |
164 | { | |
165 | void __iomem *scu_base = scu_base_addr(); | |
166 | unsigned int i, ncores; | |
167 | ||
168 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
169 | ||
170 | /* sanity check */ | |
a06f916b RK |
171 | if (ncores > nr_cpu_ids) { |
172 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | |
173 | ncores, nr_cpu_ids); | |
174 | ncores = nr_cpu_ids; | |
2b12b5c4 CY |
175 | } |
176 | ||
177 | for (i = 0; i < ncores; i++) | |
178 | set_cpu_possible(i, true); | |
0f7b332f RK |
179 | |
180 | set_smp_cross_call(gic_raise_softirq); | |
2b12b5c4 CY |
181 | } |
182 | ||
05c74a6c | 183 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 184 | { |
2b12b5c4 | 185 | |
05c74a6c RK |
186 | scu_enable(scu_base_addr()); |
187 | ||
2b12b5c4 | 188 | /* |
05c74a6c RK |
189 | * Write the address of secondary startup into the |
190 | * system-wide flags register. The boot monitor waits | |
191 | * until it receives a soft interrupt, and then the | |
192 | * secondary CPU branches to this address. | |
2b12b5c4 | 193 | */ |
f7597c02 | 194 | __raw_writel(virt_to_phys(exynos4_secondary_startup), |
56b20922 | 195 | CPU1_BOOT_REG); |
2b12b5c4 | 196 | } |