[deliverable/linux.git] / arch / arm / mach-exynos / pm.c

/*
 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - Power Management support
 *
 * Based on arch/arm/mach-s3c2410/pm.c
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>

#include <plat/pm-common.h>
#include <plat/regs-srom.h>

#include <mach/map.h>

#include "common.h"
#include "regs-pmu.h"
#include "regs-sys.h"

/**
 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
 * @hwirq: Hardware IRQ signal of the GIC
 * @mask: Mask in PMU wake-up mask register
 */
struct exynos_wkup_irq {
	unsigned int hwirq;
	u32 mask;
};

static struct sleep_save exynos5_sys_save[] = {
	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
};

static struct sleep_save exynos_core_save[] = {
	/* SROM side */
	SAVE_ITEM(S5P_SROM_BW),
	SAVE_ITEM(S5P_SROM_BC0),
	SAVE_ITEM(S5P_SROM_BC1),
	SAVE_ITEM(S5P_SROM_BC2),
	SAVE_ITEM(S5P_SROM_BC3),
};

/*
 * GIC wake-up support
 */

static u32 exynos_irqwake_intmask = 0xffffffff;

static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	{ 76, BIT(1) }, /* RTC alarm */
	{ 77, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	{ 75, BIT(1) }, /* RTC alarm */
	{ 76, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
	const struct exynos_wkup_irq *wkup_irq;

	if (soc_is_exynos5250())
		wkup_irq = exynos5250_wkup_irq;
	else
		wkup_irq = exynos4_wkup_irq;

	while (wkup_irq->mask) {
		if (wkup_irq->hwirq == data->hwirq) {
			if (!state)
				exynos_irqwake_intmask |= wkup_irq->mask;
			else
				exynos_irqwake_intmask &= ~wkup_irq->mask;
			return 0;
		}
		++wkup_irq;
	}

	return -ENOENT;
}

#define EXYNOS_BOOT_VECTOR_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			pmu_base_addr + S5P_INFORM7 : \
			(samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(sysram_base_addr + 0x24) : \
			pmu_base_addr + S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			pmu_base_addr + S5P_INFORM6 : \
			(samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(sysram_base_addr + 0x20) : \
			pmu_base_addr + S5P_INFORM1))

#define S5P_CHECK_AFTR  0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD

/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
	pmu_raw_writel(mask, S5P_WAKEUP_MASK);
}

static void exynos_cpu_set_boot_vector(long flags)
{
	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
}

void exynos_enter_aftr(void)
{
	exynos_set_wakeupmask(0x0000ff3e);
	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
	/* Set value of power down register for aftr mode */
	exynos_sys_powerdown_conf(SYS_AFTR);
}

/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];

static void exynos_cpu_save_register(void)
{
	unsigned long tmp;

	/* Save Power control register */
	asm ("mrc p15, 0, %0, c15, c0, 0"
	     : "=r" (tmp) : : "cc");

	save_arm_register[0] = tmp;

	/* Save Diagnostic register */
	asm ("mrc p15, 0, %0, c15, c0, 1"
	     : "=r" (tmp) : : "cc");

	save_arm_register[1] = tmp;
}

static void exynos_cpu_restore_register(void)
{
	unsigned long tmp;

	/* Restore Power control register */
	tmp = save_arm_register[0];

	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
		      : : "r" (tmp)
		      : "cc");

	/* Restore Diagnostic register */
	tmp = save_arm_register[1];

	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
		      : : "r" (tmp)
		      : "cc");
}

static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
	outer_flush_all();
#endif

	if (soc_is_exynos5250())
		flush_cache_all();

	/* issue the standby signal into the pm unit. */
	cpu_do_idle();

	pr_info("Failed to suspend the system\n");
	return 1; /* Aborting suspend */
}

static void exynos_pm_prepare(void)
{
	unsigned int tmp;

	/* Set wake-up mask registers */
	pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
	pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);

	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (soc_is_exynos5250()) {
		s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
		tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	}

	/* Set value of power down register for sleep mode */

	exynos_sys_powerdown_conf(SYS_SLEEP);
	pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}

static void exynos_pm_central_suspend(void)
{
	unsigned long tmp;

	/* Setting Central Sequence Register for power down mode */
	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}

static int exynos_pm_suspend(void)
{
	unsigned long tmp;

	exynos_pm_central_suspend();

	/* Setting SEQ_OPTION register */

	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		exynos_cpu_save_register();

	return 0;
}

static int exynos_pm_central_resume(void)
{
	unsigned long tmp;

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* clear the wakeup state register */
		pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
		/* No need to perform below restore code */
		return -1;
	}

	return 0;
}

static void exynos_pm_resume(void)
{
	if (exynos_pm_central_resume())
		goto early_wakeup;

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		exynos_cpu_restore_register();

	/* For release retention */

	pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	if (soc_is_exynos5250())
		s3c_pm_do_restore(exynos5_sys_save,
			ARRAY_SIZE(exynos5_sys_save));

	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		scu_enable(S5P_VA_SCU);

early_wakeup:

	/* Clear SLEEP mode set in INFORM1 */
	pmu_raw_writel(0x0, S5P_INFORM1);

	return;
}

static struct syscore_ops exynos_pm_syscore_ops = {
	.suspend	= exynos_pm_suspend,
	.resume		= exynos_pm_resume,
};

/*
 * Suspend Ops
 */

static int exynos_suspend_enter(suspend_state_t state)
{
	int ret;

	s3c_pm_debug_init();

	S3C_PMDBG("%s: suspending the system...\n", __func__);

	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
			exynos_irqwake_intmask, exynos_get_eint_wake_mask());

	if (exynos_irqwake_intmask == -1U
	    && exynos_get_eint_wake_mask() == -1U) {
		pr_err("%s: No wake-up sources!\n", __func__);
		pr_err("%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	s3c_pm_save_uarts();
	exynos_pm_prepare();
	flush_cache_all();
	s3c_pm_check_store();

	ret = cpu_suspend(0, exynos_cpu_suspend);
	if (ret)
		return ret;

	s3c_pm_restore_uarts();

	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
			pmu_raw_readl(S5P_WAKEUP_STAT));

	s3c_pm_check_restore();

	S3C_PMDBG("%s: resuming the system...\n", __func__);

	return 0;
}

static int exynos_suspend_prepare(void)
{
	s3c_pm_check_prepare();

	return 0;
}

static void exynos_suspend_finish(void)
{
	s3c_pm_check_cleanup();
}

static const struct platform_suspend_ops exynos_suspend_ops = {
	.enter		= exynos_suspend_enter,
	.prepare	= exynos_suspend_prepare,
	.finish		= exynos_suspend_finish,
	.valid		= suspend_valid_only_mem,
};

static int exynos_cpu_pm_notifier(struct notifier_block *self,
				  unsigned long cmd, void *v)
{
	int cpu = smp_processor_id();

	switch (cmd) {
	case CPU_PM_ENTER:
		if (cpu == 0) {
			exynos_pm_central_suspend();
			if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
				exynos_cpu_save_register();
		}
		break;

	case CPU_PM_EXIT:
		if (cpu == 0) {
			if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
				scu_enable(S5P_VA_SCU);
				exynos_cpu_restore_register();
			}
			exynos_pm_central_resume();
		}
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos_cpu_pm_notifier_block = {
	.notifier_call = exynos_cpu_pm_notifier,
};

void __init exynos_pm_init(void)
{
	u32 tmp;

	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);

	/* Platform-specific GIC callback */
	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;

	/* All wakeup disable */
	tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
	tmp |= ((0xFF << 8) | (0x1F << 1));
	pmu_raw_writel(tmp, S5P_WAKEUP_MASK);

	register_syscore_ops(&exynos_pm_syscore_ops);
	suspend_set_ops(&exynos_suspend_ops);
}
Commit	Line	Data
c9347101 JL	1	/*
c9347101 JL	2	* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
1663895c JL	3	* http://www.samsung.com
1663895c JL	4	*
c9347101	5	* EXYNOS - Power Management support
1663895c JL	6	*
	7	* Based on arch/arm/mach-s3c2410/pm.c
	8	* Copyright (c) 2006 Simtec Electronics
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/suspend.h>
bb072c3c	18	#include <linux/syscore_ops.h>
85f9f908	19	#include <linux/cpu_pm.h>
1663895c	20	#include <linux/io.h>
dd8ac696	21	#include <linux/irqchip/arm-gic.h>
56c03d91 JL	22	#include <linux/err.h>
56c03d91 JL	23	#include <linux/clk.h>
1663895c JL	24
	25	#include <asm/cacheflush.h>
	26	#include <asm/hardware/cache-l2x0.h>
63b870f1	27	#include <asm/smp_scu.h>
d710aa31	28	#include <asm/suspend.h>
1663895c	29
d710aa31	30	#include <plat/pm-common.h>
b93cb91b	31	#include <plat/regs-srom.h>
1663895c	32
9c9239af	33	#include <mach/map.h>
ccd458c1 KK	34
ccd458c1 KK	35	#include "common.h"
65c9a853	36	#include "regs-pmu.h"
318fd20b	37	#include "regs-sys.h"
1663895c	38
dd8ac696 TF	39	/**
	40	* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
	41	* @hwirq: Hardware IRQ signal of the GIC
	42	* @mask: Mask in PMU wake-up mask register
	43	*/
	44	struct exynos_wkup_irq {
	45	unsigned int hwirq;
	46	u32 mask;
	47	};
	48
86ffb0e8 AK	49	static struct sleep_save exynos5_sys_save[] = {
	50	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
	51	};
	52
c9347101	53	static struct sleep_save exynos_core_save[] = {
b93cb91b MH	54	/* SROM side */
	55	SAVE_ITEM(S5P_SROM_BW),
	56	SAVE_ITEM(S5P_SROM_BC0),
	57	SAVE_ITEM(S5P_SROM_BC1),
	58	SAVE_ITEM(S5P_SROM_BC2),
	59	SAVE_ITEM(S5P_SROM_BC3),
1663895c JL	60	};
1663895c JL	61
dd8ac696 TF	62	/*
	63	* GIC wake-up support
	64	*/
	65
d710aa31	66	static u32 exynos_irqwake_intmask = 0xffffffff;
1663895c	67
dd8ac696 TF	68	static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	69	{ 76, BIT(1) }, /* RTC alarm */
	70	{ 77, BIT(2) }, /* RTC tick */
	71	{ /* sentinel */ },
	72	};
	73
	74	static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	75	{ 75, BIT(1) }, /* RTC alarm */
	76	{ 76, BIT(2) }, /* RTC tick */
	77	{ /* sentinel */ },
	78	};
	79
	80	static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
	81	{
	82	const struct exynos_wkup_irq *wkup_irq;
	83
	84	if (soc_is_exynos5250())
	85	wkup_irq = exynos5250_wkup_irq;
	86	else
	87	wkup_irq = exynos4_wkup_irq;
	88
	89	while (wkup_irq->mask) {
	90	if (wkup_irq->hwirq == data->hwirq) {
	91	if (!state)
	92	exynos_irqwake_intmask \|= wkup_irq->mask;
	93	else
	94	exynos_irqwake_intmask &= ~wkup_irq->mask;
	95	return 0;
	96	}
	97	++wkup_irq;
	98	}
	99
	100	return -ENOENT;
	101	}
	102
3681bafe	103	#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
2e94ac42 PD	104	pmu_base_addr + S5P_INFORM7 : \
	105	(samsung_rev() == EXYNOS4210_REV_1_0 ? \
	106	(sysram_base_addr + 0x24) : \
	107	pmu_base_addr + S5P_INFORM0))
3681bafe	108	#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
2e94ac42 PD	109	pmu_base_addr + S5P_INFORM6 : \
	110	(samsung_rev() == EXYNOS4210_REV_1_0 ? \
	111	(sysram_base_addr + 0x20) : \
	112	pmu_base_addr + S5P_INFORM1))
3681bafe	113
e30b154b DL	114	#define S5P_CHECK_AFTR 0xFCBA0D10
e30b154b DL	115	#define S5P_CHECK_SLEEP 0x00000BAD
3681bafe DL	116
	117	/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
	118	static void exynos_set_wakeupmask(long mask)
	119	{
2e94ac42	120	pmu_raw_writel(mask, S5P_WAKEUP_MASK);
3681bafe DL	121	}
	122
	123	static void exynos_cpu_set_boot_vector(long flags)
	124	{
	125	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
	126	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
	127	}
	128
	129	void exynos_enter_aftr(void)
	130	{
	131	exynos_set_wakeupmask(0x0000ff3e);
	132	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
	133	/* Set value of power down register for aftr mode */
	134	exynos_sys_powerdown_conf(SYS_AFTR);
	135	}
	136
f4ba4b01 JL	137	/* For Cortex-A9 Diagnostic and Power control register */
	138	static unsigned int save_arm_register[2];
	139
309e08c4 DL	140	static void exynos_cpu_save_register(void)
	141	{
	142	unsigned long tmp;
	143
	144	/* Save Power control register */
	145	asm ("mrc p15, 0, %0, c15, c0, 0"
	146	: "=r" (tmp) : : "cc");
	147
	148	save_arm_register[0] = tmp;
	149
	150	/* Save Diagnostic register */
	151	asm ("mrc p15, 0, %0, c15, c0, 1"
	152	: "=r" (tmp) : : "cc");
	153
	154	save_arm_register[1] = tmp;
	155	}
	156
	157	static void exynos_cpu_restore_register(void)
	158	{
	159	unsigned long tmp;
	160
	161	/* Restore Power control register */
	162	tmp = save_arm_register[0];
	163
	164	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
	165	: : "r" (tmp)
	166	: "cc");
	167
	168	/* Restore Diagnostic register */
	169	tmp = save_arm_register[1];
	170
	171	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
	172	: : "r" (tmp)
	173	: "cc");
	174	}
	175
c9347101	176	static int exynos_cpu_suspend(unsigned long arg)
1663895c	177	{
60e49ca6	178	#ifdef CONFIG_CACHE_L2X0
1663895c	179	outer_flush_all();
60e49ca6	180	#endif
1663895c	181
573e5bbe AK	182	if (soc_is_exynos5250())
	183	flush_cache_all();
	184
1663895c JL	185	/* issue the standby signal into the pm unit. */
	186	cpu_do_idle();
	187
d3fcacf5 AK	188	pr_info("Failed to suspend the system\n");
d3fcacf5 AK	189	return 1; /* Aborting suspend */
1663895c JL	190	}
1663895c JL	191
c9347101	192	static void exynos_pm_prepare(void)
1663895c	193	{
60e49ca6	194	unsigned int tmp;
1663895c	195
d710aa31	196	/* Set wake-up mask registers */
2e94ac42 PD	197	pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
2e94ac42 PD	198	pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
d710aa31	199
c9347101	200	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	201
e11d919e	202	if (soc_is_exynos5250()) {
86ffb0e8	203	s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
60e49ca6	204	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
2e94ac42	205	tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
60e49ca6	206	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
2e94ac42	207	pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
60e49ca6	208	}
1663895c JL	209
	210	/* Set value of power down register for sleep mode */
	211
7d44d2ba	212	exynos_sys_powerdown_conf(SYS_SLEEP);
2e94ac42	213	pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
1663895c JL	214
	215	/* ensure at least INFORM0 has the resume address */
	216
2e94ac42	217	pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
1663895c JL	218	}
1663895c JL	219
0ebc13e2	220	static void exynos_pm_central_suspend(void)
12974e9f JL	221	{
	222	unsigned long tmp;
	223
	224	/* Setting Central Sequence Register for power down mode */
2e94ac42	225	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
12974e9f	226	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
2e94ac42	227	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
0ebc13e2 DL	228	}
	229
	230	static int exynos_pm_suspend(void)
	231	{
	232	unsigned long tmp;
	233
	234	exynos_pm_central_suspend();
12974e9f	235
60e49ca6	236	/* Setting SEQ_OPTION register */
00a351f2	237
60e49ca6	238	tmp = (S5P_USE_STANDBY_WFI0 \| S5P_USE_STANDBY_WFE0);
2e94ac42	239	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
f4ba4b01	240
af040ffc	241	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
309e08c4	242	exynos_cpu_save_register();
f4ba4b01	243
12974e9f JL	244	return 0;
	245	}
	246
0ebc13e2	247	static int exynos_pm_central_resume(void)
1663895c	248	{
e240ab1c JL	249	unsigned long tmp;
	250
	251	/*
	252	* If PMU failed while entering sleep mode, WFI will be
	253	* ignored by PMU and then exiting cpu_do_idle().
	254	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	255	* in this situation.
	256	*/
2e94ac42	257	tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
e240ab1c JL	258	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
e240ab1c JL	259	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
2e94ac42	260	pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
d3fcacf5	261	/* clear the wakeup state register */
2e94ac42	262	pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
e240ab1c	263	/* No need to perform below restore code */
0ebc13e2	264	return -1;
e240ab1c	265	}
309e08c4	266
0ebc13e2 DL	267	return 0;
	268	}
	269
	270	static void exynos_pm_resume(void)
	271	{
	272	if (exynos_pm_central_resume())
	273	goto early_wakeup;
	274
af040ffc	275	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
309e08c4	276	exynos_cpu_restore_register();
e240ab1c	277
1663895c JL	278	/* For release retention */
1663895c JL	279
2e94ac42 PD	280	pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	281	pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	282	pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	283	pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	284	pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	285	pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	286	pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
1663895c	287
86ffb0e8 AK	288	if (soc_is_exynos5250())
	289	s3c_pm_do_restore(exynos5_sys_save,
	290	ARRAY_SIZE(exynos5_sys_save));
	291
c9347101	292	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	293
af040ffc	294	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
60e49ca6	295	scu_enable(S5P_VA_SCU);
1663895c	296
e240ab1c	297	early_wakeup:
ebee8541 IS	298
ebee8541 IS	299	/* Clear SLEEP mode set in INFORM1 */
2e94ac42	300	pmu_raw_writel(0x0, S5P_INFORM1);
ebee8541	301
e240ab1c	302	return;
1663895c JL	303	}
1663895c JL	304
c9347101 JL	305	static struct syscore_ops exynos_pm_syscore_ops = {
	306	.suspend = exynos_pm_suspend,
	307	.resume = exynos_pm_resume,
1663895c JL	308	};
1663895c JL	309
d710aa31 TF	310	/*
	311	* Suspend Ops
	312	*/
	313
	314	static int exynos_suspend_enter(suspend_state_t state)
1663895c	315	{
d710aa31 TF	316	int ret;
	317
	318	s3c_pm_debug_init();
	319
	320	S3C_PMDBG("%s: suspending the system...\n", __func__);
	321
	322	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
	323	exynos_irqwake_intmask, exynos_get_eint_wake_mask());
559ba237	324
d710aa31 TF	325	if (exynos_irqwake_intmask == -1U
	326	&& exynos_get_eint_wake_mask() == -1U) {
	327	pr_err("%s: No wake-up sources!\n", __func__);
	328	pr_err("%s: Aborting sleep\n", __func__);
	329	return -EINVAL;
	330	}
	331
	332	s3c_pm_save_uarts();
	333	exynos_pm_prepare();
	334	flush_cache_all();
	335	s3c_pm_check_store();
	336
	337	ret = cpu_suspend(0, exynos_cpu_suspend);
	338	if (ret)
	339	return ret;
	340
	341	s3c_pm_restore_uarts();
559ba237	342
d710aa31	343	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
2e94ac42	344	pmu_raw_readl(S5P_WAKEUP_STAT));
d710aa31 TF	345
	346	s3c_pm_check_restore();
	347
	348	S3C_PMDBG("%s: resuming the system...\n", __func__);
	349
	350	return 0;
	351	}
	352
	353	static int exynos_suspend_prepare(void)
	354	{
	355	s3c_pm_check_prepare();
	356
	357	return 0;
	358	}
	359
	360	static void exynos_suspend_finish(void)
	361	{
	362	s3c_pm_check_cleanup();
	363	}
	364
	365	static const struct platform_suspend_ops exynos_suspend_ops = {
	366	.enter = exynos_suspend_enter,
	367	.prepare = exynos_suspend_prepare,
	368	.finish = exynos_suspend_finish,
	369	.valid = suspend_valid_only_mem,
	370	};
	371
85f9f908 DL	372	static int exynos_cpu_pm_notifier(struct notifier_block *self,
	373	unsigned long cmd, void *v)
	374	{
	375	int cpu = smp_processor_id();
	376
	377	switch (cmd) {
	378	case CPU_PM_ENTER:
0ebc13e2 DL	379	if (cpu == 0) {
0ebc13e2 DL	380	exynos_pm_central_suspend();
af040ffc	381	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
c0c3c359	382	exynos_cpu_save_register();
0ebc13e2	383	}
85f9f908 DL	384	break;
	385
	386	case CPU_PM_EXIT:
795537da	387	if (cpu == 0) {
af040ffc	388	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
795537da	389	scu_enable(S5P_VA_SCU);
c0c3c359 AK	390	exynos_cpu_restore_register();
c0c3c359 AK	391	}
0ebc13e2	392	exynos_pm_central_resume();
795537da	393	}
85f9f908 DL	394	break;
	395	}
	396
	397	return NOTIFY_OK;
	398	}
	399
	400	static struct notifier_block exynos_cpu_pm_notifier_block = {
	401	.notifier_call = exynos_cpu_pm_notifier,
	402	};
	403
d710aa31 TF	404	void __init exynos_pm_init(void)
	405	{
	406	u32 tmp;
559ba237	407
85f9f908 DL	408	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
85f9f908 DL	409
dd8ac696 TF	410	/* Platform-specific GIC callback */
	411	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
	412
559ba237	413	/* All wakeup disable */
2e94ac42	414	tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
559ba237	415	tmp \|= ((0xFF << 8) \| (0x1F << 1));
2e94ac42	416	pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
e085cad6	417
c9347101	418	register_syscore_ops(&exynos_pm_syscore_ops);
d710aa31	419	suspend_set_ops(&exynos_suspend_ops);
1663895c	420	}