Commit | Line | Data |
---|---|---|
c9347101 | 1 | /* |
0d713cf1 | 2 | * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. |
1663895c JL |
3 | * http://www.samsung.com |
4 | * | |
c9347101 | 5 | * EXYNOS - Power Management support |
1663895c JL |
6 | * |
7 | * Based on arch/arm/mach-s3c2410/pm.c | |
8 | * Copyright (c) 2006 Simtec Electronics | |
9 | * Ben Dooks <ben@simtec.co.uk> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/suspend.h> | |
85f9f908 | 18 | #include <linux/cpu_pm.h> |
1663895c | 19 | #include <linux/io.h> |
a4781441 | 20 | #include <linux/of.h> |
2262d6ef PD |
21 | #include <linux/soc/samsung/exynos-regs-pmu.h> |
22 | #include <linux/soc/samsung/exynos-pmu.h> | |
1663895c | 23 | |
2b9d9c32 | 24 | #include <asm/firmware.h> |
63b870f1 | 25 | #include <asm/smp_scu.h> |
d710aa31 | 26 | #include <asm/suspend.h> |
af997114 | 27 | #include <asm/cacheflush.h> |
1663895c | 28 | |
32b0aa9a PD |
29 | #include <mach/map.h> |
30 | ||
ccd458c1 | 31 | #include "common.h" |
1663895c | 32 | |
134abc29 BZ |
33 | static inline void __iomem *exynos_boot_vector_addr(void) |
34 | { | |
35 | if (samsung_rev() == EXYNOS4210_REV_1_1) | |
36 | return pmu_base_addr + S5P_INFORM7; | |
37 | else if (samsung_rev() == EXYNOS4210_REV_1_0) | |
38 | return sysram_base_addr + 0x24; | |
39 | return pmu_base_addr + S5P_INFORM0; | |
40 | } | |
41 | ||
42 | static inline void __iomem *exynos_boot_vector_flag(void) | |
43 | { | |
44 | if (samsung_rev() == EXYNOS4210_REV_1_1) | |
45 | return pmu_base_addr + S5P_INFORM6; | |
46 | else if (samsung_rev() == EXYNOS4210_REV_1_0) | |
47 | return sysram_base_addr + 0x20; | |
48 | return pmu_base_addr + S5P_INFORM1; | |
49 | } | |
3681bafe | 50 | |
e30b154b | 51 | #define S5P_CHECK_AFTR 0xFCBA0D10 |
3681bafe | 52 | |
f4ba4b01 JL |
53 | /* For Cortex-A9 Diagnostic and Power control register */ |
54 | static unsigned int save_arm_register[2]; | |
55 | ||
0d713cf1 | 56 | void exynos_cpu_save_register(void) |
309e08c4 DL |
57 | { |
58 | unsigned long tmp; | |
59 | ||
60 | /* Save Power control register */ | |
61 | asm ("mrc p15, 0, %0, c15, c0, 0" | |
62 | : "=r" (tmp) : : "cc"); | |
63 | ||
64 | save_arm_register[0] = tmp; | |
65 | ||
66 | /* Save Diagnostic register */ | |
67 | asm ("mrc p15, 0, %0, c15, c0, 1" | |
68 | : "=r" (tmp) : : "cc"); | |
69 | ||
70 | save_arm_register[1] = tmp; | |
71 | } | |
72 | ||
0d713cf1 | 73 | void exynos_cpu_restore_register(void) |
309e08c4 DL |
74 | { |
75 | unsigned long tmp; | |
76 | ||
77 | /* Restore Power control register */ | |
78 | tmp = save_arm_register[0]; | |
79 | ||
80 | asm volatile ("mcr p15, 0, %0, c15, c0, 0" | |
81 | : : "r" (tmp) | |
82 | : "cc"); | |
83 | ||
84 | /* Restore Diagnostic register */ | |
85 | tmp = save_arm_register[1]; | |
86 | ||
87 | asm volatile ("mcr p15, 0, %0, c15, c0, 1" | |
88 | : : "r" (tmp) | |
89 | : "cc"); | |
90 | } | |
91 | ||
0d713cf1 | 92 | void exynos_pm_central_suspend(void) |
01601b34 TF |
93 | { |
94 | unsigned long tmp; | |
95 | ||
96 | /* Setting Central Sequence Register for power down mode */ | |
97 | tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
98 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
99 | pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
100 | } | |
101 | ||
0d713cf1 | 102 | int exynos_pm_central_resume(void) |
01601b34 TF |
103 | { |
104 | unsigned long tmp; | |
105 | ||
106 | /* | |
107 | * If PMU failed while entering sleep mode, WFI will be | |
108 | * ignored by PMU and then exiting cpu_do_idle(). | |
109 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
110 | * in this situation. | |
111 | */ | |
112 | tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
113 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
114 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
115 | pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
116 | /* clear the wakeup state register */ | |
117 | pmu_raw_writel(0x0, S5P_WAKEUP_STAT); | |
118 | /* No need to perform below restore code */ | |
119 | return -1; | |
120 | } | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ | |
126 | static void exynos_set_wakeupmask(long mask) | |
127 | { | |
128 | pmu_raw_writel(mask, S5P_WAKEUP_MASK); | |
89366409 BZ |
129 | if (soc_is_exynos3250()) |
130 | pmu_raw_writel(0x0, S5P_WAKEUP_MASK2); | |
01601b34 TF |
131 | } |
132 | ||
133 | static void exynos_cpu_set_boot_vector(long flags) | |
134 | { | |
134abc29 BZ |
135 | __raw_writel(virt_to_phys(exynos_cpu_resume), |
136 | exynos_boot_vector_addr()); | |
137 | __raw_writel(flags, exynos_boot_vector_flag()); | |
01601b34 TF |
138 | } |
139 | ||
140 | static int exynos_aftr_finisher(unsigned long flags) | |
141 | { | |
a135e201 BZ |
142 | int ret; |
143 | ||
89366409 | 144 | exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e); |
01601b34 TF |
145 | /* Set value of power down register for aftr mode */ |
146 | exynos_sys_powerdown_conf(SYS_AFTR); | |
a135e201 BZ |
147 | |
148 | ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR); | |
149 | if (ret == -ENOSYS) { | |
150 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) | |
151 | exynos_cpu_save_register(); | |
152 | exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); | |
153 | cpu_do_idle(); | |
154 | } | |
01601b34 TF |
155 | |
156 | return 1; | |
157 | } | |
158 | ||
159 | void exynos_enter_aftr(void) | |
160 | { | |
89366409 BZ |
161 | unsigned int cpuid = smp_processor_id(); |
162 | ||
01601b34 TF |
163 | cpu_pm_enter(); |
164 | ||
89366409 BZ |
165 | if (soc_is_exynos3250()) |
166 | exynos_set_boot_flag(cpuid, C2_STATE); | |
167 | ||
01601b34 | 168 | exynos_pm_central_suspend(); |
01601b34 | 169 | |
865e8b76 BZ |
170 | if (of_machine_is_compatible("samsung,exynos4212") || |
171 | of_machine_is_compatible("samsung,exynos4412")) { | |
172 | /* Setting SEQ_OPTION register */ | |
173 | pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, | |
174 | S5P_CENTRAL_SEQ_OPTION); | |
175 | } | |
176 | ||
01601b34 TF |
177 | cpu_suspend(0, exynos_aftr_finisher); |
178 | ||
179 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { | |
180 | scu_enable(S5P_VA_SCU); | |
a135e201 BZ |
181 | if (call_firmware_op(resume) == -ENOSYS) |
182 | exynos_cpu_restore_register(); | |
01601b34 TF |
183 | } |
184 | ||
185 | exynos_pm_central_resume(); | |
186 | ||
89366409 BZ |
187 | if (soc_is_exynos3250()) |
188 | exynos_clear_boot_flag(cpuid, C2_STATE); | |
189 | ||
01601b34 TF |
190 | cpu_pm_exit(); |
191 | } | |
712eddf7 | 192 | |
cfdda353 | 193 | #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE) |
712eddf7 BZ |
194 | static atomic_t cpu1_wakeup = ATOMIC_INIT(0); |
195 | ||
196 | static int exynos_cpu0_enter_aftr(void) | |
197 | { | |
198 | int ret = -1; | |
199 | ||
200 | /* | |
201 | * If the other cpu is powered on, we have to power it off, because | |
202 | * the AFTR state won't work otherwise | |
203 | */ | |
204 | if (cpu_online(1)) { | |
205 | /* | |
206 | * We reach a sync point with the coupled idle state, we know | |
207 | * the other cpu will power down itself or will abort the | |
208 | * sequence, let's wait for one of these to happen | |
209 | */ | |
210 | while (exynos_cpu_power_state(1)) { | |
af997114 BZ |
211 | unsigned long boot_addr; |
212 | ||
712eddf7 BZ |
213 | /* |
214 | * The other cpu may skip idle and boot back | |
215 | * up again | |
216 | */ | |
217 | if (atomic_read(&cpu1_wakeup)) | |
218 | goto abort; | |
219 | ||
220 | /* | |
221 | * The other cpu may bounce through idle and | |
222 | * boot back up again, getting stuck in the | |
223 | * boot rom code | |
224 | */ | |
af997114 BZ |
225 | ret = exynos_get_boot_addr(1, &boot_addr); |
226 | if (ret) | |
227 | goto fail; | |
228 | ret = -1; | |
229 | if (boot_addr == 0) | |
712eddf7 BZ |
230 | goto abort; |
231 | ||
232 | cpu_relax(); | |
233 | } | |
234 | } | |
235 | ||
236 | exynos_enter_aftr(); | |
237 | ret = 0; | |
238 | ||
239 | abort: | |
240 | if (cpu_online(1)) { | |
af997114 BZ |
241 | unsigned long boot_addr = virt_to_phys(exynos_cpu_resume); |
242 | ||
712eddf7 BZ |
243 | /* |
244 | * Set the boot vector to something non-zero | |
245 | */ | |
af997114 BZ |
246 | ret = exynos_set_boot_addr(1, boot_addr); |
247 | if (ret) | |
248 | goto fail; | |
712eddf7 BZ |
249 | dsb(); |
250 | ||
251 | /* | |
252 | * Turn on cpu1 and wait for it to be on | |
253 | */ | |
254 | exynos_cpu_power_up(1); | |
255 | while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN) | |
256 | cpu_relax(); | |
257 | ||
af997114 BZ |
258 | if (soc_is_exynos3250()) { |
259 | while (!pmu_raw_readl(S5P_PMU_SPARE2) && | |
260 | !atomic_read(&cpu1_wakeup)) | |
261 | cpu_relax(); | |
262 | ||
263 | if (!atomic_read(&cpu1_wakeup)) | |
264 | exynos_core_restart(1); | |
265 | } | |
266 | ||
712eddf7 | 267 | while (!atomic_read(&cpu1_wakeup)) { |
af997114 BZ |
268 | smp_rmb(); |
269 | ||
712eddf7 BZ |
270 | /* |
271 | * Poke cpu1 out of the boot rom | |
272 | */ | |
712eddf7 | 273 | |
af997114 BZ |
274 | ret = exynos_set_boot_addr(1, boot_addr); |
275 | if (ret) | |
276 | goto fail; | |
277 | ||
278 | call_firmware_op(cpu_boot, 1); | |
279 | ||
280 | if (soc_is_exynos3250()) | |
281 | dsb_sev(); | |
282 | else | |
283 | arch_send_wakeup_ipi_mask(cpumask_of(1)); | |
712eddf7 BZ |
284 | } |
285 | } | |
af997114 | 286 | fail: |
712eddf7 BZ |
287 | return ret; |
288 | } | |
289 | ||
290 | static int exynos_wfi_finisher(unsigned long flags) | |
291 | { | |
af997114 BZ |
292 | if (soc_is_exynos3250()) |
293 | flush_cache_all(); | |
712eddf7 BZ |
294 | cpu_do_idle(); |
295 | ||
296 | return -1; | |
297 | } | |
298 | ||
299 | static int exynos_cpu1_powerdown(void) | |
300 | { | |
301 | int ret = -1; | |
302 | ||
303 | /* | |
304 | * Idle sequence for cpu1 | |
305 | */ | |
306 | if (cpu_pm_enter()) | |
307 | goto cpu1_aborted; | |
308 | ||
309 | /* | |
310 | * Turn off cpu 1 | |
311 | */ | |
312 | exynos_cpu_power_down(1); | |
313 | ||
af997114 BZ |
314 | if (soc_is_exynos3250()) |
315 | pmu_raw_writel(0, S5P_PMU_SPARE2); | |
316 | ||
712eddf7 BZ |
317 | ret = cpu_suspend(0, exynos_wfi_finisher); |
318 | ||
319 | cpu_pm_exit(); | |
320 | ||
321 | cpu1_aborted: | |
322 | dsb(); | |
323 | /* | |
324 | * Notify cpu 0 that cpu 1 is awake | |
325 | */ | |
326 | atomic_set(&cpu1_wakeup, 1); | |
327 | ||
328 | return ret; | |
329 | } | |
330 | ||
331 | static void exynos_pre_enter_aftr(void) | |
332 | { | |
af997114 BZ |
333 | unsigned long boot_addr = virt_to_phys(exynos_cpu_resume); |
334 | ||
335 | (void)exynos_set_boot_addr(1, boot_addr); | |
712eddf7 BZ |
336 | } |
337 | ||
338 | static void exynos_post_enter_aftr(void) | |
339 | { | |
340 | atomic_set(&cpu1_wakeup, 0); | |
341 | } | |
342 | ||
343 | struct cpuidle_exynos_data cpuidle_coupled_exynos_data = { | |
344 | .cpu0_enter_aftr = exynos_cpu0_enter_aftr, | |
345 | .cpu1_powerdown = exynos_cpu1_powerdown, | |
346 | .pre_enter_aftr = exynos_pre_enter_aftr, | |
347 | .post_enter_aftr = exynos_post_enter_aftr, | |
348 | }; | |
cfdda353 | 349 | #endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */ |