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c9347101 JL |
1 | /* |
2 | * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd. | |
1663895c JL |
3 | * http://www.samsung.com |
4 | * | |
c9347101 | 5 | * EXYNOS - Power Management support |
1663895c JL |
6 | * |
7 | * Based on arch/arm/mach-s3c2410/pm.c | |
8 | * Copyright (c) 2006 Simtec Electronics | |
9 | * Ben Dooks <ben@simtec.co.uk> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/suspend.h> | |
bb072c3c | 18 | #include <linux/syscore_ops.h> |
1663895c | 19 | #include <linux/io.h> |
56c03d91 JL |
20 | #include <linux/err.h> |
21 | #include <linux/clk.h> | |
1663895c JL |
22 | |
23 | #include <asm/cacheflush.h> | |
24 | #include <asm/hardware/cache-l2x0.h> | |
63b870f1 | 25 | #include <asm/smp_scu.h> |
1663895c JL |
26 | |
27 | #include <plat/cpu.h> | |
28 | #include <plat/pm.h> | |
56c03d91 | 29 | #include <plat/pll.h> |
b93cb91b | 30 | #include <plat/regs-srom.h> |
1663895c JL |
31 | |
32 | #include <mach/regs-irq.h> | |
1663895c JL |
33 | #include <mach/regs-clock.h> |
34 | #include <mach/regs-pmu.h> | |
35 | #include <mach/pm-core.h> | |
ccd458c1 KK |
36 | |
37 | #include "common.h" | |
1663895c JL |
38 | |
39 | static struct sleep_save exynos4_set_clksrc[] = { | |
a855039e KK |
40 | { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, |
41 | { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, | |
42 | { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, | |
43 | { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, }, | |
44 | { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, }, | |
45 | { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, }, | |
46 | { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, }, | |
47 | { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, }, | |
48 | { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, | |
1663895c JL |
49 | }; |
50 | ||
acd35616 | 51 | static struct sleep_save exynos4210_set_clksrc[] = { |
a855039e | 52 | { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, |
acd35616 JC |
53 | }; |
54 | ||
56c03d91 | 55 | static struct sleep_save exynos4_epll_save[] = { |
a855039e KK |
56 | SAVE_ITEM(EXYNOS4_EPLL_CON0), |
57 | SAVE_ITEM(EXYNOS4_EPLL_CON1), | |
56c03d91 JL |
58 | }; |
59 | ||
60 | static struct sleep_save exynos4_vpll_save[] = { | |
a855039e KK |
61 | SAVE_ITEM(EXYNOS4_VPLL_CON0), |
62 | SAVE_ITEM(EXYNOS4_VPLL_CON1), | |
56c03d91 JL |
63 | }; |
64 | ||
86ffb0e8 AK |
65 | static struct sleep_save exynos5_sys_save[] = { |
66 | SAVE_ITEM(EXYNOS5_SYS_I2C_CFG), | |
67 | }; | |
68 | ||
c9347101 | 69 | static struct sleep_save exynos_core_save[] = { |
b93cb91b MH |
70 | /* SROM side */ |
71 | SAVE_ITEM(S5P_SROM_BW), | |
72 | SAVE_ITEM(S5P_SROM_BC0), | |
73 | SAVE_ITEM(S5P_SROM_BC1), | |
74 | SAVE_ITEM(S5P_SROM_BC2), | |
75 | SAVE_ITEM(S5P_SROM_BC3), | |
1663895c JL |
76 | }; |
77 | ||
1663895c | 78 | |
f4ba4b01 JL |
79 | /* For Cortex-A9 Diagnostic and Power control register */ |
80 | static unsigned int save_arm_register[2]; | |
81 | ||
c9347101 | 82 | static int exynos_cpu_suspend(unsigned long arg) |
1663895c | 83 | { |
60e49ca6 | 84 | #ifdef CONFIG_CACHE_L2X0 |
1663895c | 85 | outer_flush_all(); |
60e49ca6 | 86 | #endif |
1663895c | 87 | |
573e5bbe AK |
88 | if (soc_is_exynos5250()) |
89 | flush_cache_all(); | |
90 | ||
1663895c JL |
91 | /* issue the standby signal into the pm unit. */ |
92 | cpu_do_idle(); | |
93 | ||
d3fcacf5 AK |
94 | pr_info("Failed to suspend the system\n"); |
95 | return 1; /* Aborting suspend */ | |
1663895c JL |
96 | } |
97 | ||
c9347101 | 98 | static void exynos_pm_prepare(void) |
1663895c | 99 | { |
60e49ca6 | 100 | unsigned int tmp; |
1663895c | 101 | |
c9347101 | 102 | s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save)); |
1663895c | 103 | |
60e49ca6 JL |
104 | if (!soc_is_exynos5250()) { |
105 | s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); | |
106 | s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); | |
107 | } else { | |
86ffb0e8 | 108 | s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save)); |
60e49ca6 JL |
109 | /* Disable USE_RETENTION of JPEG_MEM_OPTION */ |
110 | tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION); | |
111 | tmp &= ~EXYNOS5_OPTION_USE_RETENTION; | |
112 | __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION); | |
113 | } | |
1663895c JL |
114 | |
115 | /* Set value of power down register for sleep mode */ | |
116 | ||
7d44d2ba | 117 | exynos_sys_powerdown_conf(SYS_SLEEP); |
1663895c JL |
118 | __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1); |
119 | ||
120 | /* ensure at least INFORM0 has the resume address */ | |
121 | ||
122 | __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0); | |
123 | ||
124 | /* Before enter central sequence mode, clock src register have to set */ | |
125 | ||
60e49ca6 JL |
126 | if (!soc_is_exynos5250()) |
127 | s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc)); | |
1663895c | 128 | |
acd35616 JC |
129 | if (soc_is_exynos4210()) |
130 | s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc)); | |
131 | ||
1663895c JL |
132 | } |
133 | ||
c9347101 | 134 | static int exynos_pm_add(struct device *dev, struct subsys_interface *sif) |
1663895c | 135 | { |
c9347101 JL |
136 | pm_cpu_prep = exynos_pm_prepare; |
137 | pm_cpu_sleep = exynos_cpu_suspend; | |
1663895c JL |
138 | |
139 | return 0; | |
140 | } | |
141 | ||
56c03d91 JL |
142 | static unsigned long pll_base_rate; |
143 | ||
144 | static void exynos4_restore_pll(void) | |
145 | { | |
146 | unsigned long pll_con, locktime, lockcnt; | |
147 | unsigned long pll_in_rate; | |
148 | unsigned int p_div, epll_wait = 0, vpll_wait = 0; | |
149 | ||
150 | if (pll_base_rate == 0) | |
151 | return; | |
152 | ||
153 | pll_in_rate = pll_base_rate; | |
154 | ||
155 | /* EPLL */ | |
156 | pll_con = exynos4_epll_save[0].val; | |
157 | ||
158 | if (pll_con & (1 << 31)) { | |
159 | pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT); | |
160 | p_div = (pll_con >> PLL46XX_PDIV_SHIFT); | |
161 | ||
162 | pll_in_rate /= 1000000; | |
163 | ||
164 | locktime = (3000 / pll_in_rate) * p_div; | |
165 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | |
166 | ||
a855039e | 167 | __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK); |
56c03d91 JL |
168 | |
169 | s3c_pm_do_restore_core(exynos4_epll_save, | |
170 | ARRAY_SIZE(exynos4_epll_save)); | |
171 | epll_wait = 1; | |
172 | } | |
173 | ||
174 | pll_in_rate = pll_base_rate; | |
175 | ||
176 | /* VPLL */ | |
177 | pll_con = exynos4_vpll_save[0].val; | |
178 | ||
179 | if (pll_con & (1 << 31)) { | |
180 | pll_in_rate /= 1000000; | |
181 | /* 750us */ | |
182 | locktime = 750; | |
183 | lockcnt = locktime * 10000 / (10000 / pll_in_rate); | |
184 | ||
a855039e | 185 | __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK); |
56c03d91 JL |
186 | |
187 | s3c_pm_do_restore_core(exynos4_vpll_save, | |
188 | ARRAY_SIZE(exynos4_vpll_save)); | |
189 | vpll_wait = 1; | |
190 | } | |
191 | ||
192 | /* Wait PLL locking */ | |
193 | ||
194 | do { | |
195 | if (epll_wait) { | |
a855039e KK |
196 | pll_con = __raw_readl(EXYNOS4_EPLL_CON0); |
197 | if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT)) | |
56c03d91 JL |
198 | epll_wait = 0; |
199 | } | |
200 | ||
201 | if (vpll_wait) { | |
a855039e KK |
202 | pll_con = __raw_readl(EXYNOS4_VPLL_CON0); |
203 | if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT)) | |
56c03d91 JL |
204 | vpll_wait = 0; |
205 | } | |
206 | } while (epll_wait || vpll_wait); | |
207 | } | |
208 | ||
c9347101 | 209 | static struct subsys_interface exynos_pm_interface = { |
60e49ca6 | 210 | .name = "exynos_pm", |
9ee6af9c | 211 | .subsys = &exynos_subsys, |
c9347101 | 212 | .add_dev = exynos_pm_add, |
bb072c3c RW |
213 | }; |
214 | ||
c9347101 | 215 | static __init int exynos_pm_drvinit(void) |
bb072c3c | 216 | { |
56c03d91 | 217 | struct clk *pll_base; |
bb072c3c RW |
218 | unsigned int tmp; |
219 | ||
e085cad6 KK |
220 | if (soc_is_exynos5440()) |
221 | return 0; | |
222 | ||
bb072c3c RW |
223 | s3c_pm_init(); |
224 | ||
225 | /* All wakeup disable */ | |
226 | ||
227 | tmp = __raw_readl(S5P_WAKEUP_MASK); | |
228 | tmp |= ((0xFF << 8) | (0x1F << 1)); | |
229 | __raw_writel(tmp, S5P_WAKEUP_MASK); | |
230 | ||
c9347101 JL |
231 | if (!soc_is_exynos5250()) { |
232 | pll_base = clk_get(NULL, "xtal"); | |
56c03d91 | 233 | |
c9347101 JL |
234 | if (!IS_ERR(pll_base)) { |
235 | pll_base_rate = clk_get_rate(pll_base); | |
236 | clk_put(pll_base); | |
237 | } | |
56c03d91 JL |
238 | } |
239 | ||
c9347101 | 240 | return subsys_interface_register(&exynos_pm_interface); |
bb072c3c | 241 | } |
c9347101 | 242 | arch_initcall(exynos_pm_drvinit); |
bb072c3c | 243 | |
c9347101 | 244 | static int exynos_pm_suspend(void) |
12974e9f JL |
245 | { |
246 | unsigned long tmp; | |
247 | ||
248 | /* Setting Central Sequence Register for power down mode */ | |
249 | ||
250 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
251 | tmp &= ~S5P_CENTRAL_LOWPWR_CFG; | |
252 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
253 | ||
60e49ca6 | 254 | /* Setting SEQ_OPTION register */ |
00a351f2 | 255 | |
60e49ca6 JL |
256 | tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0); |
257 | __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); | |
f4ba4b01 | 258 | |
60e49ca6 JL |
259 | if (!soc_is_exynos5250()) { |
260 | /* Save Power control register */ | |
261 | asm ("mrc p15, 0, %0, c15, c0, 0" | |
262 | : "=r" (tmp) : : "cc"); | |
263 | save_arm_register[0] = tmp; | |
264 | ||
265 | /* Save Diagnostic register */ | |
266 | asm ("mrc p15, 0, %0, c15, c0, 1" | |
267 | : "=r" (tmp) : : "cc"); | |
268 | save_arm_register[1] = tmp; | |
269 | } | |
f4ba4b01 | 270 | |
12974e9f JL |
271 | return 0; |
272 | } | |
273 | ||
c9347101 | 274 | static void exynos_pm_resume(void) |
1663895c | 275 | { |
e240ab1c JL |
276 | unsigned long tmp; |
277 | ||
278 | /* | |
279 | * If PMU failed while entering sleep mode, WFI will be | |
280 | * ignored by PMU and then exiting cpu_do_idle(). | |
281 | * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically | |
282 | * in this situation. | |
283 | */ | |
284 | tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); | |
285 | if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { | |
286 | tmp |= S5P_CENTRAL_LOWPWR_CFG; | |
287 | __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); | |
d3fcacf5 AK |
288 | /* clear the wakeup state register */ |
289 | __raw_writel(0x0, S5P_WAKEUP_STAT); | |
e240ab1c JL |
290 | /* No need to perform below restore code */ |
291 | goto early_wakeup; | |
292 | } | |
60e49ca6 JL |
293 | if (!soc_is_exynos5250()) { |
294 | /* Restore Power control register */ | |
295 | tmp = save_arm_register[0]; | |
296 | asm volatile ("mcr p15, 0, %0, c15, c0, 0" | |
297 | : : "r" (tmp) | |
298 | : "cc"); | |
299 | ||
300 | /* Restore Diagnostic register */ | |
301 | tmp = save_arm_register[1]; | |
302 | asm volatile ("mcr p15, 0, %0, c15, c0, 1" | |
303 | : : "r" (tmp) | |
304 | : "cc"); | |
305 | } | |
e240ab1c | 306 | |
1663895c JL |
307 | /* For release retention */ |
308 | ||
309 | __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); | |
310 | __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION); | |
311 | __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION); | |
312 | __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION); | |
313 | __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION); | |
314 | __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION); | |
315 | __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION); | |
316 | ||
86ffb0e8 AK |
317 | if (soc_is_exynos5250()) |
318 | s3c_pm_do_restore(exynos5_sys_save, | |
319 | ARRAY_SIZE(exynos5_sys_save)); | |
320 | ||
c9347101 | 321 | s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save)); |
1663895c | 322 | |
60e49ca6 JL |
323 | if (!soc_is_exynos5250()) { |
324 | exynos4_restore_pll(); | |
56c03d91 | 325 | |
556ef3e4 | 326 | #ifdef CONFIG_SMP |
60e49ca6 | 327 | scu_enable(S5P_VA_SCU); |
556ef3e4 | 328 | #endif |
60e49ca6 | 329 | } |
1663895c | 330 | |
e240ab1c | 331 | early_wakeup: |
ebee8541 IS |
332 | |
333 | /* Clear SLEEP mode set in INFORM1 */ | |
334 | __raw_writel(0x0, S5P_INFORM1); | |
335 | ||
e240ab1c | 336 | return; |
1663895c JL |
337 | } |
338 | ||
c9347101 JL |
339 | static struct syscore_ops exynos_pm_syscore_ops = { |
340 | .suspend = exynos_pm_suspend, | |
341 | .resume = exynos_pm_resume, | |
1663895c JL |
342 | }; |
343 | ||
60e49ca6 | 344 | static __init int exynos_pm_syscore_init(void) |
1663895c | 345 | { |
e085cad6 KK |
346 | if (soc_is_exynos5440()) |
347 | return 0; | |
348 | ||
c9347101 | 349 | register_syscore_ops(&exynos_pm_syscore_ops); |
bb072c3c | 350 | return 0; |
1663895c | 351 | } |
60e49ca6 | 352 | arch_initcall(exynos_pm_syscore_init); |