[deliverable/linux.git] / arch / arm / mach-exynos / pm.c

/*
 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - Power Management support
 *
 * Based on arch/arm/mach-s3c2410/pm.c
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>

#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>

#include <mach/map.h>

#include "common.h"
#include "regs-pmu.h"

/**
 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
 * @hwirq: Hardware IRQ signal of the GIC
 * @mask: Mask in PMU wake-up mask register
 */
struct exynos_wkup_irq {
	unsigned int hwirq;
	u32 mask;
};

static struct sleep_save exynos5_sys_save[] = {
	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
};

static struct sleep_save exynos_core_save[] = {
	/* SROM side */
	SAVE_ITEM(S5P_SROM_BW),
	SAVE_ITEM(S5P_SROM_BC0),
	SAVE_ITEM(S5P_SROM_BC1),
	SAVE_ITEM(S5P_SROM_BC2),
	SAVE_ITEM(S5P_SROM_BC3),
};

/*
 * GIC wake-up support
 */

static u32 exynos_irqwake_intmask = 0xffffffff;

static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	{ 76, BIT(1) }, /* RTC alarm */
	{ 77, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	{ 75, BIT(1) }, /* RTC alarm */
	{ 76, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
	const struct exynos_wkup_irq *wkup_irq;

	if (soc_is_exynos5250())
		wkup_irq = exynos5250_wkup_irq;
	else
		wkup_irq = exynos4_wkup_irq;

	while (wkup_irq->mask) {
		if (wkup_irq->hwirq == data->hwirq) {
			if (!state)
				exynos_irqwake_intmask |= wkup_irq->mask;
			else
				exynos_irqwake_intmask &= ~wkup_irq->mask;
			return 0;
		}
		++wkup_irq;
	}

	return -ENOENT;
}

/**
 * exynos_core_power_down : power down the specified cpu
 * @cpu : the cpu to power down
 *
 * Power down the specified cpu. The sequence must be finished by a
 * call to cpu_do_idle()
 *
 */
void exynos_cpu_power_down(int cpu)
{
	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}

/**
 * exynos_cpu_power_up : power up the specified cpu
 * @cpu : the cpu to power up
 *
 * Power up the specified cpu
 */
void exynos_cpu_power_up(int cpu)
{
	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
		     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}

/**
 * exynos_cpu_power_state : returns the power state of the cpu
 * @cpu : the cpu to retrieve the power state from
 *
 */
int exynos_cpu_power_state(int cpu)
{
	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
			S5P_CORE_LOCAL_PWR_EN);
}

/**
 * exynos_cluster_power_down : power down the specified cluster
 * @cluster : the cluster to power down
 */
void exynos_cluster_power_down(int cluster)
{
	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
}

/**
 * exynos_cluster_power_up : power up the specified cluster
 * @cluster : the cluster to power up
 */
void exynos_cluster_power_up(int cluster)
{
	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
		     EXYNOS_COMMON_CONFIGURATION(cluster));
}

/**
 * exynos_cluster_power_state : returns the power state of the cluster
 * @cluster : the cluster to retrieve the power state from
 *
 */
int exynos_cluster_power_state(int cluster)
{
	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
			S5P_CORE_LOCAL_PWR_EN);
}

#define EXYNOS_BOOT_VECTOR_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(sysram_base_addr + 0x24) : S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \
			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
			(sysram_base_addr + 0x20) : S5P_INFORM1))

#define S5P_CHECK_AFTR  0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD

/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
	__raw_writel(mask, S5P_WAKEUP_MASK);
}

static void exynos_cpu_set_boot_vector(long flags)
{
	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
}

void exynos_enter_aftr(void)
{
	exynos_set_wakeupmask(0x0000ff3e);
	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
	/* Set value of power down register for aftr mode */
	exynos_sys_powerdown_conf(SYS_AFTR);
}

/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];

static void exynos_cpu_save_register(void)
{
	unsigned long tmp;

	/* Save Power control register */
	asm ("mrc p15, 0, %0, c15, c0, 0"
	     : "=r" (tmp) : : "cc");

	save_arm_register[0] = tmp;

	/* Save Diagnostic register */
	asm ("mrc p15, 0, %0, c15, c0, 1"
	     : "=r" (tmp) : : "cc");

	save_arm_register[1] = tmp;
}

static void exynos_cpu_restore_register(void)
{
	unsigned long tmp;

	/* Restore Power control register */
	tmp = save_arm_register[0];

	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
		      : : "r" (tmp)
		      : "cc");

	/* Restore Diagnostic register */
	tmp = save_arm_register[1];

	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
		      : : "r" (tmp)
		      : "cc");
}

static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
	outer_flush_all();
#endif

	if (soc_is_exynos5250())
		flush_cache_all();

	/* issue the standby signal into the pm unit. */
	cpu_do_idle();

	pr_info("Failed to suspend the system\n");
	return 1; /* Aborting suspend */
}

static void exynos_pm_prepare(void)
{
	unsigned int tmp;

	/* Set wake-up mask registers */
	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);

	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (soc_is_exynos5250()) {
		s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	}

	/* Set value of power down register for sleep mode */

	exynos_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}

static void exynos_pm_central_suspend(void)
{
	unsigned long tmp;

	/* Setting Central Sequence Register for power down mode */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}

static int exynos_pm_suspend(void)
{
	unsigned long tmp;

	exynos_pm_central_suspend();

	/* Setting SEQ_OPTION register */

	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
		exynos_cpu_save_register();

	return 0;
}

static int exynos_pm_central_resume(void)
{
	unsigned long tmp;

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* clear the wakeup state register */
		__raw_writel(0x0, S5P_WAKEUP_STAT);
		/* No need to perform below restore code */
		return -1;
	}

	return 0;
}

static void exynos_pm_resume(void)
{
	if (exynos_pm_central_resume())
		goto early_wakeup;

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
		exynos_cpu_restore_register();

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	if (soc_is_exynos5250())
		s3c_pm_do_restore(exynos5_sys_save,
			ARRAY_SIZE(exynos5_sys_save));

	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
		scu_enable(S5P_VA_SCU);

early_wakeup:

	/* Clear SLEEP mode set in INFORM1 */
	__raw_writel(0x0, S5P_INFORM1);

	return;
}

static struct syscore_ops exynos_pm_syscore_ops = {
	.suspend	= exynos_pm_suspend,
	.resume		= exynos_pm_resume,
};

/*
 * Suspend Ops
 */

static int exynos_suspend_enter(suspend_state_t state)
{
	int ret;

	s3c_pm_debug_init();

	S3C_PMDBG("%s: suspending the system...\n", __func__);

	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
			exynos_irqwake_intmask, exynos_get_eint_wake_mask());

	if (exynos_irqwake_intmask == -1U
	    && exynos_get_eint_wake_mask() == -1U) {
		pr_err("%s: No wake-up sources!\n", __func__);
		pr_err("%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	s3c_pm_save_uarts();
	exynos_pm_prepare();
	flush_cache_all();
	s3c_pm_check_store();

	ret = cpu_suspend(0, exynos_cpu_suspend);
	if (ret)
		return ret;

	s3c_pm_restore_uarts();

	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
			__raw_readl(S5P_WAKEUP_STAT));

	s3c_pm_check_restore();

	S3C_PMDBG("%s: resuming the system...\n", __func__);

	return 0;
}

static int exynos_suspend_prepare(void)
{
	s3c_pm_check_prepare();

	return 0;
}

static void exynos_suspend_finish(void)
{
	s3c_pm_check_cleanup();
}

static const struct platform_suspend_ops exynos_suspend_ops = {
	.enter		= exynos_suspend_enter,
	.prepare	= exynos_suspend_prepare,
	.finish		= exynos_suspend_finish,
	.valid		= suspend_valid_only_mem,
};

static int exynos_cpu_pm_notifier(struct notifier_block *self,
				  unsigned long cmd, void *v)
{
	int cpu = smp_processor_id();

	switch (cmd) {
	case CPU_PM_ENTER:
		if (cpu == 0) {
			exynos_pm_central_suspend();
			if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
				exynos_cpu_save_register();
		}
		break;

	case CPU_PM_EXIT:
		if (cpu == 0) {
			if (read_cpuid_part_number() ==
					ARM_CPU_PART_CORTEX_A9) {
				scu_enable(S5P_VA_SCU);
				exynos_cpu_restore_register();
			}
			exynos_pm_central_resume();
		}
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos_cpu_pm_notifier_block = {
	.notifier_call = exynos_cpu_pm_notifier,
};

void __init exynos_pm_init(void)
{
	u32 tmp;

	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);

	/* Platform-specific GIC callback */
	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;

	/* All wakeup disable */
	tmp = __raw_readl(S5P_WAKEUP_MASK);
	tmp |= ((0xFF << 8) | (0x1F << 1));
	__raw_writel(tmp, S5P_WAKEUP_MASK);

	register_syscore_ops(&exynos_pm_syscore_ops);
	suspend_set_ops(&exynos_suspend_ops);
}
Commit	Line	Data
c9347101 JL	1	/*
c9347101 JL	2	* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
1663895c JL	3	* http://www.samsung.com
1663895c JL	4	*
c9347101	5	* EXYNOS - Power Management support
1663895c JL	6	*
	7	* Based on arch/arm/mach-s3c2410/pm.c
	8	* Copyright (c) 2006 Simtec Electronics
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/suspend.h>
bb072c3c	18	#include <linux/syscore_ops.h>
85f9f908	19	#include <linux/cpu_pm.h>
1663895c	20	#include <linux/io.h>
dd8ac696	21	#include <linux/irqchip/arm-gic.h>
56c03d91 JL	22	#include <linux/err.h>
56c03d91 JL	23	#include <linux/clk.h>
1663895c JL	24
	25	#include <asm/cacheflush.h>
	26	#include <asm/hardware/cache-l2x0.h>
63b870f1	27	#include <asm/smp_scu.h>
d710aa31	28	#include <asm/suspend.h>
1663895c	29
d710aa31	30	#include <plat/pm-common.h>
56c03d91	31	#include <plat/pll.h>
b93cb91b	32	#include <plat/regs-srom.h>
1663895c	33
9c9239af	34	#include <mach/map.h>
ccd458c1 KK	35
ccd458c1 KK	36	#include "common.h"
65c9a853	37	#include "regs-pmu.h"
1663895c	38
dd8ac696 TF	39	/**
	40	* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
	41	* @hwirq: Hardware IRQ signal of the GIC
	42	* @mask: Mask in PMU wake-up mask register
	43	*/
	44	struct exynos_wkup_irq {
	45	unsigned int hwirq;
	46	u32 mask;
	47	};
	48
86ffb0e8 AK	49	static struct sleep_save exynos5_sys_save[] = {
	50	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
	51	};
	52
c9347101	53	static struct sleep_save exynos_core_save[] = {
b93cb91b MH	54	/* SROM side */
	55	SAVE_ITEM(S5P_SROM_BW),
	56	SAVE_ITEM(S5P_SROM_BC0),
	57	SAVE_ITEM(S5P_SROM_BC1),
	58	SAVE_ITEM(S5P_SROM_BC2),
	59	SAVE_ITEM(S5P_SROM_BC3),
1663895c JL	60	};
1663895c JL	61
dd8ac696 TF	62	/*
	63	* GIC wake-up support
	64	*/
	65
d710aa31	66	static u32 exynos_irqwake_intmask = 0xffffffff;
1663895c	67
dd8ac696 TF	68	static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	69	{ 76, BIT(1) }, /* RTC alarm */
	70	{ 77, BIT(2) }, /* RTC tick */
	71	{ /* sentinel */ },
	72	};
	73
	74	static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	75	{ 75, BIT(1) }, /* RTC alarm */
	76	{ 76, BIT(2) }, /* RTC tick */
	77	{ /* sentinel */ },
	78	};
	79
	80	static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
	81	{
	82	const struct exynos_wkup_irq *wkup_irq;
	83
	84	if (soc_is_exynos5250())
	85	wkup_irq = exynos5250_wkup_irq;
	86	else
	87	wkup_irq = exynos4_wkup_irq;
	88
	89	while (wkup_irq->mask) {
	90	if (wkup_irq->hwirq == data->hwirq) {
	91	if (!state)
	92	exynos_irqwake_intmask \|= wkup_irq->mask;
	93	else
	94	exynos_irqwake_intmask &= ~wkup_irq->mask;
	95	return 0;
	96	}
	97	++wkup_irq;
	98	}
	99
	100	return -ENOENT;
	101	}
	102
d3af6976 LKA	103	/**
	104	* exynos_core_power_down : power down the specified cpu
	105	* @cpu : the cpu to power down
	106	*
	107	* Power down the specified cpu. The sequence must be finished by a
	108	* call to cpu_do_idle()
	109	*
	110	*/
	111	void exynos_cpu_power_down(int cpu)
	112	{
	113	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
	114	}
	115
	116	/**
	117	* exynos_cpu_power_up : power up the specified cpu
	118	* @cpu : the cpu to power up
	119	*
	120	* Power up the specified cpu
	121	*/
	122	void exynos_cpu_power_up(int cpu)
	123	{
	124	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
	125	EXYNOS_ARM_CORE_CONFIGURATION(cpu));
	126	}
	127
	128	/**
	129	* exynos_cpu_power_state : returns the power state of the cpu
	130	* @cpu : the cpu to retrieve the power state from
	131	*
	132	*/
	133	int exynos_cpu_power_state(int cpu)
	134	{
	135	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
	136	S5P_CORE_LOCAL_PWR_EN);
	137	}
	138
096d21c6 AK	139	/**
	140	* exynos_cluster_power_down : power down the specified cluster
	141	* @cluster : the cluster to power down
	142	*/
	143	void exynos_cluster_power_down(int cluster)
	144	{
	145	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
	146	}
	147
	148	/**
	149	* exynos_cluster_power_up : power up the specified cluster
	150	* @cluster : the cluster to power up
	151	*/
	152	void exynos_cluster_power_up(int cluster)
	153	{
	154	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
	155	EXYNOS_COMMON_CONFIGURATION(cluster));
	156	}
	157
	158	/**
	159	* exynos_cluster_power_state : returns the power state of the cluster
	160	* @cluster : the cluster to retrieve the power state from
	161	*
	162	*/
	163	int exynos_cluster_power_state(int cluster)
	164	{
	165	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
	166	S5P_CORE_LOCAL_PWR_EN);
	167	}
	168
3681bafe DL	169	#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
3681bafe DL	170	S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
cd245f59	171	(sysram_base_addr + 0x24) : S5P_INFORM0))
3681bafe DL	172	#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
3681bafe DL	173	S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
cd245f59	174	(sysram_base_addr + 0x20) : S5P_INFORM1))
3681bafe	175
e30b154b DL	176	#define S5P_CHECK_AFTR 0xFCBA0D10
e30b154b DL	177	#define S5P_CHECK_SLEEP 0x00000BAD
3681bafe DL	178
	179	/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
	180	static void exynos_set_wakeupmask(long mask)
	181	{
	182	__raw_writel(mask, S5P_WAKEUP_MASK);
	183	}
	184
	185	static void exynos_cpu_set_boot_vector(long flags)
	186	{
	187	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
	188	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
	189	}
	190
	191	void exynos_enter_aftr(void)
	192	{
	193	exynos_set_wakeupmask(0x0000ff3e);
	194	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
	195	/* Set value of power down register for aftr mode */
	196	exynos_sys_powerdown_conf(SYS_AFTR);
	197	}
	198
f4ba4b01 JL	199	/* For Cortex-A9 Diagnostic and Power control register */
	200	static unsigned int save_arm_register[2];
	201
309e08c4 DL	202	static void exynos_cpu_save_register(void)
	203	{
	204	unsigned long tmp;
	205
	206	/* Save Power control register */
	207	asm ("mrc p15, 0, %0, c15, c0, 0"
	208	: "=r" (tmp) : : "cc");
	209
	210	save_arm_register[0] = tmp;
	211
	212	/* Save Diagnostic register */
	213	asm ("mrc p15, 0, %0, c15, c0, 1"
	214	: "=r" (tmp) : : "cc");
	215
	216	save_arm_register[1] = tmp;
	217	}
	218
	219	static void exynos_cpu_restore_register(void)
	220	{
	221	unsigned long tmp;
	222
	223	/* Restore Power control register */
	224	tmp = save_arm_register[0];
	225
	226	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
	227	: : "r" (tmp)
	228	: "cc");
	229
	230	/* Restore Diagnostic register */
	231	tmp = save_arm_register[1];
	232
	233	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
	234	: : "r" (tmp)
	235	: "cc");
	236	}
	237
c9347101	238	static int exynos_cpu_suspend(unsigned long arg)
1663895c	239	{
60e49ca6	240	#ifdef CONFIG_CACHE_L2X0
1663895c	241	outer_flush_all();
60e49ca6	242	#endif
1663895c	243
573e5bbe AK	244	if (soc_is_exynos5250())
	245	flush_cache_all();
	246
1663895c JL	247	/* issue the standby signal into the pm unit. */
	248	cpu_do_idle();
	249
d3fcacf5 AK	250	pr_info("Failed to suspend the system\n");
d3fcacf5 AK	251	return 1; /* Aborting suspend */
1663895c JL	252	}
1663895c JL	253
c9347101	254	static void exynos_pm_prepare(void)
1663895c	255	{
60e49ca6	256	unsigned int tmp;
1663895c	257
d710aa31 TF	258	/* Set wake-up mask registers */
	259	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
	260	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
	261
c9347101	262	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	263
e11d919e	264	if (soc_is_exynos5250()) {
86ffb0e8	265	s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
60e49ca6 JL	266	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
	267	tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
	268	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
	269	__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	270	}
1663895c JL	271
	272	/* Set value of power down register for sleep mode */
	273
7d44d2ba	274	exynos_sys_powerdown_conf(SYS_SLEEP);
1663895c JL	275	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
	276
	277	/* ensure at least INFORM0 has the resume address */
	278
d710aa31	279	__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
1663895c JL	280	}
1663895c JL	281
0ebc13e2	282	static void exynos_pm_central_suspend(void)
12974e9f JL	283	{
	284	unsigned long tmp;
	285
	286	/* Setting Central Sequence Register for power down mode */
12974e9f JL	287	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	288	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	289	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
0ebc13e2 DL	290	}
	291
	292	static int exynos_pm_suspend(void)
	293	{
	294	unsigned long tmp;
	295
	296	exynos_pm_central_suspend();
12974e9f	297
60e49ca6	298	/* Setting SEQ_OPTION register */
00a351f2	299
60e49ca6 JL	300	tmp = (S5P_USE_STANDBY_WFI0 \| S5P_USE_STANDBY_WFE0);
60e49ca6 JL	301	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
f4ba4b01	302
c0c3c359	303	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
309e08c4	304	exynos_cpu_save_register();
f4ba4b01	305
12974e9f JL	306	return 0;
	307	}
	308
0ebc13e2	309	static int exynos_pm_central_resume(void)
1663895c	310	{
e240ab1c JL	311	unsigned long tmp;
	312
	313	/*
	314	* If PMU failed while entering sleep mode, WFI will be
	315	* ignored by PMU and then exiting cpu_do_idle().
	316	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	317	* in this situation.
	318	*/
	319	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	320	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	321	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	322	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
d3fcacf5 AK	323	/* clear the wakeup state register */
d3fcacf5 AK	324	__raw_writel(0x0, S5P_WAKEUP_STAT);
e240ab1c	325	/* No need to perform below restore code */
0ebc13e2	326	return -1;
e240ab1c	327	}
309e08c4	328
0ebc13e2 DL	329	return 0;
	330	}
	331
	332	static void exynos_pm_resume(void)
	333	{
	334	if (exynos_pm_central_resume())
	335	goto early_wakeup;
	336
c0c3c359	337	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
309e08c4	338	exynos_cpu_restore_register();
e240ab1c	339
1663895c JL	340	/* For release retention */
	341
	342	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	343	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	344	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	345	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	346	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	347	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	348	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
	349
86ffb0e8 AK	350	if (soc_is_exynos5250())
	351	s3c_pm_do_restore(exynos5_sys_save,
	352	ARRAY_SIZE(exynos5_sys_save));
	353
c9347101	354	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	355
c0c3c359	356	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
60e49ca6	357	scu_enable(S5P_VA_SCU);
1663895c	358
e240ab1c	359	early_wakeup:
ebee8541 IS	360
	361	/* Clear SLEEP mode set in INFORM1 */
	362	__raw_writel(0x0, S5P_INFORM1);
	363
e240ab1c	364	return;
1663895c JL	365	}
1663895c JL	366
c9347101 JL	367	static struct syscore_ops exynos_pm_syscore_ops = {
	368	.suspend = exynos_pm_suspend,
	369	.resume = exynos_pm_resume,
1663895c JL	370	};
1663895c JL	371
d710aa31 TF	372	/*
	373	* Suspend Ops
	374	*/
	375
	376	static int exynos_suspend_enter(suspend_state_t state)
1663895c	377	{
d710aa31 TF	378	int ret;
	379
	380	s3c_pm_debug_init();
	381
	382	S3C_PMDBG("%s: suspending the system...\n", __func__);
	383
	384	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
	385	exynos_irqwake_intmask, exynos_get_eint_wake_mask());
559ba237	386
d710aa31 TF	387	if (exynos_irqwake_intmask == -1U
	388	&& exynos_get_eint_wake_mask() == -1U) {
	389	pr_err("%s: No wake-up sources!\n", __func__);
	390	pr_err("%s: Aborting sleep\n", __func__);
	391	return -EINVAL;
	392	}
	393
	394	s3c_pm_save_uarts();
	395	exynos_pm_prepare();
	396	flush_cache_all();
	397	s3c_pm_check_store();
	398
	399	ret = cpu_suspend(0, exynos_cpu_suspend);
	400	if (ret)
	401	return ret;
	402
	403	s3c_pm_restore_uarts();
559ba237	404
d710aa31 TF	405	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
	406	__raw_readl(S5P_WAKEUP_STAT));
	407
	408	s3c_pm_check_restore();
	409
	410	S3C_PMDBG("%s: resuming the system...\n", __func__);
	411
	412	return 0;
	413	}
	414
	415	static int exynos_suspend_prepare(void)
	416	{
	417	s3c_pm_check_prepare();
	418
	419	return 0;
	420	}
	421
	422	static void exynos_suspend_finish(void)
	423	{
	424	s3c_pm_check_cleanup();
	425	}
	426
	427	static const struct platform_suspend_ops exynos_suspend_ops = {
	428	.enter = exynos_suspend_enter,
	429	.prepare = exynos_suspend_prepare,
	430	.finish = exynos_suspend_finish,
	431	.valid = suspend_valid_only_mem,
	432	};
	433
85f9f908 DL	434	static int exynos_cpu_pm_notifier(struct notifier_block *self,
	435	unsigned long cmd, void *v)
	436	{
	437	int cpu = smp_processor_id();
	438
	439	switch (cmd) {
	440	case CPU_PM_ENTER:
0ebc13e2 DL	441	if (cpu == 0) {
0ebc13e2 DL	442	exynos_pm_central_suspend();
c0c3c359 AK	443	if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
c0c3c359 AK	444	exynos_cpu_save_register();
0ebc13e2	445	}
85f9f908 DL	446	break;
	447
	448	case CPU_PM_EXIT:
795537da	449	if (cpu == 0) {
c0c3c359 AK	450	if (read_cpuid_part_number() ==
c0c3c359 AK	451	ARM_CPU_PART_CORTEX_A9) {
795537da	452	scu_enable(S5P_VA_SCU);
c0c3c359 AK	453	exynos_cpu_restore_register();
c0c3c359 AK	454	}
0ebc13e2	455	exynos_pm_central_resume();
795537da	456	}
85f9f908 DL	457	break;
	458	}
	459
	460	return NOTIFY_OK;
	461	}
	462
	463	static struct notifier_block exynos_cpu_pm_notifier_block = {
	464	.notifier_call = exynos_cpu_pm_notifier,
	465	};
	466
d710aa31 TF	467	void __init exynos_pm_init(void)
	468	{
	469	u32 tmp;
559ba237	470
85f9f908 DL	471	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
85f9f908 DL	472
dd8ac696 TF	473	/* Platform-specific GIC callback */
	474	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
	475
559ba237 TF	476	/* All wakeup disable */
	477	tmp = __raw_readl(S5P_WAKEUP_MASK);
	478	tmp \|= ((0xFF << 8) \| (0x1F << 1));
	479	__raw_writel(tmp, S5P_WAKEUP_MASK);
e085cad6	480
c9347101	481	register_syscore_ops(&exynos_pm_syscore_ops);
d710aa31	482	suspend_set_ops(&exynos_suspend_ops);
1663895c	483	}