[deliverable/linux.git] / arch / arm / mach-exynos / pm.c

/*
 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - Power Management support
 *
 * Based on arch/arm/mach-s3c2410/pm.c
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_scu.h>

#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>

#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
#include <mach/pmu.h>

static struct sleep_save exynos4_set_clksrc[] = {
	{ .reg = EXYNOS4_CLKSRC_MASK_TOP		, .val = 0x00000001, },
	{ .reg = EXYNOS4_CLKSRC_MASK_CAM		, .val = 0x11111111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_TV			, .val = 0x00000111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_LCD0		, .val = 0x00001111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO		, .val = 0x00000001, },
	{ .reg = EXYNOS4_CLKSRC_MASK_FSYS		, .val = 0x01011111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0		, .val = 0x01111111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1		, .val = 0x01110111, },
	{ .reg = EXYNOS4_CLKSRC_MASK_DMC		, .val = 0x00010000, },
};

static struct sleep_save exynos4210_set_clksrc[] = {
	{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1		, .val = 0x00001111, },
};

static struct sleep_save exynos4_epll_save[] = {
	SAVE_ITEM(EXYNOS4_EPLL_CON0),
	SAVE_ITEM(EXYNOS4_EPLL_CON1),
};

static struct sleep_save exynos4_vpll_save[] = {
	SAVE_ITEM(EXYNOS4_VPLL_CON0),
	SAVE_ITEM(EXYNOS4_VPLL_CON1),
};

static struct sleep_save exynos_core_save[] = {
	/* SROM side */
	SAVE_ITEM(S5P_SROM_BW),
	SAVE_ITEM(S5P_SROM_BC0),
	SAVE_ITEM(S5P_SROM_BC1),
	SAVE_ITEM(S5P_SROM_BC2),
	SAVE_ITEM(S5P_SROM_BC3),
};


/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];

static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
	outer_flush_all();
#endif

	if (soc_is_exynos5250())
		flush_cache_all();

	/* issue the standby signal into the pm unit. */
	cpu_do_idle();

	/* we should never get past here */
	panic("sleep resumed to originator?");
}

static void exynos_pm_prepare(void)
{
	unsigned int tmp;

	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (!soc_is_exynos5250()) {
		s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
		s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
	} else {
		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	}

	/* Set value of power down register for sleep mode */

	exynos_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);

	/* Before enter central sequence mode, clock src register have to set */

	if (!soc_is_exynos5250())
		s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));

	if (soc_is_exynos4210())
		s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));

}

static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
{
	pm_cpu_prep = exynos_pm_prepare;
	pm_cpu_sleep = exynos_cpu_suspend;

	return 0;
}

static unsigned long pll_base_rate;

static void exynos4_restore_pll(void)
{
	unsigned long pll_con, locktime, lockcnt;
	unsigned long pll_in_rate;
	unsigned int p_div, epll_wait = 0, vpll_wait = 0;

	if (pll_base_rate == 0)
		return;

	pll_in_rate = pll_base_rate;

	/* EPLL */
	pll_con = exynos4_epll_save[0].val;

	if (pll_con & (1 << 31)) {
		pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
		p_div = (pll_con >> PLL46XX_PDIV_SHIFT);

		pll_in_rate /= 1000000;

		locktime = (3000 / pll_in_rate) * p_div;
		lockcnt = locktime * 10000 / (10000 / pll_in_rate);

		__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);

		s3c_pm_do_restore_core(exynos4_epll_save,
					ARRAY_SIZE(exynos4_epll_save));
		epll_wait = 1;
	}

	pll_in_rate = pll_base_rate;

	/* VPLL */
	pll_con = exynos4_vpll_save[0].val;

	if (pll_con & (1 << 31)) {
		pll_in_rate /= 1000000;
		/* 750us */
		locktime = 750;
		lockcnt = locktime * 10000 / (10000 / pll_in_rate);

		__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);

		s3c_pm_do_restore_core(exynos4_vpll_save,
					ARRAY_SIZE(exynos4_vpll_save));
		vpll_wait = 1;
	}

	/* Wait PLL locking */

	do {
		if (epll_wait) {
			pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
			if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
				epll_wait = 0;
		}

		if (vpll_wait) {
			pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
			if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
				vpll_wait = 0;
		}
	} while (epll_wait || vpll_wait);
}

static struct subsys_interface exynos_pm_interface = {
	.name		= "exynos_pm",
	.subsys		= &exynos_subsys,
	.add_dev	= exynos_pm_add,
};

static __init int exynos_pm_drvinit(void)
{
	struct clk *pll_base;
	unsigned int tmp;

	s3c_pm_init();

	/* All wakeup disable */

	tmp = __raw_readl(S5P_WAKEUP_MASK);
	tmp |= ((0xFF << 8) | (0x1F << 1));
	__raw_writel(tmp, S5P_WAKEUP_MASK);

	if (!soc_is_exynos5250()) {
		pll_base = clk_get(NULL, "xtal");

		if (!IS_ERR(pll_base)) {
			pll_base_rate = clk_get_rate(pll_base);
			clk_put(pll_base);
		}
	}

	return subsys_interface_register(&exynos_pm_interface);
}
arch_initcall(exynos_pm_drvinit);

static int exynos_pm_suspend(void)
{
	unsigned long tmp;

	/* Setting Central Sequence Register for power down mode */

	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	/* Setting SEQ_OPTION register */

	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

	if (!soc_is_exynos5250()) {
		/* Save Power control register */
		asm ("mrc p15, 0, %0, c15, c0, 0"
		     : "=r" (tmp) : : "cc");
		save_arm_register[0] = tmp;

		/* Save Diagnostic register */
		asm ("mrc p15, 0, %0, c15, c0, 1"
		     : "=r" (tmp) : : "cc");
		save_arm_register[1] = tmp;
	}

	return 0;
}

static void exynos_pm_resume(void)
{
	unsigned long tmp;

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* No need to perform below restore code */
		goto early_wakeup;
	}
	if (!soc_is_exynos5250()) {
		/* Restore Power control register */
		tmp = save_arm_register[0];
		asm volatile ("mcr p15, 0, %0, c15, c0, 0"
			      : : "r" (tmp)
			      : "cc");

		/* Restore Diagnostic register */
		tmp = save_arm_register[1];
		asm volatile ("mcr p15, 0, %0, c15, c0, 1"
			      : : "r" (tmp)
			      : "cc");
	}

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (!soc_is_exynos5250()) {
		exynos4_restore_pll();

#ifdef CONFIG_SMP
		scu_enable(S5P_VA_SCU);
#endif
	}

early_wakeup:

	/* Clear SLEEP mode set in INFORM1 */
	__raw_writel(0x0, S5P_INFORM1);

	return;
}

static struct syscore_ops exynos_pm_syscore_ops = {
	.suspend	= exynos_pm_suspend,
	.resume		= exynos_pm_resume,
};

static __init int exynos_pm_syscore_init(void)
{
	register_syscore_ops(&exynos_pm_syscore_ops);
	return 0;
}
arch_initcall(exynos_pm_syscore_init);
Commit	Line	Data
c9347101 JL	1	/*
c9347101 JL	2	* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
1663895c JL	3	* http://www.samsung.com
1663895c JL	4	*
c9347101	5	* EXYNOS - Power Management support
1663895c JL	6	*
	7	* Based on arch/arm/mach-s3c2410/pm.c
	8	* Copyright (c) 2006 Simtec Electronics
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/suspend.h>
bb072c3c	18	#include <linux/syscore_ops.h>
1663895c	19	#include <linux/io.h>
56c03d91 JL	20	#include <linux/err.h>
56c03d91 JL	21	#include <linux/clk.h>
1663895c JL	22
	23	#include <asm/cacheflush.h>
	24	#include <asm/hardware/cache-l2x0.h>
63b870f1	25	#include <asm/smp_scu.h>
1663895c JL	26
	27	#include <plat/cpu.h>
	28	#include <plat/pm.h>
56c03d91	29	#include <plat/pll.h>
b93cb91b	30	#include <plat/regs-srom.h>
1663895c JL	31
	32	#include <mach/regs-irq.h>
	33	#include <mach/regs-gpio.h>
	34	#include <mach/regs-clock.h>
	35	#include <mach/regs-pmu.h>
	36	#include <mach/pm-core.h>
e4cf2d14	37	#include <mach/pmu.h>
1663895c JL	38
1663895c JL	39	static struct sleep_save exynos4_set_clksrc[] = {
a855039e KK	40	{ .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
	41	{ .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
	42	{ .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
	43	{ .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
	44	{ .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
	45	{ .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
	46	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
	47	{ .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
	48	{ .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
1663895c JL	49	};
1663895c JL	50
acd35616	51	static struct sleep_save exynos4210_set_clksrc[] = {
a855039e	52	{ .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
acd35616 JC	53	};
acd35616 JC	54
56c03d91	55	static struct sleep_save exynos4_epll_save[] = {
a855039e KK	56	SAVE_ITEM(EXYNOS4_EPLL_CON0),
a855039e KK	57	SAVE_ITEM(EXYNOS4_EPLL_CON1),
56c03d91 JL	58	};
	59
	60	static struct sleep_save exynos4_vpll_save[] = {
a855039e KK	61	SAVE_ITEM(EXYNOS4_VPLL_CON0),
a855039e KK	62	SAVE_ITEM(EXYNOS4_VPLL_CON1),
56c03d91 JL	63	};
56c03d91 JL	64
c9347101	65	static struct sleep_save exynos_core_save[] = {
b93cb91b MH	66	/* SROM side */
	67	SAVE_ITEM(S5P_SROM_BW),
	68	SAVE_ITEM(S5P_SROM_BC0),
	69	SAVE_ITEM(S5P_SROM_BC1),
	70	SAVE_ITEM(S5P_SROM_BC2),
	71	SAVE_ITEM(S5P_SROM_BC3),
1663895c JL	72	};
1663895c JL	73
1663895c	74
f4ba4b01 JL	75	/* For Cortex-A9 Diagnostic and Power control register */
	76	static unsigned int save_arm_register[2];
	77
c9347101	78	static int exynos_cpu_suspend(unsigned long arg)
1663895c	79	{
60e49ca6	80	#ifdef CONFIG_CACHE_L2X0
1663895c	81	outer_flush_all();
60e49ca6	82	#endif
1663895c	83
573e5bbe AK	84	if (soc_is_exynos5250())
	85	flush_cache_all();
	86
1663895c JL	87	/* issue the standby signal into the pm unit. */
	88	cpu_do_idle();
	89
	90	/* we should never get past here */
	91	panic("sleep resumed to originator?");
	92	}
	93
c9347101	94	static void exynos_pm_prepare(void)
1663895c	95	{
60e49ca6	96	unsigned int tmp;
1663895c	97
c9347101	98	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	99
60e49ca6 JL	100	if (!soc_is_exynos5250()) {
	101	s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
	102	s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
	103	} else {
	104	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
	105	tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
	106	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
	107	__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	108	}
1663895c JL	109
	110	/* Set value of power down register for sleep mode */
	111
7d44d2ba	112	exynos_sys_powerdown_conf(SYS_SLEEP);
1663895c JL	113	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
	114
	115	/* ensure at least INFORM0 has the resume address */
	116
	117	__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
	118
	119	/* Before enter central sequence mode, clock src register have to set */
	120
60e49ca6 JL	121	if (!soc_is_exynos5250())
60e49ca6 JL	122	s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
1663895c	123
acd35616 JC	124	if (soc_is_exynos4210())
	125	s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
	126
1663895c JL	127	}
1663895c JL	128
c9347101	129	static int exynos_pm_add(struct device dev, struct subsys_interface sif)
1663895c	130	{
c9347101 JL	131	pm_cpu_prep = exynos_pm_prepare;
c9347101 JL	132	pm_cpu_sleep = exynos_cpu_suspend;
1663895c JL	133
	134	return 0;
	135	}
	136
56c03d91 JL	137	static unsigned long pll_base_rate;
	138
	139	static void exynos4_restore_pll(void)
	140	{
	141	unsigned long pll_con, locktime, lockcnt;
	142	unsigned long pll_in_rate;
	143	unsigned int p_div, epll_wait = 0, vpll_wait = 0;
	144
	145	if (pll_base_rate == 0)
	146	return;
	147
	148	pll_in_rate = pll_base_rate;
	149
	150	/* EPLL */
	151	pll_con = exynos4_epll_save[0].val;
	152
	153	if (pll_con & (1 << 31)) {
	154	pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
	155	p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
	156
	157	pll_in_rate /= 1000000;
	158
	159	locktime = (3000 / pll_in_rate) * p_div;
	160	lockcnt = locktime * 10000 / (10000 / pll_in_rate);
	161
a855039e	162	__raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
56c03d91 JL	163
	164	s3c_pm_do_restore_core(exynos4_epll_save,
	165	ARRAY_SIZE(exynos4_epll_save));
	166	epll_wait = 1;
	167	}
	168
	169	pll_in_rate = pll_base_rate;
	170
	171	/* VPLL */
	172	pll_con = exynos4_vpll_save[0].val;
	173
	174	if (pll_con & (1 << 31)) {
	175	pll_in_rate /= 1000000;
	176	/* 750us */
	177	locktime = 750;
	178	lockcnt = locktime * 10000 / (10000 / pll_in_rate);
	179
a855039e	180	__raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
56c03d91 JL	181
	182	s3c_pm_do_restore_core(exynos4_vpll_save,
	183	ARRAY_SIZE(exynos4_vpll_save));
	184	vpll_wait = 1;
	185	}
	186
	187	/* Wait PLL locking */
	188
	189	do {
	190	if (epll_wait) {
a855039e KK	191	pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
a855039e KK	192	if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
56c03d91 JL	193	epll_wait = 0;
	194	}
	195
	196	if (vpll_wait) {
a855039e KK	197	pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
a855039e KK	198	if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
56c03d91 JL	199	vpll_wait = 0;
	200	}
	201	} while (epll_wait \|\| vpll_wait);
	202	}
	203
c9347101	204	static struct subsys_interface exynos_pm_interface = {
60e49ca6	205	.name = "exynos_pm",
9ee6af9c	206	.subsys = &exynos_subsys,
c9347101	207	.add_dev = exynos_pm_add,
bb072c3c RW	208	};
bb072c3c RW	209
c9347101	210	static __init int exynos_pm_drvinit(void)
bb072c3c	211	{
56c03d91	212	struct clk *pll_base;
bb072c3c RW	213	unsigned int tmp;
	214
	215	s3c_pm_init();
	216
	217	/* All wakeup disable */
	218
	219	tmp = __raw_readl(S5P_WAKEUP_MASK);
	220	tmp \|= ((0xFF << 8) \| (0x1F << 1));
	221	__raw_writel(tmp, S5P_WAKEUP_MASK);
	222
c9347101 JL	223	if (!soc_is_exynos5250()) {
c9347101 JL	224	pll_base = clk_get(NULL, "xtal");
56c03d91	225
c9347101 JL	226	if (!IS_ERR(pll_base)) {
	227	pll_base_rate = clk_get_rate(pll_base);
	228	clk_put(pll_base);
	229	}
56c03d91 JL	230	}
56c03d91 JL	231
c9347101	232	return subsys_interface_register(&exynos_pm_interface);
bb072c3c	233	}
c9347101	234	arch_initcall(exynos_pm_drvinit);
bb072c3c	235
c9347101	236	static int exynos_pm_suspend(void)
12974e9f JL	237	{
	238	unsigned long tmp;
	239
	240	/* Setting Central Sequence Register for power down mode */
	241
	242	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	243	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	244	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	245
60e49ca6	246	/* Setting SEQ_OPTION register */
00a351f2	247
60e49ca6 JL	248	tmp = (S5P_USE_STANDBY_WFI0 \| S5P_USE_STANDBY_WFE0);
60e49ca6 JL	249	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
f4ba4b01	250
60e49ca6 JL	251	if (!soc_is_exynos5250()) {
	252	/* Save Power control register */
	253	asm ("mrc p15, 0, %0, c15, c0, 0"
	254	: "=r" (tmp) : : "cc");
	255	save_arm_register[0] = tmp;
	256
	257	/* Save Diagnostic register */
	258	asm ("mrc p15, 0, %0, c15, c0, 1"
	259	: "=r" (tmp) : : "cc");
	260	save_arm_register[1] = tmp;
	261	}
f4ba4b01	262
12974e9f JL	263	return 0;
	264	}
	265
c9347101	266	static void exynos_pm_resume(void)
1663895c	267	{
e240ab1c JL	268	unsigned long tmp;
	269
	270	/*
	271	* If PMU failed while entering sleep mode, WFI will be
	272	* ignored by PMU and then exiting cpu_do_idle().
	273	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	274	* in this situation.
	275	*/
	276	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	277	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	278	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	279	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	280	/* No need to perform below restore code */
	281	goto early_wakeup;
	282	}
60e49ca6 JL	283	if (!soc_is_exynos5250()) {
	284	/* Restore Power control register */
	285	tmp = save_arm_register[0];
	286	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
	287	: : "r" (tmp)
	288	: "cc");
	289
	290	/* Restore Diagnostic register */
	291	tmp = save_arm_register[1];
	292	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
	293	: : "r" (tmp)
	294	: "cc");
	295	}
e240ab1c	296
1663895c JL	297	/* For release retention */
	298
	299	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	300	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	301	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	302	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	303	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	304	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	305	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
	306
c9347101	307	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	308
60e49ca6 JL	309	if (!soc_is_exynos5250()) {
60e49ca6 JL	310	exynos4_restore_pll();
56c03d91	311
556ef3e4	312	#ifdef CONFIG_SMP
60e49ca6	313	scu_enable(S5P_VA_SCU);
556ef3e4	314	#endif
60e49ca6	315	}
1663895c	316
e240ab1c	317	early_wakeup:
ebee8541 IS	318
	319	/* Clear SLEEP mode set in INFORM1 */
	320	__raw_writel(0x0, S5P_INFORM1);
	321
e240ab1c	322	return;
1663895c JL	323	}
1663895c JL	324
c9347101 JL	325	static struct syscore_ops exynos_pm_syscore_ops = {
	326	.suspend = exynos_pm_suspend,
	327	.resume = exynos_pm_resume,
1663895c JL	328	};
1663895c JL	329
60e49ca6	330	static __init int exynos_pm_syscore_init(void)
1663895c	331	{
c9347101	332	register_syscore_ops(&exynos_pm_syscore_ops);
bb072c3c	333	return 0;
1663895c	334	}
60e49ca6	335	arch_initcall(exynos_pm_syscore_init);