[deliverable/linux.git] / arch / arm / mach-exynos / pm.c

/*
 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS - Power Management support
 *
 * Based on arch/arm/mach-s3c2410/pm.c
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/init.h>
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/err.h>
#include <linux/clk.h>

#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/smp_scu.h>
#include <asm/suspend.h>

#include <plat/cpu.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>

#include <mach/map.h>

#include "common.h"
#include "regs-pmu.h"

/**
 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
 * @hwirq: Hardware IRQ signal of the GIC
 * @mask: Mask in PMU wake-up mask register
 */
struct exynos_wkup_irq {
	unsigned int hwirq;
	u32 mask;
};

static struct sleep_save exynos5_sys_save[] = {
	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
};

static struct sleep_save exynos_core_save[] = {
	/* SROM side */
	SAVE_ITEM(S5P_SROM_BW),
	SAVE_ITEM(S5P_SROM_BC0),
	SAVE_ITEM(S5P_SROM_BC1),
	SAVE_ITEM(S5P_SROM_BC2),
	SAVE_ITEM(S5P_SROM_BC3),
};

/*
 * GIC wake-up support
 */

static u32 exynos_irqwake_intmask = 0xffffffff;

static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	{ 76, BIT(1) }, /* RTC alarm */
	{ 77, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	{ 75, BIT(1) }, /* RTC alarm */
	{ 76, BIT(2) }, /* RTC tick */
	{ /* sentinel */ },
};

static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
{
	const struct exynos_wkup_irq *wkup_irq;

	if (soc_is_exynos5250())
		wkup_irq = exynos5250_wkup_irq;
	else
		wkup_irq = exynos4_wkup_irq;

	while (wkup_irq->mask) {
		if (wkup_irq->hwirq == data->hwirq) {
			if (!state)
				exynos_irqwake_intmask |= wkup_irq->mask;
			else
				exynos_irqwake_intmask &= ~wkup_irq->mask;
			return 0;
		}
		++wkup_irq;
	}

	return -ENOENT;
}

/**
 * exynos_core_power_down : power down the specified cpu
 * @cpu : the cpu to power down
 *
 * Power down the specified cpu. The sequence must be finished by a
 * call to cpu_do_idle()
 *
 */
void exynos_cpu_power_down(int cpu)
{
	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}

/**
 * exynos_cpu_power_up : power up the specified cpu
 * @cpu : the cpu to power up
 *
 * Power up the specified cpu
 */
void exynos_cpu_power_up(int cpu)
{
	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
		     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
}

/**
 * exynos_cpu_power_state : returns the power state of the cpu
 * @cpu : the cpu to retrieve the power state from
 *
 */
int exynos_cpu_power_state(int cpu)
{
	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
			S5P_CORE_LOCAL_PWR_EN);
}

/**
 * exynos_cluster_power_down : power down the specified cluster
 * @cluster : the cluster to power down
 */
void exynos_cluster_power_down(int cluster)
{
	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
}

/**
 * exynos_cluster_power_up : power up the specified cluster
 * @cluster : the cluster to power up
 */
void exynos_cluster_power_up(int cluster)
{
	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
		     EXYNOS_COMMON_CONFIGURATION(cluster));
}

/**
 * exynos_cluster_power_state : returns the power state of the cluster
 * @cluster : the cluster to retrieve the power state from
 *
 */
int exynos_cluster_power_state(int cluster)
{
	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
			S5P_CORE_LOCAL_PWR_EN);
}

/* For Cortex-A9 Diagnostic and Power control register */
static unsigned int save_arm_register[2];

static void exynos_cpu_save_register(void)
{
	unsigned long tmp;

	/* Save Power control register */
	asm ("mrc p15, 0, %0, c15, c0, 0"
	     : "=r" (tmp) : : "cc");

	save_arm_register[0] = tmp;

	/* Save Diagnostic register */
	asm ("mrc p15, 0, %0, c15, c0, 1"
	     : "=r" (tmp) : : "cc");

	save_arm_register[1] = tmp;
}

static void exynos_cpu_restore_register(void)
{
	unsigned long tmp;

	/* Restore Power control register */
	tmp = save_arm_register[0];

	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
		      : : "r" (tmp)
		      : "cc");

	/* Restore Diagnostic register */
	tmp = save_arm_register[1];

	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
		      : : "r" (tmp)
		      : "cc");
}

static int exynos_cpu_suspend(unsigned long arg)
{
#ifdef CONFIG_CACHE_L2X0
	outer_flush_all();
#endif

	if (soc_is_exynos5250())
		flush_cache_all();

	/* issue the standby signal into the pm unit. */
	cpu_do_idle();

	pr_info("Failed to suspend the system\n");
	return 1; /* Aborting suspend */
}

static void exynos_pm_prepare(void)
{
	unsigned int tmp;

	/* Set wake-up mask registers */
	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);

	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (soc_is_exynos5250()) {
		s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
		/* Disable USE_RETENTION of JPEG_MEM_OPTION */
		tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
		tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
		__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	}

	/* Set value of power down register for sleep mode */

	exynos_sys_powerdown_conf(SYS_SLEEP);
	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);

	/* ensure at least INFORM0 has the resume address */

	__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}

static int exynos_pm_suspend(void)
{
	unsigned long tmp;

	/* Setting Central Sequence Register for power down mode */

	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);

	/* Setting SEQ_OPTION register */

	tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);

	if (!soc_is_exynos5250())
		exynos_cpu_save_register();

	return 0;
}

static void exynos_pm_resume(void)
{
	unsigned long tmp;

	/*
	 * If PMU failed while entering sleep mode, WFI will be
	 * ignored by PMU and then exiting cpu_do_idle().
	 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	 * in this situation.
	 */
	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
		tmp |= S5P_CENTRAL_LOWPWR_CFG;
		__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
		/* clear the wakeup state register */
		__raw_writel(0x0, S5P_WAKEUP_STAT);
		/* No need to perform below restore code */
		goto early_wakeup;
	}

	if (!soc_is_exynos5250())
		exynos_cpu_restore_register();

	/* For release retention */

	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);

	if (soc_is_exynos5250())
		s3c_pm_do_restore(exynos5_sys_save,
			ARRAY_SIZE(exynos5_sys_save));

	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));

	if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
		scu_enable(S5P_VA_SCU);

early_wakeup:

	/* Clear SLEEP mode set in INFORM1 */
	__raw_writel(0x0, S5P_INFORM1);

	return;
}

static struct syscore_ops exynos_pm_syscore_ops = {
	.suspend	= exynos_pm_suspend,
	.resume		= exynos_pm_resume,
};

/*
 * Suspend Ops
 */

static int exynos_suspend_enter(suspend_state_t state)
{
	int ret;

	s3c_pm_debug_init();

	S3C_PMDBG("%s: suspending the system...\n", __func__);

	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
			exynos_irqwake_intmask, exynos_get_eint_wake_mask());

	if (exynos_irqwake_intmask == -1U
	    && exynos_get_eint_wake_mask() == -1U) {
		pr_err("%s: No wake-up sources!\n", __func__);
		pr_err("%s: Aborting sleep\n", __func__);
		return -EINVAL;
	}

	s3c_pm_save_uarts();
	exynos_pm_prepare();
	flush_cache_all();
	s3c_pm_check_store();

	ret = cpu_suspend(0, exynos_cpu_suspend);
	if (ret)
		return ret;

	s3c_pm_restore_uarts();

	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
			__raw_readl(S5P_WAKEUP_STAT));

	s3c_pm_check_restore();

	S3C_PMDBG("%s: resuming the system...\n", __func__);

	return 0;
}

static int exynos_suspend_prepare(void)
{
	s3c_pm_check_prepare();

	return 0;
}

static void exynos_suspend_finish(void)
{
	s3c_pm_check_cleanup();
}

static const struct platform_suspend_ops exynos_suspend_ops = {
	.enter		= exynos_suspend_enter,
	.prepare	= exynos_suspend_prepare,
	.finish		= exynos_suspend_finish,
	.valid		= suspend_valid_only_mem,
};

static int exynos_cpu_pm_notifier(struct notifier_block *self,
				  unsigned long cmd, void *v)
{
	int cpu = smp_processor_id();

	switch (cmd) {
	case CPU_PM_ENTER:
		if (cpu == 0)
			exynos_cpu_save_register();
		break;

	case CPU_PM_EXIT:
		if (cpu == 0)
			exynos_cpu_restore_register();
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block exynos_cpu_pm_notifier_block = {
	.notifier_call = exynos_cpu_pm_notifier,
};

void __init exynos_pm_init(void)
{
	u32 tmp;

	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);

	/* Platform-specific GIC callback */
	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;

	/* All wakeup disable */
	tmp = __raw_readl(S5P_WAKEUP_MASK);
	tmp |= ((0xFF << 8) | (0x1F << 1));
	__raw_writel(tmp, S5P_WAKEUP_MASK);

	register_syscore_ops(&exynos_pm_syscore_ops);
	suspend_set_ops(&exynos_suspend_ops);
}
Commit	Line	Data
c9347101 JL	1	/*
c9347101 JL	2	* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
1663895c JL	3	* http://www.samsung.com
1663895c JL	4	*
c9347101	5	* EXYNOS - Power Management support
1663895c JL	6	*
	7	* Based on arch/arm/mach-s3c2410/pm.c
	8	* Copyright (c) 2006 Simtec Electronics
	9	* Ben Dooks <ben@simtec.co.uk>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/init.h>
	17	#include <linux/suspend.h>
bb072c3c	18	#include <linux/syscore_ops.h>
85f9f908	19	#include <linux/cpu_pm.h>
1663895c	20	#include <linux/io.h>
dd8ac696	21	#include <linux/irqchip/arm-gic.h>
56c03d91 JL	22	#include <linux/err.h>
56c03d91 JL	23	#include <linux/clk.h>
1663895c JL	24
	25	#include <asm/cacheflush.h>
	26	#include <asm/hardware/cache-l2x0.h>
63b870f1	27	#include <asm/smp_scu.h>
d710aa31	28	#include <asm/suspend.h>
1663895c JL	29
1663895c JL	30	#include <plat/cpu.h>
d710aa31	31	#include <plat/pm-common.h>
56c03d91	32	#include <plat/pll.h>
b93cb91b	33	#include <plat/regs-srom.h>
1663895c	34
9c9239af	35	#include <mach/map.h>
ccd458c1 KK	36
ccd458c1 KK	37	#include "common.h"
65c9a853	38	#include "regs-pmu.h"
1663895c	39
dd8ac696 TF	40	/**
	41	* struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
	42	* @hwirq: Hardware IRQ signal of the GIC
	43	* @mask: Mask in PMU wake-up mask register
	44	*/
	45	struct exynos_wkup_irq {
	46	unsigned int hwirq;
	47	u32 mask;
	48	};
	49
86ffb0e8 AK	50	static struct sleep_save exynos5_sys_save[] = {
	51	SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
	52	};
	53
c9347101	54	static struct sleep_save exynos_core_save[] = {
b93cb91b MH	55	/* SROM side */
	56	SAVE_ITEM(S5P_SROM_BW),
	57	SAVE_ITEM(S5P_SROM_BC0),
	58	SAVE_ITEM(S5P_SROM_BC1),
	59	SAVE_ITEM(S5P_SROM_BC2),
	60	SAVE_ITEM(S5P_SROM_BC3),
1663895c JL	61	};
1663895c JL	62
dd8ac696 TF	63	/*
	64	* GIC wake-up support
	65	*/
	66
d710aa31	67	static u32 exynos_irqwake_intmask = 0xffffffff;
1663895c	68
dd8ac696 TF	69	static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
	70	{ 76, BIT(1) }, /* RTC alarm */
	71	{ 77, BIT(2) }, /* RTC tick */
	72	{ /* sentinel */ },
	73	};
	74
	75	static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
	76	{ 75, BIT(1) }, /* RTC alarm */
	77	{ 76, BIT(2) }, /* RTC tick */
	78	{ /* sentinel */ },
	79	};
	80
	81	static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
	82	{
	83	const struct exynos_wkup_irq *wkup_irq;
	84
	85	if (soc_is_exynos5250())
	86	wkup_irq = exynos5250_wkup_irq;
	87	else
	88	wkup_irq = exynos4_wkup_irq;
	89
	90	while (wkup_irq->mask) {
	91	if (wkup_irq->hwirq == data->hwirq) {
	92	if (!state)
	93	exynos_irqwake_intmask \|= wkup_irq->mask;
	94	else
	95	exynos_irqwake_intmask &= ~wkup_irq->mask;
	96	return 0;
	97	}
	98	++wkup_irq;
	99	}
	100
	101	return -ENOENT;
	102	}
	103
d3af6976 LKA	104	/**
	105	* exynos_core_power_down : power down the specified cpu
	106	* @cpu : the cpu to power down
	107	*
	108	* Power down the specified cpu. The sequence must be finished by a
	109	* call to cpu_do_idle()
	110	*
	111	*/
	112	void exynos_cpu_power_down(int cpu)
	113	{
	114	__raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
	115	}
	116
	117	/**
	118	* exynos_cpu_power_up : power up the specified cpu
	119	* @cpu : the cpu to power up
	120	*
	121	* Power up the specified cpu
	122	*/
	123	void exynos_cpu_power_up(int cpu)
	124	{
	125	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
	126	EXYNOS_ARM_CORE_CONFIGURATION(cpu));
	127	}
	128
	129	/**
	130	* exynos_cpu_power_state : returns the power state of the cpu
	131	* @cpu : the cpu to retrieve the power state from
	132	*
	133	*/
	134	int exynos_cpu_power_state(int cpu)
	135	{
	136	return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
	137	S5P_CORE_LOCAL_PWR_EN);
	138	}
	139
096d21c6 AK	140	/**
	141	* exynos_cluster_power_down : power down the specified cluster
	142	* @cluster : the cluster to power down
	143	*/
	144	void exynos_cluster_power_down(int cluster)
	145	{
	146	__raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
	147	}
	148
	149	/**
	150	* exynos_cluster_power_up : power up the specified cluster
	151	* @cluster : the cluster to power up
	152	*/
	153	void exynos_cluster_power_up(int cluster)
	154	{
	155	__raw_writel(S5P_CORE_LOCAL_PWR_EN,
	156	EXYNOS_COMMON_CONFIGURATION(cluster));
	157	}
	158
	159	/**
	160	* exynos_cluster_power_state : returns the power state of the cluster
	161	* @cluster : the cluster to retrieve the power state from
	162	*
	163	*/
	164	int exynos_cluster_power_state(int cluster)
	165	{
	166	return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
	167	S5P_CORE_LOCAL_PWR_EN);
	168	}
	169
f4ba4b01 JL	170	/* For Cortex-A9 Diagnostic and Power control register */
	171	static unsigned int save_arm_register[2];
	172
309e08c4 DL	173	static void exynos_cpu_save_register(void)
	174	{
	175	unsigned long tmp;
	176
	177	/* Save Power control register */
	178	asm ("mrc p15, 0, %0, c15, c0, 0"
	179	: "=r" (tmp) : : "cc");
	180
	181	save_arm_register[0] = tmp;
	182
	183	/* Save Diagnostic register */
	184	asm ("mrc p15, 0, %0, c15, c0, 1"
	185	: "=r" (tmp) : : "cc");
	186
	187	save_arm_register[1] = tmp;
	188	}
	189
	190	static void exynos_cpu_restore_register(void)
	191	{
	192	unsigned long tmp;
	193
	194	/* Restore Power control register */
	195	tmp = save_arm_register[0];
	196
	197	asm volatile ("mcr p15, 0, %0, c15, c0, 0"
	198	: : "r" (tmp)
	199	: "cc");
	200
	201	/* Restore Diagnostic register */
	202	tmp = save_arm_register[1];
	203
	204	asm volatile ("mcr p15, 0, %0, c15, c0, 1"
	205	: : "r" (tmp)
	206	: "cc");
	207	}
	208
c9347101	209	static int exynos_cpu_suspend(unsigned long arg)
1663895c	210	{
60e49ca6	211	#ifdef CONFIG_CACHE_L2X0
1663895c	212	outer_flush_all();
60e49ca6	213	#endif
1663895c	214
573e5bbe AK	215	if (soc_is_exynos5250())
	216	flush_cache_all();
	217
1663895c JL	218	/* issue the standby signal into the pm unit. */
	219	cpu_do_idle();
	220
d3fcacf5 AK	221	pr_info("Failed to suspend the system\n");
d3fcacf5 AK	222	return 1; /* Aborting suspend */
1663895c JL	223	}
1663895c JL	224
c9347101	225	static void exynos_pm_prepare(void)
1663895c	226	{
60e49ca6	227	unsigned int tmp;
1663895c	228
d710aa31 TF	229	/* Set wake-up mask registers */
	230	__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
	231	__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
	232
c9347101	233	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	234
e11d919e	235	if (soc_is_exynos5250()) {
86ffb0e8	236	s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
60e49ca6 JL	237	/* Disable USE_RETENTION of JPEG_MEM_OPTION */
	238	tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
	239	tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
	240	__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
	241	}
1663895c JL	242
	243	/* Set value of power down register for sleep mode */
	244
7d44d2ba	245	exynos_sys_powerdown_conf(SYS_SLEEP);
1663895c JL	246	__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
	247
	248	/* ensure at least INFORM0 has the resume address */
	249
d710aa31	250	__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
1663895c JL	251	}
1663895c JL	252
c9347101	253	static int exynos_pm_suspend(void)
12974e9f JL	254	{
	255	unsigned long tmp;
	256
	257	/* Setting Central Sequence Register for power down mode */
	258
	259	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	260	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
	261	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
	262
60e49ca6	263	/* Setting SEQ_OPTION register */
00a351f2	264
60e49ca6 JL	265	tmp = (S5P_USE_STANDBY_WFI0 \| S5P_USE_STANDBY_WFE0);
60e49ca6 JL	266	__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
f4ba4b01	267
309e08c4 DL	268	if (!soc_is_exynos5250())
309e08c4 DL	269	exynos_cpu_save_register();
f4ba4b01	270
12974e9f JL	271	return 0;
	272	}
	273
c9347101	274	static void exynos_pm_resume(void)
1663895c	275	{
e240ab1c JL	276	unsigned long tmp;
	277
	278	/*
	279	* If PMU failed while entering sleep mode, WFI will be
	280	* ignored by PMU and then exiting cpu_do_idle().
	281	* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
	282	* in this situation.
	283	*/
	284	tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
	285	if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
	286	tmp \|= S5P_CENTRAL_LOWPWR_CFG;
	287	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
d3fcacf5 AK	288	/* clear the wakeup state register */
d3fcacf5 AK	289	__raw_writel(0x0, S5P_WAKEUP_STAT);
e240ab1c JL	290	/* No need to perform below restore code */
	291	goto early_wakeup;
	292	}
309e08c4 DL	293
	294	if (!soc_is_exynos5250())
	295	exynos_cpu_restore_register();
e240ab1c	296
1663895c JL	297	/* For release retention */
	298
	299	__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
	300	__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
	301	__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
	302	__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
	303	__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
	304	__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
	305	__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
	306
86ffb0e8 AK	307	if (soc_is_exynos5250())
	308	s3c_pm_do_restore(exynos5_sys_save,
	309	ARRAY_SIZE(exynos5_sys_save));
	310
c9347101	311	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
1663895c	312
e11d919e	313	if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
60e49ca6	314	scu_enable(S5P_VA_SCU);
1663895c	315
e240ab1c	316	early_wakeup:
ebee8541 IS	317
	318	/* Clear SLEEP mode set in INFORM1 */
	319	__raw_writel(0x0, S5P_INFORM1);
	320
e240ab1c	321	return;
1663895c JL	322	}
1663895c JL	323
c9347101 JL	324	static struct syscore_ops exynos_pm_syscore_ops = {
	325	.suspend = exynos_pm_suspend,
	326	.resume = exynos_pm_resume,
1663895c JL	327	};
1663895c JL	328
d710aa31 TF	329	/*
	330	* Suspend Ops
	331	*/
	332
	333	static int exynos_suspend_enter(suspend_state_t state)
1663895c	334	{
d710aa31 TF	335	int ret;
	336
	337	s3c_pm_debug_init();
	338
	339	S3C_PMDBG("%s: suspending the system...\n", __func__);
	340
	341	S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
	342	exynos_irqwake_intmask, exynos_get_eint_wake_mask());
559ba237	343
d710aa31 TF	344	if (exynos_irqwake_intmask == -1U
	345	&& exynos_get_eint_wake_mask() == -1U) {
	346	pr_err("%s: No wake-up sources!\n", __func__);
	347	pr_err("%s: Aborting sleep\n", __func__);
	348	return -EINVAL;
	349	}
	350
	351	s3c_pm_save_uarts();
	352	exynos_pm_prepare();
	353	flush_cache_all();
	354	s3c_pm_check_store();
	355
	356	ret = cpu_suspend(0, exynos_cpu_suspend);
	357	if (ret)
	358	return ret;
	359
	360	s3c_pm_restore_uarts();
559ba237	361
d710aa31 TF	362	S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
	363	__raw_readl(S5P_WAKEUP_STAT));
	364
	365	s3c_pm_check_restore();
	366
	367	S3C_PMDBG("%s: resuming the system...\n", __func__);
	368
	369	return 0;
	370	}
	371
	372	static int exynos_suspend_prepare(void)
	373	{
	374	s3c_pm_check_prepare();
	375
	376	return 0;
	377	}
	378
	379	static void exynos_suspend_finish(void)
	380	{
	381	s3c_pm_check_cleanup();
	382	}
	383
	384	static const struct platform_suspend_ops exynos_suspend_ops = {
	385	.enter = exynos_suspend_enter,
	386	.prepare = exynos_suspend_prepare,
	387	.finish = exynos_suspend_finish,
	388	.valid = suspend_valid_only_mem,
	389	};
	390
85f9f908 DL	391	static int exynos_cpu_pm_notifier(struct notifier_block *self,
	392	unsigned long cmd, void *v)
	393	{
	394	int cpu = smp_processor_id();
	395
	396	switch (cmd) {
	397	case CPU_PM_ENTER:
	398	if (cpu == 0)
	399	exynos_cpu_save_register();
	400	break;
	401
	402	case CPU_PM_EXIT:
	403	if (cpu == 0)
	404	exynos_cpu_restore_register();
	405	break;
	406	}
	407
	408	return NOTIFY_OK;
	409	}
	410
	411	static struct notifier_block exynos_cpu_pm_notifier_block = {
	412	.notifier_call = exynos_cpu_pm_notifier,
	413	};
	414
d710aa31 TF	415	void __init exynos_pm_init(void)
	416	{
	417	u32 tmp;
559ba237	418
85f9f908 DL	419	cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
85f9f908 DL	420
dd8ac696 TF	421	/* Platform-specific GIC callback */
	422	gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
	423
559ba237 TF	424	/* All wakeup disable */
	425	tmp = __raw_readl(S5P_WAKEUP_MASK);
	426	tmp \|= ((0xFF << 8) \| (0x1F << 1));
	427	__raw_writel(tmp, S5P_WAKEUP_MASK);
e085cad6	428
c9347101	429	register_syscore_ops(&exynos_pm_syscore_ops);
d710aa31	430	suspend_set_ops(&exynos_suspend_ops);
1663895c	431	}