[deliverable/linux.git] / arch / arm / mach-exynos / pm_domains.c

/*
 * Exynos Generic power domain support.
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Implementation of Exynos specific power domain control which is used in
 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
 * based power domain support is included.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/io.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/pm_domain.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sched.h>

#define INT_LOCAL_PWR_EN	0x7
#define MAX_CLK_PER_DOMAIN	4

/*
 * Exynos specific wrapper around the generic power domain
 */
struct exynos_pm_domain {
	void __iomem *base;
	char const *name;
	bool is_off;
	struct generic_pm_domain pd;
	struct clk *oscclk;
	struct clk *clk[MAX_CLK_PER_DOMAIN];
	struct clk *pclk[MAX_CLK_PER_DOMAIN];
};

static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
{
	struct exynos_pm_domain *pd;
	void __iomem *base;
	u32 timeout, pwr;
	char *op;

	pd = container_of(domain, struct exynos_pm_domain, pd);
	base = pd->base;

	/* Set oscclk before powering off a domain*/
	if (!power_on) {
		int i;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;
			if (clk_set_parent(pd->clk[i], pd->oscclk))
				pr_err("%s: error setting oscclk as parent to clock %d\n",
						pd->name, i);
		}
	}

	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
	__raw_writel(pwr, base);

	/* Wait max 1ms */
	timeout = 10;

	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
		if (!timeout) {
			op = (power_on) ? "enable" : "disable";
			pr_err("Power domain %s %s failed\n", domain->name, op);
			return -ETIMEDOUT;
		}
		timeout--;
		cpu_relax();
		usleep_range(80, 100);
	}

	/* Restore clocks after powering on a domain*/
	if (power_on) {
		int i;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;
			if (clk_set_parent(pd->clk[i], pd->pclk[i]))
				pr_err("%s: error setting parent to clock%d\n",
						pd->name, i);
		}
	}

	return 0;
}

static int exynos_pd_power_on(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, true);
}

static int exynos_pd_power_off(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, false);
}

static __init int exynos4_pm_init_power_domain(void)
{
	struct platform_device *pdev;
	struct device_node *np;

	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct exynos_pm_domain *pd;
		int on, i;
		struct device *dev;

		pdev = of_find_device_by_node(np);
		dev = &pdev->dev;

		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
		if (!pd) {
			pr_err("%s: failed to allocate memory for domain\n",
					__func__);
			return -ENOMEM;
		}

		pd->pd.name = kstrdup(np->name, GFP_KERNEL);
		pd->name = pd->pd.name;
		pd->base = of_iomap(np, 0);
		pd->pd.power_off = exynos_pd_power_off;
		pd->pd.power_on = exynos_pd_power_on;

		pd->oscclk = clk_get(dev, "oscclk");
		if (IS_ERR(pd->oscclk))
			goto no_clk;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			char clk_name[8];

			snprintf(clk_name, sizeof(clk_name), "clk%d", i);
			pd->clk[i] = clk_get(dev, clk_name);
			if (IS_ERR(pd->clk[i]))
				break;
			snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
			pd->pclk[i] = clk_get(dev, clk_name);
			if (IS_ERR(pd->pclk[i])) {
				clk_put(pd->clk[i]);
				pd->clk[i] = ERR_PTR(-EINVAL);
				break;
			}
		}

		if (IS_ERR(pd->clk[0]))
			clk_put(pd->oscclk);

no_clk:
		on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;

		pm_genpd_init(&pd->pd, NULL, !on);
		of_genpd_add_provider_simple(np, &pd->pd);
	}

	/* Assign the child power domains to their parents */
	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct generic_pm_domain *child_domain, *parent_domain;
		struct of_phandle_args args;

		args.np = np;
		args.args_count = 0;
		child_domain = of_genpd_get_from_provider(&args);
		if (!child_domain)
			continue;

		if (of_parse_phandle_with_args(np, "power-domains",
					 "#power-domain-cells", 0, &args) != 0)
			continue;

		parent_domain = of_genpd_get_from_provider(&args);
		if (!parent_domain)
			continue;

		if (pm_genpd_add_subdomain(parent_domain, child_domain))
			pr_warn("%s failed to add subdomain: %s\n",
				parent_domain->name, child_domain->name);
		else
			pr_info("%s has as child subdomain: %s.\n",
				parent_domain->name, child_domain->name);
		of_node_put(np);
	}

	return 0;
}
arch_initcall(exynos4_pm_init_power_domain);
Commit	Line	Data
91cfbd4e TA	1	/*
	2	* Exynos Generic power domain support.
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Implementation of Exynos specific power domain control which is used in
	8	* conjunction with runtime-pm. Support for both device-tree and non-device-tree
	9	* based power domain support is included.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
	19	#include <linux/pm_domain.h>
c760569d	20	#include <linux/clk.h>
91cfbd4e TA	21	#include <linux/delay.h>
91cfbd4e TA	22	#include <linux/of_address.h>
8a65d236 TF	23	#include <linux/of_platform.h>
8a65d236 TF	24	#include <linux/sched.h>
91cfbd4e	25
b634e38f	26	#define INT_LOCAL_PWR_EN 0x7
c760569d P	27	#define MAX_CLK_PER_DOMAIN 4
c760569d P	28
91cfbd4e TA	29	/*
	30	* Exynos specific wrapper around the generic power domain
	31	*/
	32	struct exynos_pm_domain {
	33	void __iomem *base;
	34	char const *name;
	35	bool is_off;
	36	struct generic_pm_domain pd;
c760569d P	37	struct clk *oscclk;
	38	struct clk *clk[MAX_CLK_PER_DOMAIN];
	39	struct clk *pclk[MAX_CLK_PER_DOMAIN];
91cfbd4e TA	40	};
	41
	42	static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
	43	{
	44	struct exynos_pm_domain *pd;
	45	void __iomem *base;
	46	u32 timeout, pwr;
	47	char *op;
	48
	49	pd = container_of(domain, struct exynos_pm_domain, pd);
	50	base = pd->base;
	51
c760569d P	52	/* Set oscclk before powering off a domain*/
	53	if (!power_on) {
	54	int i;
	55
	56	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	57	if (IS_ERR(pd->clk[i]))
	58	break;
	59	if (clk_set_parent(pd->clk[i], pd->oscclk))
	60	pr_err("%s: error setting oscclk as parent to clock %d\n",
	61	pd->name, i);
	62	}
	63	}
	64
b634e38f	65	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
91cfbd4e TA	66	__raw_writel(pwr, base);
	67
	68	/* Wait max 1ms */
	69	timeout = 10;
	70
b634e38f	71	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
91cfbd4e TA	72	if (!timeout) {
	73	op = (power_on) ? "enable" : "disable";
	74	pr_err("Power domain %s %s failed\n", domain->name, op);
	75	return -ETIMEDOUT;
	76	}
	77	timeout--;
	78	cpu_relax();
	79	usleep_range(80, 100);
	80	}
c760569d P	81
	82	/* Restore clocks after powering on a domain*/
	83	if (power_on) {
	84	int i;
	85
	86	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	87	if (IS_ERR(pd->clk[i]))
	88	break;
	89	if (clk_set_parent(pd->clk[i], pd->pclk[i]))
	90	pr_err("%s: error setting parent to clock%d\n",
	91	pd->name, i);
	92	}
	93	}
	94
91cfbd4e TA	95	return 0;
	96	}
	97
	98	static int exynos_pd_power_on(struct generic_pm_domain *domain)
	99	{
	100	return exynos_pd_power(domain, true);
	101	}
	102
	103	static int exynos_pd_power_off(struct generic_pm_domain *domain)
	104	{
	105	return exynos_pd_power(domain, false);
	106	}
	107
8eaa9e42	108	static __init int exynos4_pm_init_power_domain(void)
91cfbd4e	109	{
8a65d236	110	struct platform_device *pdev;
91cfbd4e TA	111	struct device_node *np;
	112
	113	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	114	struct exynos_pm_domain *pd;
c760569d P	115	int on, i;
c760569d P	116	struct device *dev;
91cfbd4e	117
8a65d236	118	pdev = of_find_device_by_node(np);
c760569d	119	dev = &pdev->dev;
8a65d236	120
91cfbd4e TA	121	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
	122	if (!pd) {
	123	pr_err("%s: failed to allocate memory for domain\n",
	124	__func__);
	125	return -ENOMEM;
	126	}
	127
7add0ec0 TF	128	pd->pd.name = kstrdup(np->name, GFP_KERNEL);
7add0ec0 TF	129	pd->name = pd->pd.name;
91cfbd4e TA	130	pd->base = of_iomap(np, 0);
	131	pd->pd.power_off = exynos_pd_power_off;
	132	pd->pd.power_on = exynos_pd_power_on;
2ed5f236	133
c760569d P	134	pd->oscclk = clk_get(dev, "oscclk");
	135	if (IS_ERR(pd->oscclk))
	136	goto no_clk;
	137
	138	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	139	char clk_name[8];
	140
	141	snprintf(clk_name, sizeof(clk_name), "clk%d", i);
	142	pd->clk[i] = clk_get(dev, clk_name);
	143	if (IS_ERR(pd->clk[i]))
	144	break;
	145	snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
	146	pd->pclk[i] = clk_get(dev, clk_name);
	147	if (IS_ERR(pd->pclk[i])) {
	148	clk_put(pd->clk[i]);
	149	pd->clk[i] = ERR_PTR(-EINVAL);
	150	break;
	151	}
	152	}
	153
	154	if (IS_ERR(pd->clk[0]))
	155	clk_put(pd->oscclk);
	156
	157	no_clk:
b634e38f	158	on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
2ed5f236 TF	159
2ed5f236 TF	160	pm_genpd_init(&pd->pd, NULL, !on);
a4a8c2c4	161	of_genpd_add_provider_simple(np, &pd->pd);
91cfbd4e	162	}
8a65d236	163
0f780751 MS	164	/* Assign the child power domains to their parents */
	165	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	166	struct generic_pm_domain child_domain, parent_domain;
	167	struct of_phandle_args args;
	168
	169	args.np = np;
	170	args.args_count = 0;
	171	child_domain = of_genpd_get_from_provider(&args);
	172	if (!child_domain)
	173	continue;
	174
	175	if (of_parse_phandle_with_args(np, "power-domains",
	176	"#power-domain-cells", 0, &args) != 0)
	177	continue;
	178
	179	parent_domain = of_genpd_get_from_provider(&args);
	180	if (!parent_domain)
	181	continue;
	182
	183	if (pm_genpd_add_subdomain(parent_domain, child_domain))
	184	pr_warn("%s failed to add subdomain: %s\n",
	185	parent_domain->name, child_domain->name);
	186	else
	187	pr_info("%s has as child subdomain: %s.\n",
	188	parent_domain->name, child_domain->name);
	189	of_node_put(np);
	190	}
	191
91cfbd4e TA	192	return 0;
91cfbd4e TA	193	}
91cfbd4e	194	arch_initcall(exynos4_pm_init_power_domain);