projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d44d2ba JL |
1 | /* |
| 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. | |
| d6d8b481 CY |
3 | * http://www.samsung.com |
| 4 | * | |
| 7d44d2ba | 5 | * EXYNOS - Power management unit definition |
| d6d8b481 CY |
6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __ASM_ARCH_REGS_PMU_H | |
| 13 | #define __ASM_ARCH_REGS_PMU_H __FILE__ | |
| 14 | ||
| 2e94ac42 | 15 | #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 |
| d6d8b481 | 16 | |
| b77ca655 JL |
17 | #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) |
| 18 | ||
| 2e94ac42 | 19 | #define S5P_CENTRAL_SEQ_OPTION 0x0208 |
| b77ca655 JL |
20 | |
| 21 | #define S5P_USE_STANDBY_WFI0 (1 << 16) | |
| b77ca655 | 22 | #define S5P_USE_STANDBY_WFE0 (1 << 24) |
| b77ca655 | 23 | |
| 2e94ac42 PD |
24 | #define EXYNOS_SWRESET 0x0400 |
| 25 | #define EXYNOS5440_SWRESET 0x00C4 | |
| 26 | ||
| 27 | #define S5P_WAKEUP_STAT 0x0600 | |
| 28 | #define S5P_EINT_WAKEUP_MASK 0x0604 | |
| 29 | #define S5P_WAKEUP_MASK 0x0608 | |
| 30 | ||
| 31 | #define S5P_INFORM0 0x0800 | |
| 32 | #define S5P_INFORM1 0x0804 | |
| 33 | #define S5P_INFORM5 0x0814 | |
| 34 | #define S5P_INFORM6 0x0818 | |
| 35 | #define S5P_INFORM7 0x081C | |
| 36 | #define S5P_PMU_SPARE3 0x090C | |
| 37 | ||
| 38 | #define S5P_ARM_CORE0_LOWPWR 0x1000 | |
| 39 | #define S5P_DIS_IRQ_CORE0 0x1004 | |
| 40 | #define S5P_DIS_IRQ_CENTRAL0 0x1008 | |
| 41 | #define S5P_ARM_CORE1_LOWPWR 0x1010 | |
| 42 | #define S5P_DIS_IRQ_CORE1 0x1014 | |
| 43 | #define S5P_DIS_IRQ_CENTRAL1 0x1018 | |
| 44 | #define S5P_ARM_COMMON_LOWPWR 0x1080 | |
| 45 | #define S5P_L2_0_LOWPWR 0x10C0 | |
| 46 | #define S5P_L2_1_LOWPWR 0x10C4 | |
| 47 | #define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 | |
| 48 | #define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 | |
| 49 | #define S5P_CMU_RESET_LOWPWR 0x110C | |
| 50 | #define S5P_APLL_SYSCLK_LOWPWR 0x1120 | |
| 51 | #define S5P_MPLL_SYSCLK_LOWPWR 0x1124 | |
| 52 | #define S5P_VPLL_SYSCLK_LOWPWR 0x1128 | |
| 53 | #define S5P_EPLL_SYSCLK_LOWPWR 0x112C | |
| 54 | #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 | |
| 55 | #define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C | |
| 56 | #define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 | |
| 57 | #define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 | |
| 58 | #define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 | |
| 59 | #define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C | |
| 60 | #define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 | |
| 61 | #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 | |
| 62 | #define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C | |
| 63 | #define S5P_CMU_RESET_CAM_LOWPWR 0x1160 | |
| 64 | #define S5P_CMU_RESET_TV_LOWPWR 0x1164 | |
| 65 | #define S5P_CMU_RESET_MFC_LOWPWR 0x1168 | |
| 66 | #define S5P_CMU_RESET_G3D_LOWPWR 0x116C | |
| 67 | #define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 | |
| 68 | #define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 | |
| 69 | #define S5P_CMU_RESET_GPS_LOWPWR 0x117C | |
| 70 | #define S5P_TOP_BUS_LOWPWR 0x1180 | |
| 71 | #define S5P_TOP_RETENTION_LOWPWR 0x1184 | |
| 72 | #define S5P_TOP_PWR_LOWPWR 0x1188 | |
| 73 | #define S5P_LOGIC_RESET_LOWPWR 0x11A0 | |
| 74 | #define S5P_ONENAND_MEM_LOWPWR 0x11C0 | |
| 75 | #define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 | |
| 76 | #define S5P_USBOTG_MEM_LOWPWR 0x11CC | |
| 77 | #define S5P_HSMMC_MEM_LOWPWR 0x11D0 | |
| 78 | #define S5P_CSSYS_MEM_LOWPWR 0x11D4 | |
| 79 | #define S5P_SECSS_MEM_LOWPWR 0x11D8 | |
| 80 | #define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 | |
| 81 | #define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 | |
| 82 | #define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 | |
| 83 | #define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 | |
| 84 | #define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 | |
| 85 | #define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C | |
| 86 | #define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 | |
| 87 | #define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 | |
| 88 | #define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 | |
| 89 | #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 | |
| 90 | #define S5P_XUSBXTI_LOWPWR 0x1280 | |
| 91 | #define S5P_XXTI_LOWPWR 0x1284 | |
| 92 | #define S5P_EXT_REGULATOR_LOWPWR 0x12C0 | |
| 93 | #define S5P_GPIO_MODE_LOWPWR 0x1300 | |
| 94 | #define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 | |
| 95 | #define S5P_CAM_LOWPWR 0x1380 | |
| 96 | #define S5P_TV_LOWPWR 0x1384 | |
| 97 | #define S5P_MFC_LOWPWR 0x1388 | |
| 98 | #define S5P_G3D_LOWPWR 0x138C | |
| 99 | #define S5P_LCD0_LOWPWR 0x1390 | |
| 100 | #define S5P_MAUDIO_LOWPWR 0x1398 | |
| 101 | #define S5P_GPS_LOWPWR 0x139C | |
| 102 | #define S5P_GPS_ALIVE_LOWPWR 0x13A0 | |
| 103 | ||
| 104 | #define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 | |
| d3af6976 LKA |
105 | #define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ |
| 106 | (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) | |
| 107 | #define EXYNOS_ARM_CORE_STATUS(_nr) \ | |
| 108 | (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) | |
| 109 | ||
| 2e94ac42 | 110 | #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 |
| 096d21c6 AK |
111 | #define EXYNOS_COMMON_CONFIGURATION(_nr) \ |
| 112 | (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) | |
| 113 | #define EXYNOS_COMMON_STATUS(_nr) \ | |
| 114 | (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) | |
| 20fe6f98 AK |
115 | #define EXYNOS_COMMON_OPTION(_nr) \ |
| 116 | (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) | |
| 096d21c6 | 117 | |
| 2e94ac42 PD |
118 | #define S5P_PAD_RET_MAUDIO_OPTION 0x3028 |
| 119 | #define S5P_PAD_RET_GPIO_OPTION 0x3108 | |
| 120 | #define S5P_PAD_RET_UART_OPTION 0x3128 | |
| 121 | #define S5P_PAD_RET_MMCA_OPTION 0x3148 | |
| 122 | #define S5P_PAD_RET_MMCB_OPTION 0x3168 | |
| 123 | #define S5P_PAD_RET_EBIA_OPTION 0x3188 | |
| 124 | #define S5P_PAD_RET_EBIB_OPTION 0x31A8 | |
| b77ca655 | 125 | |
| 911c29b0 | 126 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
| b77ca655 | 127 | |
| 9a94296c | 128 | /* Only for EXYNOS4210 */ |
| 2e94ac42 PD |
129 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 |
| 130 | #define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 | |
| 131 | #define S5P_MODIMIF_MEM_LOWPWR 0x11C4 | |
| 132 | #define S5P_PCIE_MEM_LOWPWR 0x11E0 | |
| 133 | #define S5P_SATA_MEM_LOWPWR 0x11E4 | |
| 134 | #define S5P_LCD1_LOWPWR 0x1394 | |
| 9a94296c | 135 | |
| 5ddfa842 | 136 | /* Only for EXYNOS4x12 */ |
| 2e94ac42 PD |
137 | #define S5P_ISP_ARM_LOWPWR 0x1050 |
| 138 | #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 | |
| 139 | #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 | |
| 140 | #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 | |
| 141 | #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 | |
| 142 | #define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C | |
| 143 | #define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 | |
| 144 | #define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 | |
| 145 | #define S5P_CMU_RESET_ISP_LOWPWR 0x1174 | |
| 146 | #define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 | |
| 147 | #define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 | |
| 148 | #define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 | |
| 149 | #define S5P_OSCCLK_GATE_LOWPWR 0x11A4 | |
| 150 | #define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 | |
| 151 | #define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 | |
| 152 | #define S5P_HSI_MEM_LOWPWR 0x11C4 | |
| 153 | #define S5P_ROTATOR_MEM_LOWPWR 0x11DC | |
| 154 | #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C | |
| 155 | #define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 | |
| 156 | #define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 | |
| 157 | #define S5P_TOP_ASB_RESET_LOWPWR 0x1344 | |
| 158 | #define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 | |
| 159 | #define S5P_ISP_LOWPWR 0x1394 | |
| 160 | #define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 | |
| 161 | #define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 | |
| 162 | #define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 | |
| 163 | #define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC | |
| 164 | #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 | |
| 165 | ||
| 166 | #define S5P_ARM_L2_0_OPTION 0x2608 | |
| 167 | #define S5P_ARM_L2_1_OPTION 0x2628 | |
| 168 | #define S5P_ONENAND_MEM_OPTION 0x2E08 | |
| 169 | #define S5P_HSI_MEM_OPTION 0x2E28 | |
| 170 | #define S5P_G2D_ACP_MEM_OPTION 0x2E48 | |
| 171 | #define S5P_USBOTG_MEM_OPTION 0x2E68 | |
| 172 | #define S5P_HSMMC_MEM_OPTION 0x2E88 | |
| 173 | #define S5P_CSSYS_MEM_OPTION 0x2EA8 | |
| 174 | #define S5P_SECSS_MEM_OPTION 0x2EC8 | |
| 175 | #define S5P_ROTATOR_MEM_OPTION 0x2F48 | |
| 9a94296c | 176 | |
| 5ddfa842 | 177 | /* Only for EXYNOS4412 */ |
| 2e94ac42 PD |
178 | #define S5P_ARM_CORE2_LOWPWR 0x1020 |
| 179 | #define S5P_DIS_IRQ_CORE2 0x1024 | |
| 180 | #define S5P_DIS_IRQ_CENTRAL2 0x1028 | |
| 181 | #define S5P_ARM_CORE3_LOWPWR 0x1030 | |
| 182 | #define S5P_DIS_IRQ_CORE3 0x1034 | |
| 183 | #define S5P_DIS_IRQ_CENTRAL3 0x1038 | |
| 5ddfa842 | 184 | |
| 7d44d2ba JL |
185 | /* For EXYNOS5 */ |
| 186 | ||
| 2e94ac42 PD |
187 | #define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 |
| 188 | #define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C | |
| 7d896aac JC |
189 | |
| 190 | #define EXYNOS5_SYS_WDTRESET (1 << 20) | |
| 191 | ||
| 2e94ac42 PD |
192 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 |
| 193 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 | |
| 194 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 | |
| 195 | #define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 | |
| 196 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 | |
| 197 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 | |
| 198 | #define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 | |
| 199 | #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 | |
| 200 | #define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 | |
| 201 | #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 | |
| 202 | #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 | |
| 203 | #define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 | |
| 204 | #define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 | |
| 205 | #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 | |
| 206 | #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 | |
| 207 | #define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C | |
| 208 | #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 | |
| 209 | #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 | |
| 210 | #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C | |
| 211 | #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 | |
| 212 | #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 | |
| 213 | #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 | |
| 214 | #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 | |
| 215 | #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 | |
| 216 | #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 | |
| 217 | #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C | |
| 218 | #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 | |
| 219 | #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 | |
| 220 | #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 | |
| 221 | #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 | |
| 222 | #define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 | |
| 223 | #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 | |
| 224 | #define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 | |
| 225 | #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 | |
| 226 | #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 | |
| 227 | #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 | |
| 228 | #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 | |
| 229 | #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 | |
| 230 | #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 | |
| 231 | #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 | |
| 232 | #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 | |
| 233 | #define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 | |
| 234 | #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC | |
| 235 | #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 | |
| 236 | #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 | |
| 237 | #define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 | |
| 238 | #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC | |
| 239 | #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 | |
| 240 | #define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 | |
| 241 | #define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 | |
| 242 | #define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC | |
| 243 | #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 | |
| 244 | #define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC | |
| 245 | #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 | |
| 246 | #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 | |
| 247 | #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208 | |
| 248 | #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 | |
| 249 | #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 | |
| 250 | #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 | |
| 251 | #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C | |
| 252 | #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 | |
| 253 | #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 | |
| 254 | #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 | |
| 255 | #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C | |
| 256 | #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 | |
| 257 | #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 | |
| 258 | #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 | |
| 259 | #define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 | |
| 260 | #define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 | |
| 261 | #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 | |
| 262 | #define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 | |
| 263 | #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 | |
| 264 | #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 | |
| 265 | #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 | |
| 266 | #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 | |
| 267 | #define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 | |
| 268 | #define EXYNOS5_ISP_SYS_PWR_REG 0x1404 | |
| 269 | #define EXYNOS5_MFC_SYS_PWR_REG 0x1408 | |
| 270 | #define EXYNOS5_G3D_SYS_PWR_REG 0x140C | |
| 271 | #define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 | |
| 272 | #define EXYNOS5_MAU_SYS_PWR_REG 0x1418 | |
| 273 | #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 | |
| 274 | #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 | |
| 275 | #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 | |
| 276 | #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C | |
| 277 | #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 | |
| 278 | #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 | |
| 279 | #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 | |
| 280 | #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 | |
| 281 | #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 | |
| 282 | #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC | |
| 283 | #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 | |
| 284 | #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 | |
| 285 | #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 | |
| 286 | #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 | |
| 287 | #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 | |
| 288 | #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C | |
| 289 | #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 | |
| 290 | #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 | |
| 291 | ||
| 292 | #define EXYNOS5_ARM_CORE0_OPTION 0x2008 | |
| 293 | #define EXYNOS5_ARM_CORE1_OPTION 0x2088 | |
| 294 | #define EXYNOS5_FSYS_ARM_OPTION 0x2208 | |
| 295 | #define EXYNOS5_ISP_ARM_OPTION 0x2288 | |
| 296 | #define EXYNOS5_ARM_COMMON_OPTION 0x2408 | |
| 297 | #define EXYNOS5_ARM_L2_OPTION 0x2608 | |
| 298 | #define EXYNOS5_TOP_PWR_OPTION 0x2C48 | |
| 299 | #define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 | |
| 300 | #define EXYNOS5_JPEG_MEM_OPTION 0x2F48 | |
| 301 | #define EXYNOS5_GSCL_OPTION 0x4008 | |
| 302 | #define EXYNOS5_ISP_OPTION 0x4028 | |
| 303 | #define EXYNOS5_MFC_OPTION 0x4048 | |
| 304 | #define EXYNOS5_G3D_OPTION 0x4068 | |
| 305 | #define EXYNOS5_DISP1_OPTION 0x40A8 | |
| 306 | #define EXYNOS5_MAU_OPTION 0x40C8 | |
| 7d44d2ba JL |
307 | |
| 308 | #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) | |
| 309 | #define EXYNOS5_USE_SC_COUNTER (1 << 0) | |
| 310 | ||
| 7d44d2ba JL |
311 | #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) |
| 312 | ||
| 313 | #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) | |
| 314 | #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) | |
| 315 | ||
| 316 | #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) | |
| 317 | ||
| ccf55117 AK |
318 | #define EXYNOS5420_SWRESET_KFC_SEL 0x3 |
| 319 | ||
| 6ec4f8d0 CK |
320 | #include <asm/cputype.h> |
| 321 | #define MAX_CPUS_IN_CLUSTER 4 | |
| 322 | ||
| 323 | static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) | |
| 324 | { | |
| 325 | return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) | |
| 326 | + MPIDR_AFFINITY_LEVEL(mpidr, 0)); | |
| 327 | } | |
| 328 | ||
| d6d8b481 | 329 | #endif /* __ASM_ARCH_REGS_PMU_H */ |