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40360217 AK |
1 | /* linux/arch/arm/mach-exynos4/dev-ahci.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * EXYNOS4 - AHCI support | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/ahci_platform.h> | |
18 | ||
19 | #include <plat/cpu.h> | |
20 | ||
21 | #include <mach/irqs.h> | |
22 | #include <mach/map.h> | |
23 | #include <mach/regs-pmu.h> | |
24 | ||
25 | /* PHY Control Register */ | |
26 | #define SATA_CTRL0 0x0 | |
27 | /* PHY Link Control Register */ | |
28 | #define SATA_CTRL1 0x4 | |
29 | /* PHY Status Register */ | |
30 | #define SATA_PHY_STATUS 0x8 | |
31 | ||
32 | #define SATA_CTRL0_RX_DATA_VALID(x) (x << 27) | |
33 | #define SATA_CTRL0_SPEED_MODE (1 << 26) | |
34 | #define SATA_CTRL0_M_PHY_CAL (1 << 19) | |
35 | #define SATA_CTRL0_PHY_CMU_RST_N (1 << 10) | |
36 | #define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9) | |
37 | #define SATA_CTRL0_PHY_POR_N (1 << 8) | |
38 | ||
39 | #define SATA_CTRL1_RST_PMALIVE_N (1 << 8) | |
40 | #define SATA_CTRL1_RST_RXOOB_N (1 << 7) | |
41 | #define SATA_CTRL1_RST_RX_N (1 << 6) | |
42 | #define SATA_CTRL1_RST_TX_N (1 << 5) | |
43 | ||
44 | #define SATA_PHY_STATUS_CMU_OK (1 << 18) | |
45 | #define SATA_PHY_STATUS_LANE_OK (1 << 16) | |
46 | ||
47 | #define LANE0 0x200 | |
48 | #define COM_LANE 0xA00 | |
49 | ||
50 | #define HOST_PORTS_IMPL 0xC | |
51 | #define SCLK_SATA_FREQ (67 * MHZ) | |
52 | ||
53 | static void __iomem *phy_base, *phy_ctrl; | |
54 | ||
55 | struct phy_reg { | |
56 | u8 reg; | |
57 | u8 val; | |
58 | }; | |
59 | ||
60 | /* SATA PHY setup */ | |
61 | static const struct phy_reg exynos4_sataphy_cmu[] = { | |
62 | { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 }, | |
63 | { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 }, | |
64 | { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 }, | |
65 | { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 }, | |
66 | { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 }, | |
67 | { 0x6b, 0xc8 }, { 0x6c, 0x06 }, | |
68 | }; | |
69 | ||
70 | static const struct phy_reg exynos4_sataphy_lane[] = { | |
71 | { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 }, | |
72 | { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 }, | |
73 | { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e }, | |
74 | { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 }, | |
75 | { 0x51, 0x0f }, | |
76 | }; | |
77 | ||
78 | static const struct phy_reg exynos4_sataphy_comlane[] = { | |
79 | { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d }, | |
80 | { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 }, | |
81 | { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 }, | |
82 | { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 }, | |
83 | { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 }, | |
84 | { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 }, | |
85 | { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 }, | |
86 | { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d }, | |
87 | { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 }, | |
88 | { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 }, | |
89 | { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 }, | |
90 | { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff }, | |
91 | { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 }, | |
92 | { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 }, | |
93 | }; | |
94 | ||
95 | static int wait_for_phy_ready(void __iomem *reg, unsigned long bit) | |
96 | { | |
97 | unsigned long timeout; | |
98 | ||
99 | /* wait for maximum of 3 sec */ | |
100 | timeout = jiffies + msecs_to_jiffies(3000); | |
101 | while (!(__raw_readl(reg) & bit)) { | |
102 | if (time_after(jiffies, timeout)) | |
103 | return -1; | |
104 | cpu_relax(); | |
105 | } | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static int ahci_phy_init(void __iomem *mmio) | |
110 | { | |
111 | int i, ctrl0; | |
112 | ||
113 | for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++) | |
114 | __raw_writeb(exynos4_sataphy_cmu[i].val, | |
115 | phy_base + (exynos4_sataphy_cmu[i].reg * 4)); | |
116 | ||
117 | for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++) | |
118 | __raw_writeb(exynos4_sataphy_lane[i].val, | |
119 | phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4); | |
120 | ||
121 | for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++) | |
122 | __raw_writeb(exynos4_sataphy_comlane[i].val, | |
123 | phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4); | |
124 | ||
125 | __raw_writeb(0x07, phy_base); | |
126 | ||
127 | ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); | |
128 | ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N; | |
129 | __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); | |
130 | ||
131 | if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, | |
132 | SATA_PHY_STATUS_CMU_OK) < 0) { | |
133 | printk(KERN_ERR "PHY CMU not ready\n"); | |
134 | return -EBUSY; | |
135 | } | |
136 | ||
137 | __raw_writeb(0x03, phy_base + (COM_LANE * 4)); | |
138 | ||
139 | ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); | |
140 | ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N; | |
141 | __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); | |
142 | ||
143 | if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS, | |
144 | SATA_PHY_STATUS_LANE_OK) < 0) { | |
145 | printk(KERN_ERR "PHY LANE not ready\n"); | |
146 | return -EBUSY; | |
147 | } | |
148 | ||
149 | ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0); | |
150 | ctrl0 |= SATA_CTRL0_M_PHY_CAL; | |
151 | __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0); | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | static int exynos4_ahci_init(struct device *dev, void __iomem *mmio) | |
157 | { | |
158 | struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata; | |
159 | int val, ret; | |
160 | ||
161 | phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K); | |
162 | if (!phy_base) { | |
163 | dev_err(dev, "failed to allocate memory for SATA PHY\n"); | |
164 | return -ENOMEM; | |
165 | } | |
166 | ||
167 | phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16); | |
168 | if (!phy_ctrl) { | |
169 | dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n"); | |
170 | ret = -ENOMEM; | |
171 | goto err1; | |
172 | } | |
173 | ||
174 | clk_sata = clk_get(dev, "sata"); | |
175 | if (IS_ERR(clk_sata)) { | |
176 | dev_err(dev, "failed to get sata clock\n"); | |
177 | ret = PTR_ERR(clk_sata); | |
178 | clk_sata = NULL; | |
179 | goto err2; | |
180 | ||
181 | } | |
182 | clk_enable(clk_sata); | |
183 | ||
184 | clk_sataphy = clk_get(dev, "sataphy"); | |
185 | if (IS_ERR(clk_sataphy)) { | |
186 | dev_err(dev, "failed to get sataphy clock\n"); | |
187 | ret = PTR_ERR(clk_sataphy); | |
188 | clk_sataphy = NULL; | |
189 | goto err3; | |
190 | } | |
191 | clk_enable(clk_sataphy); | |
192 | ||
193 | clk_sclk_sata = clk_get(dev, "sclk_sata"); | |
194 | if (IS_ERR(clk_sclk_sata)) { | |
195 | dev_err(dev, "failed to get sclk_sata\n"); | |
196 | ret = PTR_ERR(clk_sclk_sata); | |
197 | clk_sclk_sata = NULL; | |
198 | goto err4; | |
199 | } | |
200 | clk_enable(clk_sclk_sata); | |
201 | clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ); | |
202 | ||
203 | __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL); | |
204 | ||
205 | /* Enable PHY link control */ | |
206 | val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N | | |
207 | SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N; | |
208 | __raw_writel(val, phy_ctrl + SATA_CTRL1); | |
209 | ||
210 | /* Set communication speed as 3Gbps and enable PHY power */ | |
211 | val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE | | |
212 | SATA_CTRL0_PHY_POR_N; | |
213 | __raw_writel(val, phy_ctrl + SATA_CTRL0); | |
214 | ||
215 | /* Port0 is available */ | |
216 | __raw_writel(0x1, mmio + HOST_PORTS_IMPL); | |
217 | ||
218 | return ahci_phy_init(mmio); | |
219 | ||
220 | err4: | |
221 | clk_disable(clk_sataphy); | |
222 | clk_put(clk_sataphy); | |
223 | err3: | |
224 | clk_disable(clk_sata); | |
225 | clk_put(clk_sata); | |
226 | err2: | |
227 | iounmap(phy_ctrl); | |
228 | err1: | |
229 | iounmap(phy_base); | |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
234 | static struct ahci_platform_data exynos4_ahci_pdata = { | |
235 | .init = exynos4_ahci_init, | |
236 | }; | |
237 | ||
238 | static struct resource exynos4_ahci_resource[] = { | |
239 | [0] = { | |
240 | .start = EXYNOS4_PA_SATA, | |
241 | .end = EXYNOS4_PA_SATA + SZ_64K - 1, | |
242 | .flags = IORESOURCE_MEM, | |
243 | }, | |
244 | [1] = { | |
245 | .start = IRQ_SATA, | |
246 | .end = IRQ_SATA, | |
247 | .flags = IORESOURCE_IRQ, | |
248 | }, | |
249 | }; | |
250 | ||
251 | static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32); | |
252 | ||
253 | struct platform_device exynos4_device_ahci = { | |
254 | .name = "ahci", | |
255 | .id = -1, | |
256 | .resource = exynos4_ahci_resource, | |
257 | .num_resources = ARRAY_SIZE(exynos4_ahci_resource), | |
258 | .dev = { | |
259 | .platform_data = &exynos4_ahci_pdata, | |
260 | .dma_mask = &exynos4_ahci_dmamask, | |
261 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
262 | }, | |
263 | }; |