Commit | Line | Data |
---|---|---|
c81a24ff | 1 | /* linux/arch/arm/mach-exynos4/irq-eint.c |
d8bb31e6 | 2 | * |
c81a24ff | 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
d8bb31e6 JH |
4 | * http://www.samsung.com |
5 | * | |
c81a24ff | 6 | * EXYNOS4 - IRQ EINT support |
d8bb31e6 JH |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/irq.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/sysdev.h> | |
18 | #include <linux/gpio.h> | |
19 | ||
20 | #include <plat/pm.h> | |
21 | #include <plat/cpu.h> | |
22 | #include <plat/gpio-cfg.h> | |
23 | ||
24 | #include <mach/regs-gpio.h> | |
25 | ||
26 | static DEFINE_SPINLOCK(eint_lock); | |
27 | ||
28 | static unsigned int eint0_15_data[16]; | |
29 | ||
c81a24ff | 30 | static unsigned int exynos4_get_irq_nr(unsigned int number) |
d8bb31e6 JH |
31 | { |
32 | u32 ret = 0; | |
33 | ||
34 | switch (number) { | |
35 | case 0 ... 3: | |
36 | ret = (number + IRQ_EINT0); | |
37 | break; | |
38 | case 4 ... 7: | |
39 | ret = (number + (IRQ_EINT4 - 4)); | |
40 | break; | |
41 | case 8 ... 15: | |
42 | ret = (number + (IRQ_EINT8 - 8)); | |
43 | break; | |
44 | default: | |
45 | printk(KERN_ERR "number available : %d\n", number); | |
46 | } | |
47 | ||
48 | return ret; | |
49 | } | |
50 | ||
c81a24ff | 51 | static inline void exynos4_irq_eint_mask(struct irq_data *data) |
d8bb31e6 JH |
52 | { |
53 | u32 mask; | |
54 | ||
55 | spin_lock(&eint_lock); | |
bb0b2374 LB |
56 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
57 | mask |= eint_irq_to_bit(data->irq); | |
58 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); | |
d8bb31e6 JH |
59 | spin_unlock(&eint_lock); |
60 | } | |
61 | ||
c81a24ff | 62 | static void exynos4_irq_eint_unmask(struct irq_data *data) |
d8bb31e6 JH |
63 | { |
64 | u32 mask; | |
65 | ||
66 | spin_lock(&eint_lock); | |
bb0b2374 LB |
67 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); |
68 | mask &= ~(eint_irq_to_bit(data->irq)); | |
69 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); | |
d8bb31e6 JH |
70 | spin_unlock(&eint_lock); |
71 | } | |
72 | ||
c81a24ff | 73 | static inline void exynos4_irq_eint_ack(struct irq_data *data) |
d8bb31e6 | 74 | { |
bb0b2374 LB |
75 | __raw_writel(eint_irq_to_bit(data->irq), |
76 | S5P_EINT_PEND(EINT_REG_NR(data->irq))); | |
d8bb31e6 JH |
77 | } |
78 | ||
c81a24ff | 79 | static void exynos4_irq_eint_maskack(struct irq_data *data) |
d8bb31e6 | 80 | { |
c81a24ff KK |
81 | exynos4_irq_eint_mask(data); |
82 | exynos4_irq_eint_ack(data); | |
d8bb31e6 JH |
83 | } |
84 | ||
c81a24ff | 85 | static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type) |
d8bb31e6 | 86 | { |
bb0b2374 | 87 | int offs = EINT_OFFSET(data->irq); |
d8bb31e6 JH |
88 | int shift; |
89 | u32 ctrl, mask; | |
90 | u32 newvalue = 0; | |
91 | ||
92 | switch (type) { | |
93 | case IRQ_TYPE_EDGE_RISING: | |
94 | newvalue = S5P_IRQ_TYPE_EDGE_RISING; | |
95 | break; | |
96 | ||
97 | case IRQ_TYPE_EDGE_FALLING: | |
98 | newvalue = S5P_IRQ_TYPE_EDGE_FALLING; | |
99 | break; | |
100 | ||
101 | case IRQ_TYPE_EDGE_BOTH: | |
102 | newvalue = S5P_IRQ_TYPE_EDGE_BOTH; | |
103 | break; | |
104 | ||
105 | case IRQ_TYPE_LEVEL_LOW: | |
106 | newvalue = S5P_IRQ_TYPE_LEVEL_LOW; | |
107 | break; | |
108 | ||
109 | case IRQ_TYPE_LEVEL_HIGH: | |
110 | newvalue = S5P_IRQ_TYPE_LEVEL_HIGH; | |
111 | break; | |
112 | ||
113 | default: | |
114 | printk(KERN_ERR "No such irq type %d", type); | |
115 | return -EINVAL; | |
116 | } | |
117 | ||
118 | shift = (offs & 0x7) * 4; | |
119 | mask = 0x7 << shift; | |
120 | ||
121 | spin_lock(&eint_lock); | |
bb0b2374 | 122 | ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq))); |
d8bb31e6 JH |
123 | ctrl &= ~mask; |
124 | ctrl |= newvalue << shift; | |
bb0b2374 | 125 | __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq))); |
d8bb31e6 JH |
126 | spin_unlock(&eint_lock); |
127 | ||
128 | switch (offs) { | |
129 | case 0 ... 7: | |
130 | s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); | |
131 | break; | |
132 | case 8 ... 15: | |
133 | s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); | |
134 | break; | |
135 | case 16 ... 23: | |
136 | s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); | |
137 | break; | |
138 | case 24 ... 31: | |
139 | s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); | |
140 | break; | |
141 | default: | |
142 | printk(KERN_ERR "No such irq number %d", offs); | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
c81a24ff KK |
148 | static struct irq_chip exynos4_irq_eint = { |
149 | .name = "exynos4-eint", | |
150 | .irq_mask = exynos4_irq_eint_mask, | |
151 | .irq_unmask = exynos4_irq_eint_unmask, | |
152 | .irq_mask_ack = exynos4_irq_eint_maskack, | |
153 | .irq_ack = exynos4_irq_eint_ack, | |
154 | .irq_set_type = exynos4_irq_eint_set_type, | |
d8bb31e6 | 155 | #ifdef CONFIG_PM |
f5aeffb7 | 156 | .irq_set_wake = s3c_irqext_wake, |
d8bb31e6 JH |
157 | #endif |
158 | }; | |
159 | ||
c81a24ff | 160 | /* exynos4_irq_demux_eint |
d8bb31e6 JH |
161 | * |
162 | * This function demuxes the IRQ from from EINTs 16 to 31. | |
163 | * It is designed to be inlined into the specific handler | |
164 | * s5p_irq_demux_eintX_Y. | |
165 | * | |
166 | * Each EINT pend/mask registers handle eight of them. | |
167 | */ | |
c81a24ff | 168 | static inline void exynos4_irq_demux_eint(unsigned int start) |
d8bb31e6 JH |
169 | { |
170 | unsigned int irq; | |
171 | ||
172 | u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); | |
173 | u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); | |
174 | ||
175 | status &= ~mask; | |
176 | status &= 0xff; | |
177 | ||
178 | while (status) { | |
179 | irq = fls(status) - 1; | |
180 | generic_handle_irq(irq + start); | |
181 | status &= ~(1 << irq); | |
182 | } | |
183 | } | |
184 | ||
c81a24ff | 185 | static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) |
d8bb31e6 | 186 | { |
c81a24ff KK |
187 | exynos4_irq_demux_eint(IRQ_EINT(16)); |
188 | exynos4_irq_demux_eint(IRQ_EINT(24)); | |
d8bb31e6 JH |
189 | } |
190 | ||
c81a24ff | 191 | static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) |
d8bb31e6 | 192 | { |
6845664a TG |
193 | u32 *irq_data = irq_get_handler_data(irq); |
194 | struct irq_chip *chip = irq_get_chip(irq); | |
d8bb31e6 | 195 | |
bb0b2374 | 196 | chip->irq_mask(&desc->irq_data); |
d8bb31e6 | 197 | |
bb0b2374 LB |
198 | if (chip->irq_ack) |
199 | chip->irq_ack(&desc->irq_data); | |
d8bb31e6 JH |
200 | |
201 | generic_handle_irq(*irq_data); | |
202 | ||
bb0b2374 | 203 | chip->irq_unmask(&desc->irq_data); |
d8bb31e6 JH |
204 | } |
205 | ||
c81a24ff | 206 | int __init exynos4_init_irq_eint(void) |
d8bb31e6 JH |
207 | { |
208 | int irq; | |
209 | ||
210 | for (irq = 0 ; irq <= 31 ; irq++) { | |
f38c02f3 TG |
211 | irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint, |
212 | handle_level_irq); | |
d8bb31e6 JH |
213 | set_irq_flags(IRQ_EINT(irq), IRQF_VALID); |
214 | } | |
215 | ||
6845664a | 216 | irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); |
d8bb31e6 JH |
217 | |
218 | for (irq = 0 ; irq <= 15 ; irq++) { | |
219 | eint0_15_data[irq] = IRQ_EINT(irq); | |
220 | ||
6845664a TG |
221 | irq_set_handler_data(exynos4_get_irq_nr(irq), |
222 | &eint0_15_data[irq]); | |
223 | irq_set_chained_handler(exynos4_get_irq_nr(irq), | |
c81a24ff | 224 | exynos4_irq_eint0_15); |
d8bb31e6 JH |
225 | } |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
c81a24ff | 230 | arch_initcall(exynos4_init_irq_eint); |