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699efdd2 JK |
1 | /* linux/arch/arm/mach-exynos4/mach-origen.c |
2 | * | |
3 | * Copyright (c) 2011 Insignal Co., Ltd. | |
4 | * http://www.insignal.co.kr/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/serial_core.h> | |
12 | #include <linux/gpio.h> | |
13 | #include <linux/mmc/host.h> | |
14 | #include <linux/platform_device.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/input.h> | |
9edff0f7 | 17 | #include <linux/pwm_backlight.h> |
c86cfdd0 | 18 | #include <linux/gpio_keys.h> |
6e01280f IS |
19 | #include <linux/i2c.h> |
20 | #include <linux/regulator/machine.h> | |
21 | #include <linux/mfd/max8997.h> | |
9421a76d | 22 | #include <linux/lcd.h> |
699efdd2 JK |
23 | |
24 | #include <asm/mach/arch.h> | |
25 | #include <asm/mach-types.h> | |
26 | ||
9421a76d TB |
27 | #include <video/platform_lcd.h> |
28 | ||
699efdd2 | 29 | #include <plat/regs-serial.h> |
9421a76d | 30 | #include <plat/regs-fb-v4.h> |
699efdd2 JK |
31 | #include <plat/exynos4.h> |
32 | #include <plat/cpu.h> | |
33 | #include <plat/devs.h> | |
34 | #include <plat/sdhci.h> | |
35 | #include <plat/iic.h> | |
24f9e1f3 SK |
36 | #include <plat/ehci.h> |
37 | #include <plat/clock.h> | |
9edff0f7 GM |
38 | #include <plat/gpio-cfg.h> |
39 | #include <plat/backlight.h> | |
9421a76d TB |
40 | #include <plat/pd.h> |
41 | #include <plat/fb.h> | |
699efdd2 JK |
42 | |
43 | #include <mach/map.h> | |
44 | ||
45 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | |
46 | #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | |
47 | S3C2410_UCON_RXILEVEL | \ | |
48 | S3C2410_UCON_TXIRQMODE | \ | |
49 | S3C2410_UCON_RXIRQMODE | \ | |
50 | S3C2410_UCON_RXFIFO_TOI | \ | |
51 | S3C2443_UCON_RXERR_IRQEN) | |
52 | ||
53 | #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 | |
54 | ||
55 | #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | |
56 | S5PV210_UFCON_TXTRIG4 | \ | |
57 | S5PV210_UFCON_RXTRIG4) | |
58 | ||
59 | static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { | |
60 | [0] = { | |
61 | .hwport = 0, | |
62 | .flags = 0, | |
63 | .ucon = ORIGEN_UCON_DEFAULT, | |
64 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
65 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
66 | }, | |
67 | [1] = { | |
68 | .hwport = 1, | |
69 | .flags = 0, | |
70 | .ucon = ORIGEN_UCON_DEFAULT, | |
71 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
72 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
73 | }, | |
74 | [2] = { | |
75 | .hwport = 2, | |
76 | .flags = 0, | |
77 | .ucon = ORIGEN_UCON_DEFAULT, | |
78 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
79 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
80 | }, | |
81 | [3] = { | |
82 | .hwport = 3, | |
83 | .flags = 0, | |
84 | .ucon = ORIGEN_UCON_DEFAULT, | |
85 | .ulcon = ORIGEN_ULCON_DEFAULT, | |
86 | .ufcon = ORIGEN_UFCON_DEFAULT, | |
87 | }, | |
88 | }; | |
89 | ||
6e01280f IS |
90 | static struct regulator_consumer_supply __initdata ldo3_consumer[] = { |
91 | REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ | |
92 | }; | |
93 | static struct regulator_consumer_supply __initdata ldo6_consumer[] = { | |
94 | REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ | |
95 | }; | |
96 | static struct regulator_consumer_supply __initdata ldo7_consumer[] = { | |
97 | REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ | |
98 | }; | |
99 | static struct regulator_consumer_supply __initdata ldo8_consumer[] = { | |
100 | REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */ | |
101 | }; | |
102 | static struct regulator_consumer_supply __initdata ldo9_consumer[] = { | |
103 | REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ | |
104 | }; | |
105 | static struct regulator_consumer_supply __initdata ldo11_consumer[] = { | |
106 | REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */ | |
107 | }; | |
108 | static struct regulator_consumer_supply __initdata ldo14_consumer[] = { | |
109 | REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ | |
110 | }; | |
111 | static struct regulator_consumer_supply __initdata ldo17_consumer[] = { | |
112 | REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ | |
113 | }; | |
114 | static struct regulator_consumer_supply __initdata buck1_consumer[] = { | |
115 | REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ | |
116 | }; | |
117 | static struct regulator_consumer_supply __initdata buck2_consumer[] = { | |
118 | REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ | |
119 | }; | |
120 | static struct regulator_consumer_supply __initdata buck3_consumer[] = { | |
121 | REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ | |
122 | }; | |
123 | static struct regulator_consumer_supply __initdata buck7_consumer[] = { | |
124 | REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ | |
125 | }; | |
126 | ||
127 | static struct regulator_init_data __initdata max8997_ldo1_data = { | |
128 | .constraints = { | |
129 | .name = "VDD_ABB_3.3V", | |
130 | .min_uV = 3300000, | |
131 | .max_uV = 3300000, | |
132 | .apply_uV = 1, | |
133 | .state_mem = { | |
134 | .disabled = 1, | |
135 | }, | |
136 | }, | |
137 | }; | |
138 | ||
139 | static struct regulator_init_data __initdata max8997_ldo2_data = { | |
140 | .constraints = { | |
141 | .name = "VDD_ALIVE_1.1V", | |
142 | .min_uV = 1100000, | |
143 | .max_uV = 1100000, | |
144 | .apply_uV = 1, | |
145 | .always_on = 1, | |
146 | .state_mem = { | |
147 | .enabled = 1, | |
148 | }, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static struct regulator_init_data __initdata max8997_ldo3_data = { | |
153 | .constraints = { | |
154 | .name = "VMIPI_1.1V", | |
155 | .min_uV = 1100000, | |
156 | .max_uV = 1100000, | |
157 | .apply_uV = 1, | |
158 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
159 | .state_mem = { | |
160 | .disabled = 1, | |
161 | }, | |
162 | }, | |
163 | .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), | |
164 | .consumer_supplies = ldo3_consumer, | |
165 | }; | |
166 | ||
167 | static struct regulator_init_data __initdata max8997_ldo4_data = { | |
168 | .constraints = { | |
169 | .name = "VDD_RTC_1.8V", | |
170 | .min_uV = 1800000, | |
171 | .max_uV = 1800000, | |
172 | .apply_uV = 1, | |
173 | .always_on = 1, | |
174 | .state_mem = { | |
175 | .disabled = 1, | |
176 | }, | |
177 | }, | |
178 | }; | |
179 | ||
180 | static struct regulator_init_data __initdata max8997_ldo6_data = { | |
181 | .constraints = { | |
182 | .name = "VMIPI_1.8V", | |
183 | .min_uV = 1800000, | |
184 | .max_uV = 1800000, | |
185 | .apply_uV = 1, | |
186 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
187 | .state_mem = { | |
188 | .disabled = 1, | |
189 | }, | |
190 | }, | |
191 | .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer), | |
192 | .consumer_supplies = ldo6_consumer, | |
193 | }; | |
194 | ||
195 | static struct regulator_init_data __initdata max8997_ldo7_data = { | |
196 | .constraints = { | |
197 | .name = "VDD_AUD_1.8V", | |
198 | .min_uV = 1800000, | |
199 | .max_uV = 1800000, | |
200 | .apply_uV = 1, | |
201 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
202 | .state_mem = { | |
203 | .disabled = 1, | |
204 | }, | |
205 | }, | |
206 | .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), | |
207 | .consumer_supplies = ldo7_consumer, | |
208 | }; | |
209 | ||
210 | static struct regulator_init_data __initdata max8997_ldo8_data = { | |
211 | .constraints = { | |
212 | .name = "VADC_3.3V", | |
213 | .min_uV = 3300000, | |
214 | .max_uV = 3300000, | |
215 | .apply_uV = 1, | |
216 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
217 | .state_mem = { | |
218 | .disabled = 1, | |
219 | }, | |
220 | }, | |
221 | .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), | |
222 | .consumer_supplies = ldo8_consumer, | |
223 | }; | |
224 | ||
225 | static struct regulator_init_data __initdata max8997_ldo9_data = { | |
226 | .constraints = { | |
227 | .name = "DVDD_SWB_2.8V", | |
228 | .min_uV = 2800000, | |
229 | .max_uV = 2800000, | |
230 | .apply_uV = 1, | |
231 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
232 | .state_mem = { | |
233 | .disabled = 1, | |
234 | }, | |
235 | }, | |
236 | .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer), | |
237 | .consumer_supplies = ldo9_consumer, | |
238 | }; | |
239 | ||
240 | static struct regulator_init_data __initdata max8997_ldo10_data = { | |
241 | .constraints = { | |
242 | .name = "VDD_PLL_1.1V", | |
243 | .min_uV = 1100000, | |
244 | .max_uV = 1100000, | |
245 | .apply_uV = 1, | |
246 | .always_on = 1, | |
247 | .state_mem = { | |
248 | .disabled = 1, | |
249 | }, | |
250 | }, | |
251 | }; | |
252 | ||
253 | static struct regulator_init_data __initdata max8997_ldo11_data = { | |
254 | .constraints = { | |
255 | .name = "VDD_AUD_3V", | |
256 | .min_uV = 3000000, | |
257 | .max_uV = 3000000, | |
258 | .apply_uV = 1, | |
259 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
260 | .state_mem = { | |
261 | .disabled = 1, | |
262 | }, | |
263 | }, | |
264 | .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), | |
265 | .consumer_supplies = ldo11_consumer, | |
266 | }; | |
267 | ||
268 | static struct regulator_init_data __initdata max8997_ldo14_data = { | |
269 | .constraints = { | |
270 | .name = "AVDD18_SWB_1.8V", | |
271 | .min_uV = 1800000, | |
272 | .max_uV = 1800000, | |
273 | .apply_uV = 1, | |
274 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
275 | .state_mem = { | |
276 | .disabled = 1, | |
277 | }, | |
278 | }, | |
279 | .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), | |
280 | .consumer_supplies = ldo14_consumer, | |
281 | }; | |
282 | ||
283 | static struct regulator_init_data __initdata max8997_ldo17_data = { | |
284 | .constraints = { | |
285 | .name = "VDD_SWB_3.3V", | |
286 | .min_uV = 3300000, | |
287 | .max_uV = 3300000, | |
288 | .apply_uV = 1, | |
289 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
290 | .state_mem = { | |
291 | .disabled = 1, | |
292 | }, | |
293 | }, | |
294 | .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), | |
295 | .consumer_supplies = ldo17_consumer, | |
296 | }; | |
297 | ||
298 | static struct regulator_init_data __initdata max8997_ldo21_data = { | |
299 | .constraints = { | |
300 | .name = "VDD_MIF_1.2V", | |
301 | .min_uV = 1200000, | |
302 | .max_uV = 1200000, | |
303 | .apply_uV = 1, | |
304 | .always_on = 1, | |
305 | .state_mem = { | |
306 | .disabled = 1, | |
307 | }, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static struct regulator_init_data __initdata max8997_buck1_data = { | |
312 | .constraints = { | |
313 | .name = "VDD_ARM_1.2V", | |
314 | .min_uV = 950000, | |
315 | .max_uV = 1350000, | |
316 | .always_on = 1, | |
317 | .boot_on = 1, | |
318 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
319 | .state_mem = { | |
320 | .disabled = 1, | |
321 | }, | |
322 | }, | |
323 | .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), | |
324 | .consumer_supplies = buck1_consumer, | |
325 | }; | |
326 | ||
327 | static struct regulator_init_data __initdata max8997_buck2_data = { | |
328 | .constraints = { | |
329 | .name = "VDD_INT_1.1V", | |
330 | .min_uV = 900000, | |
331 | .max_uV = 1100000, | |
332 | .always_on = 1, | |
333 | .boot_on = 1, | |
334 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
335 | .state_mem = { | |
336 | .disabled = 1, | |
337 | }, | |
338 | }, | |
339 | .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), | |
340 | .consumer_supplies = buck2_consumer, | |
341 | }; | |
342 | ||
343 | static struct regulator_init_data __initdata max8997_buck3_data = { | |
344 | .constraints = { | |
345 | .name = "VDD_G3D_1.1V", | |
346 | .min_uV = 900000, | |
347 | .max_uV = 1100000, | |
348 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
349 | REGULATOR_CHANGE_STATUS, | |
350 | .state_mem = { | |
351 | .disabled = 1, | |
352 | }, | |
353 | }, | |
354 | .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), | |
355 | .consumer_supplies = buck3_consumer, | |
356 | }; | |
357 | ||
358 | static struct regulator_init_data __initdata max8997_buck5_data = { | |
359 | .constraints = { | |
360 | .name = "VDDQ_M1M2_1.2V", | |
361 | .min_uV = 1200000, | |
362 | .max_uV = 1200000, | |
363 | .apply_uV = 1, | |
364 | .always_on = 1, | |
365 | .state_mem = { | |
366 | .disabled = 1, | |
367 | }, | |
368 | }, | |
369 | }; | |
370 | ||
371 | static struct regulator_init_data __initdata max8997_buck7_data = { | |
372 | .constraints = { | |
373 | .name = "VDD_LCD_3.3V", | |
374 | .min_uV = 3300000, | |
375 | .max_uV = 3300000, | |
376 | .boot_on = 1, | |
377 | .apply_uV = 1, | |
378 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
379 | .state_mem = { | |
380 | .disabled = 1 | |
381 | }, | |
382 | }, | |
383 | .num_consumer_supplies = ARRAY_SIZE(buck7_consumer), | |
384 | .consumer_supplies = buck7_consumer, | |
385 | }; | |
386 | ||
387 | static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { | |
388 | { MAX8997_LDO1, &max8997_ldo1_data }, | |
389 | { MAX8997_LDO2, &max8997_ldo2_data }, | |
390 | { MAX8997_LDO3, &max8997_ldo3_data }, | |
391 | { MAX8997_LDO4, &max8997_ldo4_data }, | |
392 | { MAX8997_LDO6, &max8997_ldo6_data }, | |
393 | { MAX8997_LDO7, &max8997_ldo7_data }, | |
394 | { MAX8997_LDO8, &max8997_ldo8_data }, | |
395 | { MAX8997_LDO9, &max8997_ldo9_data }, | |
396 | { MAX8997_LDO10, &max8997_ldo10_data }, | |
397 | { MAX8997_LDO11, &max8997_ldo11_data }, | |
398 | { MAX8997_LDO14, &max8997_ldo14_data }, | |
399 | { MAX8997_LDO17, &max8997_ldo17_data }, | |
400 | { MAX8997_LDO21, &max8997_ldo21_data }, | |
401 | { MAX8997_BUCK1, &max8997_buck1_data }, | |
402 | { MAX8997_BUCK2, &max8997_buck2_data }, | |
403 | { MAX8997_BUCK3, &max8997_buck3_data }, | |
404 | { MAX8997_BUCK5, &max8997_buck5_data }, | |
405 | { MAX8997_BUCK7, &max8997_buck7_data }, | |
406 | }; | |
407 | ||
408 | struct max8997_platform_data __initdata origen_max8997_pdata = { | |
409 | .num_regulators = ARRAY_SIZE(origen_max8997_regulators), | |
410 | .regulators = origen_max8997_regulators, | |
411 | ||
412 | .wakeup = true, | |
413 | .buck1_gpiodvs = false, | |
414 | .buck2_gpiodvs = false, | |
415 | .buck5_gpiodvs = false, | |
416 | .irq_base = IRQ_GPIO_END + 1, | |
417 | ||
418 | .ignore_gpiodvs_side_effect = true, | |
419 | .buck125_default_idx = 0x0, | |
420 | ||
421 | .buck125_gpios[0] = EXYNOS4_GPX0(0), | |
422 | .buck125_gpios[1] = EXYNOS4_GPX0(1), | |
423 | .buck125_gpios[2] = EXYNOS4_GPX0(2), | |
424 | ||
425 | .buck1_voltage[0] = 1350000, | |
426 | .buck1_voltage[1] = 1300000, | |
427 | .buck1_voltage[2] = 1250000, | |
428 | .buck1_voltage[3] = 1200000, | |
429 | .buck1_voltage[4] = 1150000, | |
430 | .buck1_voltage[5] = 1100000, | |
431 | .buck1_voltage[6] = 1000000, | |
432 | .buck1_voltage[7] = 950000, | |
433 | ||
434 | .buck2_voltage[0] = 1100000, | |
435 | .buck2_voltage[1] = 1100000, | |
436 | .buck2_voltage[2] = 1100000, | |
437 | .buck2_voltage[3] = 1100000, | |
438 | .buck2_voltage[4] = 1000000, | |
439 | .buck2_voltage[5] = 1000000, | |
440 | .buck2_voltage[6] = 1000000, | |
441 | .buck2_voltage[7] = 1000000, | |
442 | ||
443 | .buck5_voltage[0] = 1200000, | |
444 | .buck5_voltage[1] = 1200000, | |
445 | .buck5_voltage[2] = 1200000, | |
446 | .buck5_voltage[3] = 1200000, | |
447 | .buck5_voltage[4] = 1200000, | |
448 | .buck5_voltage[5] = 1200000, | |
449 | .buck5_voltage[6] = 1200000, | |
450 | .buck5_voltage[7] = 1200000, | |
451 | }; | |
452 | ||
453 | /* I2C0 */ | |
454 | static struct i2c_board_info i2c0_devs[] __initdata = { | |
455 | { | |
456 | I2C_BOARD_INFO("max8997", (0xCC >> 1)), | |
457 | .platform_data = &origen_max8997_pdata, | |
458 | .irq = IRQ_EINT(4), | |
459 | }, | |
460 | }; | |
461 | ||
cf1dad9d TB |
462 | static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { |
463 | .cd_type = S3C_SDHCI_CD_INTERNAL, | |
464 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
465 | }; | |
466 | ||
699efdd2 | 467 | static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { |
92e41efd | 468 | .cd_type = S3C_SDHCI_CD_INTERNAL, |
699efdd2 JK |
469 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
470 | }; | |
471 | ||
24f9e1f3 SK |
472 | /* USB EHCI */ |
473 | static struct s5p_ehci_platdata origen_ehci_pdata; | |
474 | ||
475 | static void __init origen_ehci_init(void) | |
476 | { | |
477 | struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; | |
478 | ||
479 | s5p_ehci_set_platdata(pdata); | |
480 | } | |
481 | ||
c86cfdd0 SK |
482 | static struct gpio_keys_button origen_gpio_keys_table[] = { |
483 | { | |
484 | .code = KEY_MENU, | |
485 | .gpio = EXYNOS4_GPX1(5), | |
486 | .desc = "gpio-keys: KEY_MENU", | |
487 | .type = EV_KEY, | |
488 | .active_low = 1, | |
489 | .wakeup = 1, | |
490 | .debounce_interval = 1, | |
491 | }, { | |
492 | .code = KEY_HOME, | |
493 | .gpio = EXYNOS4_GPX1(6), | |
494 | .desc = "gpio-keys: KEY_HOME", | |
495 | .type = EV_KEY, | |
496 | .active_low = 1, | |
497 | .wakeup = 1, | |
498 | .debounce_interval = 1, | |
499 | }, { | |
500 | .code = KEY_BACK, | |
501 | .gpio = EXYNOS4_GPX1(7), | |
502 | .desc = "gpio-keys: KEY_BACK", | |
503 | .type = EV_KEY, | |
504 | .active_low = 1, | |
505 | .wakeup = 1, | |
506 | .debounce_interval = 1, | |
507 | }, { | |
508 | .code = KEY_UP, | |
509 | .gpio = EXYNOS4_GPX2(0), | |
510 | .desc = "gpio-keys: KEY_UP", | |
511 | .type = EV_KEY, | |
512 | .active_low = 1, | |
513 | .wakeup = 1, | |
514 | .debounce_interval = 1, | |
515 | }, { | |
516 | .code = KEY_DOWN, | |
517 | .gpio = EXYNOS4_GPX2(1), | |
518 | .desc = "gpio-keys: KEY_DOWN", | |
519 | .type = EV_KEY, | |
520 | .active_low = 1, | |
521 | .wakeup = 1, | |
522 | .debounce_interval = 1, | |
523 | }, | |
524 | }; | |
525 | ||
526 | static struct gpio_keys_platform_data origen_gpio_keys_data = { | |
527 | .buttons = origen_gpio_keys_table, | |
528 | .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), | |
529 | }; | |
530 | ||
531 | static struct platform_device origen_device_gpiokeys = { | |
532 | .name = "gpio-keys", | |
533 | .dev = { | |
534 | .platform_data = &origen_gpio_keys_data, | |
535 | }, | |
536 | }; | |
537 | ||
9421a76d TB |
538 | static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) |
539 | { | |
540 | int ret; | |
541 | ||
542 | if (power) | |
543 | ret = gpio_request_one(EXYNOS4_GPE3(4), | |
544 | GPIOF_OUT_INIT_HIGH, "GPE3_4"); | |
545 | else | |
546 | ret = gpio_request_one(EXYNOS4_GPE3(4), | |
547 | GPIOF_OUT_INIT_LOW, "GPE3_4"); | |
548 | ||
549 | gpio_free(EXYNOS4_GPE3(4)); | |
550 | ||
551 | if (ret) | |
552 | pr_err("failed to request gpio for LCD power: %d\n", ret); | |
553 | } | |
554 | ||
555 | static struct plat_lcd_data origen_lcd_hv070wsa_data = { | |
556 | .set_power = lcd_hv070wsa_set_power, | |
557 | }; | |
558 | ||
559 | static struct platform_device origen_lcd_hv070wsa = { | |
560 | .name = "platform-lcd", | |
561 | .dev.parent = &s5p_device_fimd0.dev, | |
562 | .dev.platform_data = &origen_lcd_hv070wsa_data, | |
563 | }; | |
564 | ||
565 | static struct s3c_fb_pd_win origen_fb_win0 = { | |
566 | .win_mode = { | |
567 | .left_margin = 64, | |
568 | .right_margin = 16, | |
569 | .upper_margin = 64, | |
570 | .lower_margin = 16, | |
571 | .hsync_len = 48, | |
572 | .vsync_len = 3, | |
573 | .xres = 1024, | |
574 | .yres = 600, | |
575 | }, | |
576 | .max_bpp = 32, | |
577 | .default_bpp = 24, | |
578 | }; | |
579 | ||
580 | static struct s3c_fb_platdata origen_lcd_pdata __initdata = { | |
581 | .win[0] = &origen_fb_win0, | |
582 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | |
583 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | |
584 | .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, | |
585 | }; | |
586 | ||
699efdd2 JK |
587 | static struct platform_device *origen_devices[] __initdata = { |
588 | &s3c_device_hsmmc2, | |
cf1dad9d | 589 | &s3c_device_hsmmc0, |
9421a76d | 590 | &s3c_device_i2c0, |
699efdd2 JK |
591 | &s3c_device_rtc, |
592 | &s3c_device_wdt, | |
24f9e1f3 | 593 | &s5p_device_ehci, |
6f8eb324 SK |
594 | &s5p_device_fimc0, |
595 | &s5p_device_fimc1, | |
596 | &s5p_device_fimc2, | |
597 | &s5p_device_fimc3, | |
9421a76d | 598 | &s5p_device_fimd0, |
6ca3f8bd SK |
599 | &s5p_device_hdmi, |
600 | &s5p_device_i2c_hdmiphy, | |
601 | &s5p_device_mixer, | |
9421a76d | 602 | &exynos4_device_pd[PD_LCD0], |
3c766699 | 603 | &exynos4_device_pd[PD_TV], |
c86cfdd0 | 604 | &origen_device_gpiokeys, |
9421a76d | 605 | &origen_lcd_hv070wsa, |
699efdd2 JK |
606 | }; |
607 | ||
9edff0f7 GM |
608 | /* LCD Backlight data */ |
609 | static struct samsung_bl_gpio_info origen_bl_gpio_info = { | |
6e01280f IS |
610 | .no = EXYNOS4_GPD0(0), |
611 | .func = S3C_GPIO_SFN(2), | |
9edff0f7 GM |
612 | }; |
613 | ||
614 | static struct platform_pwm_backlight_data origen_bl_data = { | |
6e01280f IS |
615 | .pwm_id = 0, |
616 | .pwm_period_ns = 1000, | |
9edff0f7 GM |
617 | }; |
618 | ||
3c766699 SK |
619 | static void s5p_tv_setup(void) |
620 | { | |
621 | /* Direct HPD to HDMI chip */ | |
622 | gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); | |
623 | s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); | |
624 | s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); | |
625 | } | |
626 | ||
699efdd2 JK |
627 | static void __init origen_map_io(void) |
628 | { | |
629 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
630 | s3c24xx_init_clocks(24000000); | |
631 | s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); | |
632 | } | |
633 | ||
6e01280f IS |
634 | static void __init origen_power_init(void) |
635 | { | |
636 | gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ"); | |
637 | s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf)); | |
638 | s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); | |
639 | } | |
640 | ||
699efdd2 JK |
641 | static void __init origen_machine_init(void) |
642 | { | |
6e01280f IS |
643 | origen_power_init(); |
644 | ||
645 | s3c_i2c0_set_platdata(NULL); | |
646 | i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); | |
647 | ||
cf1dad9d TB |
648 | /* |
649 | * Since sdhci instance 2 can contain a bootable media, | |
650 | * sdhci instance 0 is registered after instance 2. | |
651 | */ | |
699efdd2 | 652 | s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); |
cf1dad9d | 653 | s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); |
24f9e1f3 SK |
654 | |
655 | origen_ehci_init(); | |
656 | clk_xusbxti.rate = 24000000; | |
657 | ||
3c766699 | 658 | s5p_tv_setup(); |
6ca3f8bd SK |
659 | s5p_i2c_hdmiphy_set_platdata(NULL); |
660 | ||
9421a76d TB |
661 | s5p_fimd0_set_platdata(&origen_lcd_pdata); |
662 | ||
699efdd2 | 663 | platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); |
9421a76d | 664 | s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; |
9edff0f7 | 665 | |
3c766699 SK |
666 | s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; |
667 | s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; | |
668 | ||
9edff0f7 | 669 | samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); |
699efdd2 JK |
670 | } |
671 | ||
672 | MACHINE_START(ORIGEN, "ORIGEN") | |
673 | /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ | |
1abd328e | 674 | .atag_offset = 0x100, |
699efdd2 JK |
675 | .init_irq = exynos4_init_irq, |
676 | .map_io = origen_map_io, | |
677 | .init_machine = origen_machine_init, | |
678 | .timer = &exynos4_timer, | |
679 | MACHINE_END |