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d11135ca | 1 | /* linux/arch/arm/mach-exynos4/mach-universal_c210.c |
516607d6 KP |
2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
34d79315 | 10 | #include <linux/platform_device.h> |
516607d6 | 11 | #include <linux/serial_core.h> |
34d79315 | 12 | #include <linux/input.h> |
3b7998f5 | 13 | #include <linux/i2c.h> |
34d79315 KP |
14 | #include <linux/gpio_keys.h> |
15 | #include <linux/gpio.h> | |
4d838ec0 | 16 | #include <linux/mfd/max8998.h> |
a8928ce7 KP |
17 | #include <linux/regulator/machine.h> |
18 | #include <linux/regulator/fixed.h> | |
4d838ec0 | 19 | #include <linux/regulator/max8952.h> |
a8928ce7 | 20 | #include <linux/mmc/host.h> |
b908af44 MS |
21 | #include <linux/i2c-gpio.h> |
22 | #include <linux/i2c/mcs.h> | |
0b398b69 | 23 | #include <linux/i2c/atmel_mxt_ts.h> |
516607d6 KP |
24 | |
25 | #include <asm/mach/arch.h> | |
26 | #include <asm/mach-types.h> | |
516607d6 KP |
27 | |
28 | #include <plat/regs-serial.h> | |
d11135ca | 29 | #include <plat/exynos4.h> |
516607d6 | 30 | #include <plat/cpu.h> |
acf5eda9 | 31 | #include <plat/devs.h> |
4d838ec0 | 32 | #include <plat/iic.h> |
0b398b69 | 33 | #include <plat/gpio-cfg.h> |
a8928ce7 | 34 | #include <plat/sdhci.h> |
516607d6 KP |
35 | |
36 | #include <mach/map.h> | |
37 | ||
38 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | |
39 | #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | |
40 | S3C2410_UCON_RXILEVEL | \ | |
41 | S3C2410_UCON_TXIRQMODE | \ | |
42 | S3C2410_UCON_RXIRQMODE | \ | |
43 | S3C2410_UCON_RXFIFO_TOI | \ | |
44 | S3C2443_UCON_RXERR_IRQEN) | |
45 | ||
46 | #define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8 | |
47 | ||
48 | #define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | |
49 | S5PV210_UFCON_TXTRIG256 | \ | |
50 | S5PV210_UFCON_RXTRIG256) | |
51 | ||
52 | static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = { | |
53 | [0] = { | |
54 | .hwport = 0, | |
55 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
56 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
57 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
58 | }, | |
59 | [1] = { | |
60 | .hwport = 1, | |
61 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
62 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
63 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
64 | }, | |
65 | [2] = { | |
66 | .hwport = 2, | |
67 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
68 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
69 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
70 | }, | |
71 | [3] = { | |
72 | .hwport = 3, | |
73 | .ucon = UNIVERSAL_UCON_DEFAULT, | |
74 | .ulcon = UNIVERSAL_ULCON_DEFAULT, | |
75 | .ufcon = UNIVERSAL_UFCON_DEFAULT, | |
76 | }, | |
77 | }; | |
78 | ||
4d838ec0 MS |
79 | static struct regulator_consumer_supply max8952_consumer = |
80 | REGULATOR_SUPPLY("vddarm", NULL); | |
81 | ||
82 | static struct max8952_platform_data universal_max8952_pdata __initdata = { | |
83 | .gpio_vid0 = EXYNOS4_GPX0(3), | |
84 | .gpio_vid1 = EXYNOS4_GPX0(4), | |
85 | .gpio_en = -1, /* Not controllable, set "Always High" */ | |
86 | .default_mode = 0, /* vid0 = 0, vid1 = 0 */ | |
87 | .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */ | |
88 | .sync_freq = 0, /* default: fastest */ | |
89 | .ramp_speed = 0, /* default: fastest */ | |
90 | ||
91 | .reg_data = { | |
92 | .constraints = { | |
93 | .name = "VARM_1.2V", | |
94 | .min_uV = 770000, | |
95 | .max_uV = 1400000, | |
96 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, | |
97 | .always_on = 1, | |
98 | .boot_on = 1, | |
99 | }, | |
100 | .num_consumer_supplies = 1, | |
101 | .consumer_supplies = &max8952_consumer, | |
102 | }, | |
103 | }; | |
104 | ||
105 | static struct regulator_consumer_supply lp3974_buck1_consumer = | |
106 | REGULATOR_SUPPLY("vddint", NULL); | |
107 | ||
108 | static struct regulator_consumer_supply lp3974_buck2_consumer = | |
109 | REGULATOR_SUPPLY("vddg3d", NULL); | |
110 | ||
111 | static struct regulator_init_data lp3974_buck1_data = { | |
112 | .constraints = { | |
113 | .name = "VINT_1.1V", | |
114 | .min_uV = 750000, | |
115 | .max_uV = 1500000, | |
116 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
117 | REGULATOR_CHANGE_STATUS, | |
118 | .boot_on = 1, | |
119 | .state_mem = { | |
120 | .disabled = 1, | |
121 | }, | |
122 | }, | |
123 | .num_consumer_supplies = 1, | |
124 | .consumer_supplies = &lp3974_buck1_consumer, | |
125 | }; | |
126 | ||
127 | static struct regulator_init_data lp3974_buck2_data = { | |
128 | .constraints = { | |
129 | .name = "VG3D_1.1V", | |
130 | .min_uV = 750000, | |
131 | .max_uV = 1500000, | |
132 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | |
133 | REGULATOR_CHANGE_STATUS, | |
134 | .boot_on = 1, | |
135 | .state_mem = { | |
136 | .disabled = 1, | |
137 | }, | |
138 | }, | |
139 | .num_consumer_supplies = 1, | |
140 | .consumer_supplies = &lp3974_buck2_consumer, | |
141 | }; | |
142 | ||
143 | static struct regulator_init_data lp3974_buck3_data = { | |
144 | .constraints = { | |
145 | .name = "VCC_1.8V", | |
146 | .min_uV = 1800000, | |
147 | .max_uV = 1800000, | |
148 | .apply_uV = 1, | |
149 | .always_on = 1, | |
150 | .state_mem = { | |
151 | .enabled = 1, | |
152 | }, | |
153 | }, | |
154 | }; | |
155 | ||
156 | static struct regulator_init_data lp3974_buck4_data = { | |
157 | .constraints = { | |
158 | .name = "VMEM_1.2V", | |
159 | .min_uV = 1200000, | |
160 | .max_uV = 1200000, | |
161 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
162 | .apply_uV = 1, | |
163 | .state_mem = { | |
164 | .disabled = 1, | |
165 | }, | |
166 | }, | |
167 | }; | |
168 | ||
169 | static struct regulator_init_data lp3974_ldo2_data = { | |
170 | .constraints = { | |
171 | .name = "VALIVE_1.2V", | |
172 | .min_uV = 1200000, | |
173 | .max_uV = 1200000, | |
174 | .apply_uV = 1, | |
175 | .always_on = 1, | |
176 | .state_mem = { | |
177 | .enabled = 1, | |
178 | }, | |
179 | }, | |
180 | }; | |
181 | ||
182 | static struct regulator_init_data lp3974_ldo3_data = { | |
183 | .constraints = { | |
184 | .name = "VUSB+MIPI_1.1V", | |
185 | .min_uV = 1100000, | |
186 | .max_uV = 1100000, | |
187 | .apply_uV = 1, | |
188 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
189 | .state_mem = { | |
190 | .disabled = 1, | |
191 | }, | |
192 | }, | |
193 | }; | |
194 | ||
195 | static struct regulator_init_data lp3974_ldo4_data = { | |
196 | .constraints = { | |
197 | .name = "VADC_3.3V", | |
198 | .min_uV = 3300000, | |
199 | .max_uV = 3300000, | |
200 | .apply_uV = 1, | |
201 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
202 | .state_mem = { | |
203 | .disabled = 1, | |
204 | }, | |
205 | }, | |
206 | }; | |
207 | ||
208 | static struct regulator_init_data lp3974_ldo5_data = { | |
209 | .constraints = { | |
210 | .name = "VTF_2.8V", | |
211 | .min_uV = 2800000, | |
212 | .max_uV = 2800000, | |
213 | .apply_uV = 1, | |
214 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
215 | .state_mem = { | |
216 | .disabled = 1, | |
217 | }, | |
218 | }, | |
219 | }; | |
220 | ||
221 | static struct regulator_init_data lp3974_ldo6_data = { | |
222 | .constraints = { | |
223 | .name = "LDO6", | |
224 | .min_uV = 2000000, | |
225 | .max_uV = 2000000, | |
226 | .apply_uV = 1, | |
227 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
228 | .state_mem = { | |
229 | .disabled = 1, | |
230 | }, | |
231 | }, | |
232 | }; | |
233 | ||
234 | static struct regulator_init_data lp3974_ldo7_data = { | |
235 | .constraints = { | |
236 | .name = "VLCD+VMIPI_1.8V", | |
237 | .min_uV = 1800000, | |
238 | .max_uV = 1800000, | |
239 | .apply_uV = 1, | |
240 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
241 | .state_mem = { | |
242 | .disabled = 1, | |
243 | }, | |
244 | }, | |
245 | }; | |
246 | ||
247 | static struct regulator_init_data lp3974_ldo8_data = { | |
248 | .constraints = { | |
249 | .name = "VUSB+VDAC_3.3V", | |
250 | .min_uV = 3300000, | |
251 | .max_uV = 3300000, | |
252 | .apply_uV = 1, | |
253 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
254 | .state_mem = { | |
255 | .disabled = 1, | |
256 | }, | |
257 | }, | |
258 | }; | |
259 | ||
260 | static struct regulator_init_data lp3974_ldo9_data = { | |
261 | .constraints = { | |
262 | .name = "VCC_2.8V", | |
263 | .min_uV = 2800000, | |
264 | .max_uV = 2800000, | |
265 | .apply_uV = 1, | |
266 | .always_on = 1, | |
267 | .state_mem = { | |
268 | .enabled = 1, | |
269 | }, | |
270 | }, | |
271 | }; | |
272 | ||
273 | static struct regulator_init_data lp3974_ldo10_data = { | |
274 | .constraints = { | |
275 | .name = "VPLL_1.1V", | |
276 | .min_uV = 1100000, | |
277 | .max_uV = 1100000, | |
278 | .boot_on = 1, | |
279 | .apply_uV = 1, | |
280 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
281 | .state_mem = { | |
282 | .disabled = 1, | |
283 | }, | |
284 | }, | |
285 | }; | |
286 | ||
287 | static struct regulator_init_data lp3974_ldo11_data = { | |
288 | .constraints = { | |
289 | .name = "CAM_AF_3.3V", | |
290 | .min_uV = 3300000, | |
291 | .max_uV = 3300000, | |
292 | .apply_uV = 1, | |
293 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
294 | .state_mem = { | |
295 | .disabled = 1, | |
296 | }, | |
297 | }, | |
298 | }; | |
299 | ||
300 | static struct regulator_init_data lp3974_ldo12_data = { | |
301 | .constraints = { | |
302 | .name = "PS_2.8V", | |
303 | .min_uV = 2800000, | |
304 | .max_uV = 2800000, | |
305 | .apply_uV = 1, | |
306 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
307 | .state_mem = { | |
308 | .disabled = 1, | |
309 | }, | |
310 | }, | |
311 | }; | |
312 | ||
313 | static struct regulator_init_data lp3974_ldo13_data = { | |
314 | .constraints = { | |
315 | .name = "VHIC_1.2V", | |
316 | .min_uV = 1200000, | |
317 | .max_uV = 1200000, | |
318 | .apply_uV = 1, | |
319 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
320 | .state_mem = { | |
321 | .disabled = 1, | |
322 | }, | |
323 | }, | |
324 | }; | |
325 | ||
326 | static struct regulator_init_data lp3974_ldo14_data = { | |
327 | .constraints = { | |
328 | .name = "CAM_I_HOST_1.8V", | |
329 | .min_uV = 1800000, | |
330 | .max_uV = 1800000, | |
331 | .apply_uV = 1, | |
332 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
333 | .state_mem = { | |
334 | .disabled = 1, | |
335 | }, | |
336 | }, | |
337 | }; | |
338 | ||
339 | static struct regulator_init_data lp3974_ldo15_data = { | |
340 | .constraints = { | |
341 | .name = "CAM_S_DIG+FM33_CORE_1.2V", | |
342 | .min_uV = 1200000, | |
343 | .max_uV = 1200000, | |
344 | .apply_uV = 1, | |
345 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
346 | .state_mem = { | |
347 | .disabled = 1, | |
348 | }, | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct regulator_init_data lp3974_ldo16_data = { | |
353 | .constraints = { | |
354 | .name = "CAM_S_ANA_2.8V", | |
355 | .min_uV = 2800000, | |
356 | .max_uV = 2800000, | |
357 | .apply_uV = 1, | |
358 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
359 | .state_mem = { | |
360 | .disabled = 1, | |
361 | }, | |
362 | }, | |
363 | }; | |
364 | ||
365 | static struct regulator_init_data lp3974_ldo17_data = { | |
366 | .constraints = { | |
367 | .name = "VCC_3.0V_LCD", | |
368 | .min_uV = 3000000, | |
369 | .max_uV = 3000000, | |
370 | .apply_uV = 1, | |
371 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
372 | .boot_on = 1, | |
373 | .state_mem = { | |
374 | .disabled = 1, | |
375 | }, | |
376 | }, | |
377 | }; | |
378 | ||
379 | static struct regulator_init_data lp3974_32khz_ap_data = { | |
380 | .constraints = { | |
381 | .name = "32KHz AP", | |
382 | .always_on = 1, | |
383 | .state_mem = { | |
384 | .enabled = 1, | |
385 | }, | |
386 | }, | |
387 | }; | |
388 | ||
389 | static struct regulator_init_data lp3974_32khz_cp_data = { | |
390 | .constraints = { | |
391 | .name = "32KHz CP", | |
392 | .state_mem = { | |
393 | .disabled = 1, | |
394 | }, | |
395 | }, | |
396 | }; | |
397 | ||
398 | static struct regulator_init_data lp3974_vichg_data = { | |
399 | .constraints = { | |
400 | .name = "VICHG", | |
401 | .state_mem = { | |
402 | .disabled = 1, | |
403 | }, | |
404 | }, | |
405 | }; | |
406 | ||
407 | static struct regulator_init_data lp3974_esafeout1_data = { | |
408 | .constraints = { | |
409 | .name = "SAFEOUT1", | |
410 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
411 | .state_mem = { | |
412 | .enabled = 1, | |
413 | }, | |
414 | }, | |
415 | }; | |
416 | ||
417 | static struct regulator_init_data lp3974_esafeout2_data = { | |
418 | .constraints = { | |
419 | .name = "SAFEOUT2", | |
420 | .boot_on = 1, | |
421 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
422 | .state_mem = { | |
423 | .enabled = 1, | |
424 | }, | |
425 | }, | |
426 | }; | |
427 | ||
428 | static struct max8998_regulator_data lp3974_regulators[] = { | |
429 | { MAX8998_LDO2, &lp3974_ldo2_data }, | |
430 | { MAX8998_LDO3, &lp3974_ldo3_data }, | |
431 | { MAX8998_LDO4, &lp3974_ldo4_data }, | |
432 | { MAX8998_LDO5, &lp3974_ldo5_data }, | |
433 | { MAX8998_LDO6, &lp3974_ldo6_data }, | |
434 | { MAX8998_LDO7, &lp3974_ldo7_data }, | |
435 | { MAX8998_LDO8, &lp3974_ldo8_data }, | |
436 | { MAX8998_LDO9, &lp3974_ldo9_data }, | |
437 | { MAX8998_LDO10, &lp3974_ldo10_data }, | |
438 | { MAX8998_LDO11, &lp3974_ldo11_data }, | |
439 | { MAX8998_LDO12, &lp3974_ldo12_data }, | |
440 | { MAX8998_LDO13, &lp3974_ldo13_data }, | |
441 | { MAX8998_LDO14, &lp3974_ldo14_data }, | |
442 | { MAX8998_LDO15, &lp3974_ldo15_data }, | |
443 | { MAX8998_LDO16, &lp3974_ldo16_data }, | |
444 | { MAX8998_LDO17, &lp3974_ldo17_data }, | |
445 | { MAX8998_BUCK1, &lp3974_buck1_data }, | |
446 | { MAX8998_BUCK2, &lp3974_buck2_data }, | |
447 | { MAX8998_BUCK3, &lp3974_buck3_data }, | |
448 | { MAX8998_BUCK4, &lp3974_buck4_data }, | |
449 | { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data }, | |
450 | { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data }, | |
451 | { MAX8998_ENVICHG, &lp3974_vichg_data }, | |
452 | { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data }, | |
453 | { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data }, | |
454 | }; | |
455 | ||
456 | static struct max8998_platform_data universal_lp3974_pdata = { | |
457 | .num_regulators = ARRAY_SIZE(lp3974_regulators), | |
458 | .regulators = lp3974_regulators, | |
459 | .buck1_voltage1 = 1100000, /* INT */ | |
460 | .buck1_voltage2 = 1000000, | |
461 | .buck1_voltage3 = 1100000, | |
462 | .buck1_voltage4 = 1000000, | |
463 | .buck1_set1 = EXYNOS4_GPX0(5), | |
464 | .buck1_set2 = EXYNOS4_GPX0(6), | |
465 | .buck2_voltage1 = 1200000, /* G3D */ | |
466 | .buck2_voltage2 = 1100000, | |
467 | .buck1_default_idx = 0, | |
468 | .buck2_set3 = EXYNOS4_GPE2(0), | |
469 | .buck2_default_idx = 0, | |
470 | .wakeup = true, | |
471 | }; | |
472 | ||
473 | /* GPIO I2C 5 (PMIC) */ | |
474 | static struct i2c_board_info i2c5_devs[] __initdata = { | |
475 | { | |
476 | I2C_BOARD_INFO("max8952", 0xC0 >> 1), | |
477 | .platform_data = &universal_max8952_pdata, | |
478 | }, { | |
479 | I2C_BOARD_INFO("lp3974", 0xCC >> 1), | |
480 | .platform_data = &universal_lp3974_pdata, | |
481 | }, | |
482 | }; | |
483 | ||
0b398b69 MS |
484 | /* I2C3 (TSP) */ |
485 | static struct mxt_platform_data qt602240_platform_data = { | |
486 | .x_line = 19, | |
487 | .y_line = 11, | |
488 | .x_size = 800, | |
489 | .y_size = 480, | |
490 | .blen = 0x11, | |
491 | .threshold = 0x28, | |
492 | .voltage = 2800000, /* 2.8V */ | |
493 | .orient = MXT_DIAGONAL, | |
494 | }; | |
495 | ||
496 | static struct i2c_board_info i2c3_devs[] __initdata = { | |
497 | { | |
498 | I2C_BOARD_INFO("qt602240_ts", 0x4a), | |
499 | .platform_data = &qt602240_platform_data, | |
500 | }, | |
501 | }; | |
502 | ||
503 | static void __init universal_tsp_init(void) | |
504 | { | |
505 | int gpio; | |
506 | ||
507 | /* TSP_LDO_ON: XMDMADDR_11 */ | |
508 | gpio = EXYNOS4_GPE2(3); | |
509 | gpio_request(gpio, "TSP_LDO_ON"); | |
510 | gpio_direction_output(gpio, 1); | |
511 | gpio_export(gpio, 0); | |
512 | ||
513 | /* TSP_INT: XMDMADDR_7 */ | |
514 | gpio = EXYNOS4_GPE1(7); | |
515 | gpio_request(gpio, "TSP_INT"); | |
516 | ||
517 | s5p_register_gpio_interrupt(gpio); | |
518 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | |
519 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); | |
520 | i2c3_devs[0].irq = gpio_to_irq(gpio); | |
521 | } | |
522 | ||
523 | ||
b908af44 MS |
524 | /* GPIO I2C 12 (3 Touchkey) */ |
525 | static uint32_t touchkey_keymap[] = { | |
526 | /* MCS_KEY_MAP(value, keycode) */ | |
527 | MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */ | |
528 | MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */ | |
529 | }; | |
530 | ||
531 | static struct mcs_platform_data touchkey_data = { | |
532 | .keymap = touchkey_keymap, | |
533 | .keymap_size = ARRAY_SIZE(touchkey_keymap), | |
534 | .key_maxval = 2, | |
535 | }; | |
536 | ||
537 | /* GPIO I2C 3_TOUCH 2.8V */ | |
538 | #define I2C_GPIO_BUS_12 12 | |
539 | static struct i2c_gpio_platform_data i2c_gpio12_data = { | |
540 | .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */ | |
541 | .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */ | |
542 | }; | |
543 | ||
544 | static struct platform_device i2c_gpio12 = { | |
545 | .name = "i2c-gpio", | |
546 | .id = I2C_GPIO_BUS_12, | |
547 | .dev = { | |
548 | .platform_data = &i2c_gpio12_data, | |
549 | }, | |
550 | }; | |
551 | ||
552 | static struct i2c_board_info i2c_gpio12_devs[] __initdata = { | |
553 | { | |
554 | I2C_BOARD_INFO("mcs5080_touchkey", 0x20), | |
555 | .platform_data = &touchkey_data, | |
556 | }, | |
557 | }; | |
558 | ||
559 | static void __init universal_touchkey_init(void) | |
560 | { | |
561 | int gpio; | |
562 | ||
563 | gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */ | |
564 | gpio_request(gpio, "3_TOUCH_INT"); | |
565 | s5p_register_gpio_interrupt(gpio); | |
566 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf)); | |
567 | i2c_gpio12_devs[0].irq = gpio_to_irq(gpio); | |
568 | ||
569 | gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */ | |
570 | gpio_request(gpio, "3_TOUCH_EN"); | |
571 | gpio_direction_output(gpio, 1); | |
572 | } | |
573 | ||
4d838ec0 | 574 | /* GPIO KEYS */ |
34d79315 KP |
575 | static struct gpio_keys_button universal_gpio_keys_tables[] = { |
576 | { | |
577 | .code = KEY_VOLUMEUP, | |
d11135ca | 578 | .gpio = EXYNOS4_GPX2(0), /* XEINT16 */ |
34d79315 KP |
579 | .desc = "gpio-keys: KEY_VOLUMEUP", |
580 | .type = EV_KEY, | |
581 | .active_low = 1, | |
582 | .debounce_interval = 1, | |
583 | }, { | |
584 | .code = KEY_VOLUMEDOWN, | |
d11135ca | 585 | .gpio = EXYNOS4_GPX2(1), /* XEINT17 */ |
34d79315 KP |
586 | .desc = "gpio-keys: KEY_VOLUMEDOWN", |
587 | .type = EV_KEY, | |
588 | .active_low = 1, | |
589 | .debounce_interval = 1, | |
590 | }, { | |
591 | .code = KEY_CONFIG, | |
d11135ca | 592 | .gpio = EXYNOS4_GPX2(2), /* XEINT18 */ |
34d79315 KP |
593 | .desc = "gpio-keys: KEY_CONFIG", |
594 | .type = EV_KEY, | |
595 | .active_low = 1, | |
596 | .debounce_interval = 1, | |
597 | }, { | |
598 | .code = KEY_CAMERA, | |
d11135ca | 599 | .gpio = EXYNOS4_GPX2(3), /* XEINT19 */ |
34d79315 KP |
600 | .desc = "gpio-keys: KEY_CAMERA", |
601 | .type = EV_KEY, | |
602 | .active_low = 1, | |
603 | .debounce_interval = 1, | |
604 | }, { | |
605 | .code = KEY_OK, | |
d11135ca | 606 | .gpio = EXYNOS4_GPX3(5), /* XEINT29 */ |
34d79315 KP |
607 | .desc = "gpio-keys: KEY_OK", |
608 | .type = EV_KEY, | |
609 | .active_low = 1, | |
610 | .debounce_interval = 1, | |
611 | }, | |
612 | }; | |
613 | ||
614 | static struct gpio_keys_platform_data universal_gpio_keys_data = { | |
615 | .buttons = universal_gpio_keys_tables, | |
616 | .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables), | |
617 | }; | |
618 | ||
619 | static struct platform_device universal_gpio_keys = { | |
620 | .name = "gpio-keys", | |
621 | .dev = { | |
622 | .platform_data = &universal_gpio_keys_data, | |
623 | }, | |
624 | }; | |
625 | ||
a8928ce7 KP |
626 | /* eMMC */ |
627 | static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { | |
628 | .max_width = 8, | |
629 | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | | |
630 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
631 | MMC_CAP_DISABLE), | |
632 | .cd_type = S3C_SDHCI_CD_PERMANENT, | |
633 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
634 | }; | |
635 | ||
636 | static struct regulator_consumer_supply mmc0_supplies[] = { | |
637 | REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"), | |
638 | }; | |
639 | ||
640 | static struct regulator_init_data mmc0_fixed_voltage_init_data = { | |
641 | .constraints = { | |
642 | .name = "VMEM_VDD_2.8V", | |
643 | .valid_ops_mask = REGULATOR_CHANGE_STATUS, | |
644 | }, | |
645 | .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies), | |
646 | .consumer_supplies = mmc0_supplies, | |
647 | }; | |
648 | ||
649 | static struct fixed_voltage_config mmc0_fixed_voltage_config = { | |
650 | .supply_name = "MASSMEMORY_EN", | |
651 | .microvolts = 2800000, | |
d11135ca | 652 | .gpio = EXYNOS4_GPE1(3), |
a8928ce7 KP |
653 | .enable_high = true, |
654 | .init_data = &mmc0_fixed_voltage_init_data, | |
655 | }; | |
656 | ||
657 | static struct platform_device mmc0_fixed_voltage = { | |
658 | .name = "reg-fixed-voltage", | |
659 | .id = 0, | |
660 | .dev = { | |
661 | .platform_data = &mmc0_fixed_voltage_config, | |
662 | }, | |
663 | }; | |
664 | ||
665 | /* SD */ | |
666 | static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = { | |
667 | .max_width = 4, | |
668 | .host_caps = MMC_CAP_4_BIT_DATA | | |
669 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
670 | MMC_CAP_DISABLE, | |
d11135ca | 671 | .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */ |
a8928ce7 KP |
672 | .ext_cd_gpio_invert = 1, |
673 | .cd_type = S3C_SDHCI_CD_GPIO, | |
674 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, | |
675 | }; | |
676 | ||
677 | /* WiFi */ | |
678 | static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = { | |
679 | .max_width = 4, | |
680 | .host_caps = MMC_CAP_4_BIT_DATA | | |
681 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | | |
682 | MMC_CAP_DISABLE, | |
683 | .cd_type = S3C_SDHCI_CD_EXTERNAL, | |
684 | }; | |
685 | ||
686 | static void __init universal_sdhci_init(void) | |
687 | { | |
688 | s3c_sdhci0_set_platdata(&universal_hsmmc0_data); | |
689 | s3c_sdhci2_set_platdata(&universal_hsmmc2_data); | |
690 | s3c_sdhci3_set_platdata(&universal_hsmmc3_data); | |
691 | } | |
692 | ||
3b7998f5 KP |
693 | /* I2C0 */ |
694 | static struct i2c_board_info i2c0_devs[] __initdata = { | |
695 | /* Camera, To be updated */ | |
696 | }; | |
697 | ||
698 | /* I2C1 */ | |
699 | static struct i2c_board_info i2c1_devs[] __initdata = { | |
700 | /* Gyro, To be updated */ | |
701 | }; | |
702 | ||
34d79315 | 703 | static struct platform_device *universal_devices[] __initdata = { |
a8928ce7 | 704 | /* Samsung Platform Devices */ |
edd967b8 MS |
705 | &s5p_device_fimc0, |
706 | &s5p_device_fimc1, | |
707 | &s5p_device_fimc2, | |
708 | &s5p_device_fimc3, | |
a8928ce7 KP |
709 | &mmc0_fixed_voltage, |
710 | &s3c_device_hsmmc0, | |
711 | &s3c_device_hsmmc2, | |
712 | &s3c_device_hsmmc3, | |
0b398b69 | 713 | &s3c_device_i2c3, |
4d838ec0 | 714 | &s3c_device_i2c5, |
a8928ce7 KP |
715 | |
716 | /* Universal Devices */ | |
b908af44 | 717 | &i2c_gpio12, |
34d79315 | 718 | &universal_gpio_keys, |
acf5eda9 | 719 | &s5p_device_onenand, |
34d79315 KP |
720 | }; |
721 | ||
516607d6 KP |
722 | static void __init universal_map_io(void) |
723 | { | |
724 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | |
725 | s3c24xx_init_clocks(24000000); | |
726 | s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); | |
727 | } | |
728 | ||
729 | static void __init universal_machine_init(void) | |
730 | { | |
a8928ce7 KP |
731 | universal_sdhci_init(); |
732 | ||
3b7998f5 KP |
733 | i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); |
734 | i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); | |
735 | ||
0b398b69 MS |
736 | universal_tsp_init(); |
737 | s3c_i2c3_set_platdata(NULL); | |
738 | i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); | |
739 | ||
4d838ec0 MS |
740 | s3c_i2c5_set_platdata(NULL); |
741 | i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); | |
742 | ||
b908af44 MS |
743 | universal_touchkey_init(); |
744 | i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, | |
745 | ARRAY_SIZE(i2c_gpio12_devs)); | |
746 | ||
34d79315 KP |
747 | /* Last */ |
748 | platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); | |
516607d6 KP |
749 | } |
750 | ||
751 | MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") | |
752 | /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ | |
516607d6 | 753 | .boot_params = S5P_PA_SDRAM + 0x100, |
d11135ca | 754 | .init_irq = exynos4_init_irq, |
516607d6 KP |
755 | .map_io = universal_map_io, |
756 | .init_machine = universal_machine_init, | |
d11135ca | 757 | .timer = &exynos4_timer, |
516607d6 | 758 | MACHINE_END |