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Merge branch 'next-samsung-devel' into next-samsung-devel-2
[deliverable/linux.git] / arch / arm / mach-exynos4 / mach-universal_c210.c
CommitLineData
d11135ca 1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
516607d6
KP		 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
34d79315 10#include <linux/platform_device.h>
516607d6 11#include <linux/serial_core.h>
34d79315 12#include <linux/input.h>
3b7998f5 13#include <linux/i2c.h>
34d79315
KP		 14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
f3f5bfe2 16#include <linux/fb.h>
4d838ec0 17#include <linux/mfd/max8998.h>
a8928ce7
KP		 18#include <linux/regulator/machine.h>
19#include <linux/regulator/fixed.h>
4d838ec0 20#include <linux/regulator/max8952.h>
a8928ce7 21#include <linux/mmc/host.h>
b908af44
MS		 22#include <linux/i2c-gpio.h>
23#include <linux/i2c/mcs.h>
0b398b69 24#include <linux/i2c/atmel_mxt_ts.h>
516607d6
KP		 25
26#include <asm/mach/arch.h>
27#include <asm/mach-types.h>
516607d6
KP		 28
29#include <plat/regs-serial.h>
d11135ca 30#include <plat/exynos4.h>
516607d6 31#include <plat/cpu.h>
acf5eda9 32#include <plat/devs.h>
4d838ec0 33#include <plat/iic.h>
0b398b69 34#include <plat/gpio-cfg.h>
f3f5bfe2 35#include <plat/fb.h>
b14f04db 36#include <plat/mfc.h>
a8928ce7 37#include <plat/sdhci.h>
b14f04db 38#include <plat/pd.h>
f3f5bfe2 39#include <plat/regs-fb-v4.h>
05132182
SN		 40#include <plat/fimc-core.h>
41#include <plat/camport.h>
42#include <plat/mipi_csis.h>
516607d6
KP		 43
44#include <mach/map.h>
45
05132182
SN		 46#include <media/v4l2-mediabus.h>
47#include <media/s5p_fimc.h>
48#include <media/m5mols.h>
49
516607d6
KP		 50/* Following are default values for UCON, ULCON and UFCON UART registers */
51#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
52 S3C2410_UCON_RXILEVEL | \
53 S3C2410_UCON_TXIRQMODE | \
54 S3C2410_UCON_RXIRQMODE | \
55 S3C2410_UCON_RXFIFO_TOI | \
56 S3C2443_UCON_RXERR_IRQEN)
57
58#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
59
60#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
61 S5PV210_UFCON_TXTRIG256 | \
62 S5PV210_UFCON_RXTRIG256)
63
64static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
65 [0] = {
66 .hwport = 0,
67 .ucon = UNIVERSAL_UCON_DEFAULT,
68 .ulcon = UNIVERSAL_ULCON_DEFAULT,
69 .ufcon = UNIVERSAL_UFCON_DEFAULT,
70 },
71 [1] = {
72 .hwport = 1,
73 .ucon = UNIVERSAL_UCON_DEFAULT,
74 .ulcon = UNIVERSAL_ULCON_DEFAULT,
75 .ufcon = UNIVERSAL_UFCON_DEFAULT,
76 },
77 [2] = {
78 .hwport = 2,
79 .ucon = UNIVERSAL_UCON_DEFAULT,
80 .ulcon = UNIVERSAL_ULCON_DEFAULT,
81 .ufcon = UNIVERSAL_UFCON_DEFAULT,
82 },
83 [3] = {
84 .hwport = 3,
85 .ucon = UNIVERSAL_UCON_DEFAULT,
86 .ulcon = UNIVERSAL_ULCON_DEFAULT,
87 .ufcon = UNIVERSAL_UFCON_DEFAULT,
88 },
89};
90
4d838ec0 91static struct regulator_consumer_supply max8952_consumer =
c1a238aa 92 REGULATOR_SUPPLY("vdd_arm", NULL);
4d838ec0
MS		 93
94static struct max8952_platform_data universal_max8952_pdata __initdata = {
95 .gpio_vid0 = EXYNOS4_GPX0(3),
96 .gpio_vid1 = EXYNOS4_GPX0(4),
97 .gpio_en = -1, /* Not controllable, set "Always High" */
98 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
99 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
100 .sync_freq = 0, /* default: fastest */
101 .ramp_speed = 0, /* default: fastest */
102
103 .reg_data = {
104 .constraints = {
105 .name = "VARM_1.2V",
106 .min_uV = 770000,
107 .max_uV = 1400000,
108 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
109 .always_on = 1,
110 .boot_on = 1,
111 },
112 .num_consumer_supplies = 1,
113 .consumer_supplies = &max8952_consumer,
114 },
115};
116
117static struct regulator_consumer_supply lp3974_buck1_consumer =
c1a238aa 118 REGULATOR_SUPPLY("vdd_int", NULL);
4d838ec0
MS		 119
120static struct regulator_consumer_supply lp3974_buck2_consumer =
121 REGULATOR_SUPPLY("vddg3d", NULL);
122
d737cf29
TS		 123static struct regulator_consumer_supply lp3974_buck3_consumer =
124 REGULATOR_SUPPLY("vdet", "s5p-sdo");
125
4d838ec0
MS		 126static struct regulator_init_data lp3974_buck1_data = {
127 .constraints = {
128 .name = "VINT_1.1V",
129 .min_uV = 750000,
130 .max_uV = 1500000,
131 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
132 REGULATOR_CHANGE_STATUS,
133 .boot_on = 1,
134 .state_mem = {
135 .disabled = 1,
136 },
137 },
138 .num_consumer_supplies = 1,
139 .consumer_supplies = &lp3974_buck1_consumer,
140};
141
142static struct regulator_init_data lp3974_buck2_data = {
143 .constraints = {
144 .name = "VG3D_1.1V",
145 .min_uV = 750000,
146 .max_uV = 1500000,
147 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
148 REGULATOR_CHANGE_STATUS,
149 .boot_on = 1,
150 .state_mem = {
151 .disabled = 1,
152 },
153 },
154 .num_consumer_supplies = 1,
155 .consumer_supplies = &lp3974_buck2_consumer,
156};
157
158static struct regulator_init_data lp3974_buck3_data = {
159 .constraints = {
160 .name = "VCC_1.8V",
161 .min_uV = 1800000,
162 .max_uV = 1800000,
163 .apply_uV = 1,
164 .always_on = 1,
165 .state_mem = {
166 .enabled = 1,
167 },
168 },
d737cf29
TS		 169 .num_consumer_supplies = 1,
170 .consumer_supplies = &lp3974_buck3_consumer,
4d838ec0
MS		 171};
172
173static struct regulator_init_data lp3974_buck4_data = {
174 .constraints = {
175 .name = "VMEM_1.2V",
176 .min_uV = 1200000,
177 .max_uV = 1200000,
178 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
179 .apply_uV = 1,
180 .state_mem = {
181 .disabled = 1,
182 },
183 },
184};
185
186static struct regulator_init_data lp3974_ldo2_data = {
187 .constraints = {
188 .name = "VALIVE_1.2V",
189 .min_uV = 1200000,
190 .max_uV = 1200000,
191 .apply_uV = 1,
192 .always_on = 1,
193 .state_mem = {
194 .enabled = 1,
195 },
196 },
197};
198
d737cf29
TS		 199static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
200 REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
201 REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
05132182 202 REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
d737cf29
TS		 203};
204
4d838ec0
MS		 205static struct regulator_init_data lp3974_ldo3_data = {
206 .constraints = {
207 .name = "VUSB+MIPI_1.1V",
208 .min_uV = 1100000,
209 .max_uV = 1100000,
210 .apply_uV = 1,
211 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
212 .state_mem = {
213 .disabled = 1,
214 },
215 },
d737cf29
TS		 216 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
217 .consumer_supplies = lp3974_ldo3_consumer,
218};
219
220static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
221 REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
4d838ec0
MS		 222};
223
224static struct regulator_init_data lp3974_ldo4_data = {
225 .constraints = {
226 .name = "VADC_3.3V",
227 .min_uV = 3300000,
228 .max_uV = 3300000,
229 .apply_uV = 1,
230 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
231 .state_mem = {
232 .disabled = 1,
233 },
234 },
d737cf29
TS		 235 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
236 .consumer_supplies = lp3974_ldo4_consumer,
4d838ec0
MS		 237};
238
239static struct regulator_init_data lp3974_ldo5_data = {
240 .constraints = {
241 .name = "VTF_2.8V",
242 .min_uV = 2800000,
243 .max_uV = 2800000,
244 .apply_uV = 1,
245 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
246 .state_mem = {
247 .disabled = 1,
248 },
249 },
250};
251
252static struct regulator_init_data lp3974_ldo6_data = {
253 .constraints = {
254 .name = "LDO6",
255 .min_uV = 2000000,
256 .max_uV = 2000000,
257 .apply_uV = 1,
258 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
259 .state_mem = {
260 .disabled = 1,
261 },
262 },
263};
264
05132182
SN		 265static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
266 REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
267};
268
4d838ec0
MS		 269static struct regulator_init_data lp3974_ldo7_data = {
270 .constraints = {
271 .name = "VLCD+VMIPI_1.8V",
272 .min_uV = 1800000,
273 .max_uV = 1800000,
274 .apply_uV = 1,
275 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
276 .state_mem = {
277 .disabled = 1,
278 },
279 },
05132182
SN		 280 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
281 .consumer_supplies = lp3974_ldo7_consumer,
4d838ec0
MS		 282};
283
d737cf29
TS		 284static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
285 REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
286};
287
4d838ec0
MS		 288static struct regulator_init_data lp3974_ldo8_data = {
289 .constraints = {
290 .name = "VUSB+VDAC_3.3V",
291 .min_uV = 3300000,
292 .max_uV = 3300000,
293 .apply_uV = 1,
294 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
295 .state_mem = {
296 .disabled = 1,
297 },
298 },
d737cf29
TS		 299 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
300 .consumer_supplies = lp3974_ldo8_consumer,
4d838ec0
MS		 301};
302
303static struct regulator_init_data lp3974_ldo9_data = {
304 .constraints = {
305 .name = "VCC_2.8V",
306 .min_uV = 2800000,
307 .max_uV = 2800000,
308 .apply_uV = 1,
309 .always_on = 1,
310 .state_mem = {
311 .enabled = 1,
312 },
313 },
314};
315
316static struct regulator_init_data lp3974_ldo10_data = {
317 .constraints = {
318 .name = "VPLL_1.1V",
319 .min_uV = 1100000,
320 .max_uV = 1100000,
321 .boot_on = 1,
322 .apply_uV = 1,
323 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
324 .state_mem = {
325 .disabled = 1,
326 },
327 },
328};
329
05132182
SN		 330static struct regulator_consumer_supply lp3974_ldo11_consumer =
331 REGULATOR_SUPPLY("dig_28", "0-001f");
332
4d838ec0
MS		 333static struct regulator_init_data lp3974_ldo11_data = {
334 .constraints = {
335 .name = "CAM_AF_3.3V",
336 .min_uV = 3300000,
337 .max_uV = 3300000,
338 .apply_uV = 1,
339 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
340 .state_mem = {
341 .disabled = 1,
342 },
343 },
05132182
SN		 344 .num_consumer_supplies = 1,
345 .consumer_supplies = &lp3974_ldo11_consumer,
4d838ec0
MS		 346};
347
348static struct regulator_init_data lp3974_ldo12_data = {
349 .constraints = {
350 .name = "PS_2.8V",
351 .min_uV = 2800000,
352 .max_uV = 2800000,
353 .apply_uV = 1,
354 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
355 .state_mem = {
356 .disabled = 1,
357 },
358 },
359};
360
361static struct regulator_init_data lp3974_ldo13_data = {
362 .constraints = {
363 .name = "VHIC_1.2V",
364 .min_uV = 1200000,
365 .max_uV = 1200000,
366 .apply_uV = 1,
367 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
368 .state_mem = {
369 .disabled = 1,
370 },
371 },
372};
373
05132182
SN		 374static struct regulator_consumer_supply lp3974_ldo14_consumer =
375 REGULATOR_SUPPLY("dig_18", "0-001f");
376
4d838ec0
MS		 377static struct regulator_init_data lp3974_ldo14_data = {
378 .constraints = {
379 .name = "CAM_I_HOST_1.8V",
380 .min_uV = 1800000,
381 .max_uV = 1800000,
382 .apply_uV = 1,
383 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
384 .state_mem = {
385 .disabled = 1,
386 },
387 },
05132182
SN		 388 .num_consumer_supplies = 1,
389 .consumer_supplies = &lp3974_ldo14_consumer,
4d838ec0
MS		 390};
391
05132182
SN		 392
393static struct regulator_consumer_supply lp3974_ldo15_consumer =
394 REGULATOR_SUPPLY("dig_12", "0-001f");
395
4d838ec0
MS		 396static struct regulator_init_data lp3974_ldo15_data = {
397 .constraints = {
398 .name = "CAM_S_DIG+FM33_CORE_1.2V",
399 .min_uV = 1200000,
400 .max_uV = 1200000,
401 .apply_uV = 1,
402 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
403 .state_mem = {
404 .disabled = 1,
405 },
406 },
05132182
SN		 407 .num_consumer_supplies = 1,
408 .consumer_supplies = &lp3974_ldo15_consumer,
409};
410
411static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
412 REGULATOR_SUPPLY("a_sensor", "0-001f"),
4d838ec0
MS		 413};
414
415static struct regulator_init_data lp3974_ldo16_data = {
416 .constraints = {
417 .name = "CAM_S_ANA_2.8V",
418 .min_uV = 2800000,
419 .max_uV = 2800000,
420 .apply_uV = 1,
421 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
422 .state_mem = {
423 .disabled = 1,
424 },
425 },
05132182
SN		 426 .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
427 .consumer_supplies = lp3974_ldo16_consumer,
4d838ec0
MS		 428};
429
430static struct regulator_init_data lp3974_ldo17_data = {
431 .constraints = {
432 .name = "VCC_3.0V_LCD",
433 .min_uV = 3000000,
434 .max_uV = 3000000,
435 .apply_uV = 1,
436 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
437 .boot_on = 1,
438 .state_mem = {
439 .disabled = 1,
440 },
441 },
442};
443
444static struct regulator_init_data lp3974_32khz_ap_data = {
445 .constraints = {
446 .name = "32KHz AP",
447 .always_on = 1,
448 .state_mem = {
449 .enabled = 1,
450 },
451 },
452};
453
454static struct regulator_init_data lp3974_32khz_cp_data = {
455 .constraints = {
456 .name = "32KHz CP",
457 .state_mem = {
458 .disabled = 1,
459 },
460 },
461};
462
463static struct regulator_init_data lp3974_vichg_data = {
464 .constraints = {
465 .name = "VICHG",
466 .state_mem = {
467 .disabled = 1,
468 },
469 },
470};
471
472static struct regulator_init_data lp3974_esafeout1_data = {
473 .constraints = {
474 .name = "SAFEOUT1",
475 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
476 .state_mem = {
477 .enabled = 1,
478 },
479 },
480};
481
482static struct regulator_init_data lp3974_esafeout2_data = {
483 .constraints = {
484 .name = "SAFEOUT2",
485 .boot_on = 1,
486 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
487 .state_mem = {
488 .enabled = 1,
489 },
490 },
491};
492
493static struct max8998_regulator_data lp3974_regulators[] = {
494 { MAX8998_LDO2, &lp3974_ldo2_data },
495 { MAX8998_LDO3, &lp3974_ldo3_data },
496 { MAX8998_LDO4, &lp3974_ldo4_data },
497 { MAX8998_LDO5, &lp3974_ldo5_data },
498 { MAX8998_LDO6, &lp3974_ldo6_data },
499 { MAX8998_LDO7, &lp3974_ldo7_data },
500 { MAX8998_LDO8, &lp3974_ldo8_data },
501 { MAX8998_LDO9, &lp3974_ldo9_data },
502 { MAX8998_LDO10, &lp3974_ldo10_data },
503 { MAX8998_LDO11, &lp3974_ldo11_data },
504 { MAX8998_LDO12, &lp3974_ldo12_data },
505 { MAX8998_LDO13, &lp3974_ldo13_data },
506 { MAX8998_LDO14, &lp3974_ldo14_data },
507 { MAX8998_LDO15, &lp3974_ldo15_data },
508 { MAX8998_LDO16, &lp3974_ldo16_data },
509 { MAX8998_LDO17, &lp3974_ldo17_data },
510 { MAX8998_BUCK1, &lp3974_buck1_data },
511 { MAX8998_BUCK2, &lp3974_buck2_data },
512 { MAX8998_BUCK3, &lp3974_buck3_data },
513 { MAX8998_BUCK4, &lp3974_buck4_data },
514 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
515 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
516 { MAX8998_ENVICHG, &lp3974_vichg_data },
517 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
518 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
519};
520
521static struct max8998_platform_data universal_lp3974_pdata = {
522 .num_regulators = ARRAY_SIZE(lp3974_regulators),
523 .regulators = lp3974_regulators,
524 .buck1_voltage1 = 1100000, /* INT */
525 .buck1_voltage2 = 1000000,
526 .buck1_voltage3 = 1100000,
527 .buck1_voltage4 = 1000000,
528 .buck1_set1 = EXYNOS4_GPX0(5),
529 .buck1_set2 = EXYNOS4_GPX0(6),
530 .buck2_voltage1 = 1200000, /* G3D */
531 .buck2_voltage2 = 1100000,
532 .buck1_default_idx = 0,
533 .buck2_set3 = EXYNOS4_GPE2(0),
534 .buck2_default_idx = 0,
535 .wakeup = true,
536};
537
05132182
SN		 538
539enum fixed_regulator_id {
540 FIXED_REG_ID_MMC0,
541 FIXED_REG_ID_HDMI_5V,
542 FIXED_REG_ID_CAM_S_IF,
543 FIXED_REG_ID_CAM_I_CORE,
544 FIXED_REG_ID_CAM_VT_DIO,
545};
546
d737cf29
TS		 547static struct regulator_consumer_supply hdmi_fixed_consumer =
548 REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
549
550static struct regulator_init_data hdmi_fixed_voltage_init_data = {
551 .constraints = {
552 .name = "HDMI_5V",
553 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
554 },
555 .num_consumer_supplies = 1,
556 .consumer_supplies = &hdmi_fixed_consumer,
557};
558
559static struct fixed_voltage_config hdmi_fixed_voltage_config = {
560 .supply_name = "HDMI_EN1",
561 .microvolts = 5000000,
562 .gpio = EXYNOS4_GPE0(1),
563 .enable_high = true,
564 .init_data = &hdmi_fixed_voltage_init_data,
565};
566
567static struct platform_device hdmi_fixed_voltage = {
568 .name = "reg-fixed-voltage",
05132182 569 .id = FIXED_REG_ID_HDMI_5V,
d737cf29
TS		 570 .dev = {
571 .platform_data = &hdmi_fixed_voltage_config,
572 },
573};
574
4d838ec0
MS		 575/* GPIO I2C 5 (PMIC) */
576static struct i2c_board_info i2c5_devs[] __initdata = {
577 {
578 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
579 .platform_data = &universal_max8952_pdata,
580 }, {
581 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
582 .platform_data = &universal_lp3974_pdata,
583 },
584};
585
0b398b69
MS		 586/* I2C3 (TSP) */
587static struct mxt_platform_data qt602240_platform_data = {
588 .x_line = 19,
589 .y_line = 11,
590 .x_size = 800,
591 .y_size = 480,
592 .blen = 0x11,
593 .threshold = 0x28,
594 .voltage = 2800000, /* 2.8V */
595 .orient = MXT_DIAGONAL,
596};
597
598static struct i2c_board_info i2c3_devs[] __initdata = {
599 {
600 I2C_BOARD_INFO("qt602240_ts", 0x4a),
601 .platform_data = &qt602240_platform_data,
602 },
603};
604
605static void __init universal_tsp_init(void)
606{
607 int gpio;
608
609 /* TSP_LDO_ON: XMDMADDR_11 */
610 gpio = EXYNOS4_GPE2(3);
611 gpio_request(gpio, "TSP_LDO_ON");
612 gpio_direction_output(gpio, 1);
613 gpio_export(gpio, 0);
614
615 /* TSP_INT: XMDMADDR_7 */
616 gpio = EXYNOS4_GPE1(7);
617 gpio_request(gpio, "TSP_INT");
618
619 s5p_register_gpio_interrupt(gpio);
620 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
621 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
622 i2c3_devs[0].irq = gpio_to_irq(gpio);
623}
624
625
b908af44
MS		 626/* GPIO I2C 12 (3 Touchkey) */
627static uint32_t touchkey_keymap[] = {
628 /* MCS_KEY_MAP(value, keycode) */
629 MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
630 MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
631};
632
633static struct mcs_platform_data touchkey_data = {
634 .keymap = touchkey_keymap,
635 .keymap_size = ARRAY_SIZE(touchkey_keymap),
636 .key_maxval = 2,
637};
638
639/* GPIO I2C 3_TOUCH 2.8V */
640#define I2C_GPIO_BUS_12 12
641static struct i2c_gpio_platform_data i2c_gpio12_data = {
642 .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
643 .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
644};
645
646static struct platform_device i2c_gpio12 = {
647 .name = "i2c-gpio",
648 .id = I2C_GPIO_BUS_12,
649 .dev = {
650 .platform_data = &i2c_gpio12_data,
651 },
652};
653
654static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
655 {
656 I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
657 .platform_data = &touchkey_data,
658 },
659};
660
661static void __init universal_touchkey_init(void)
662{
663 int gpio;
664
665 gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
666 gpio_request(gpio, "3_TOUCH_INT");
667 s5p_register_gpio_interrupt(gpio);
668 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
669 i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
670
671 gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
672 gpio_request(gpio, "3_TOUCH_EN");
673 gpio_direction_output(gpio, 1);
674}
675
05132182
SN		 676static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
677 .frequency = 300 * 1000,
678 .sda_delay = 200,
679};
680
4d838ec0 681/* GPIO KEYS */
34d79315
KP		 682static struct gpio_keys_button universal_gpio_keys_tables[] = {
683 {
684 .code = KEY_VOLUMEUP,
d11135ca 685 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
34d79315
KP		 686 .desc = "gpio-keys: KEY_VOLUMEUP",
687 .type = EV_KEY,
688 .active_low = 1,
689 .debounce_interval = 1,
690 }, {
691 .code = KEY_VOLUMEDOWN,
d11135ca 692 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
34d79315
KP		 693 .desc = "gpio-keys: KEY_VOLUMEDOWN",
694 .type = EV_KEY,
695 .active_low = 1,
696 .debounce_interval = 1,
697 }, {
698 .code = KEY_CONFIG,
d11135ca 699 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
34d79315
KP		 700 .desc = "gpio-keys: KEY_CONFIG",
701 .type = EV_KEY,
702 .active_low = 1,
703 .debounce_interval = 1,
704 }, {
705 .code = KEY_CAMERA,
d11135ca 706 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
34d79315
KP		 707 .desc = "gpio-keys: KEY_CAMERA",
708 .type = EV_KEY,
709 .active_low = 1,
710 .debounce_interval = 1,
711 }, {
712 .code = KEY_OK,
d11135ca 713 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
34d79315
KP		 714 .desc = "gpio-keys: KEY_OK",
715 .type = EV_KEY,
716 .active_low = 1,
717 .debounce_interval = 1,
718 },
719};
720
721static struct gpio_keys_platform_data universal_gpio_keys_data = {
722 .buttons = universal_gpio_keys_tables,
723 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
724};
725
726static struct platform_device universal_gpio_keys = {
727 .name = "gpio-keys",
728 .dev = {
729 .platform_data = &universal_gpio_keys_data,
730 },
731};
732
a8928ce7
KP		 733/* eMMC */
734static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
735 .max_width = 8,
736 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
737 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
738 MMC_CAP_DISABLE),
739 .cd_type = S3C_SDHCI_CD_PERMANENT,
740 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
741};
742
743static struct regulator_consumer_supply mmc0_supplies[] = {
744 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
745};
746
747static struct regulator_init_data mmc0_fixed_voltage_init_data = {
748 .constraints = {
749 .name = "VMEM_VDD_2.8V",
750 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
751 },
752 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
753 .consumer_supplies = mmc0_supplies,
754};
755
756static struct fixed_voltage_config mmc0_fixed_voltage_config = {
757 .supply_name = "MASSMEMORY_EN",
758 .microvolts = 2800000,
d11135ca 759 .gpio = EXYNOS4_GPE1(3),
a8928ce7
KP		 760 .enable_high = true,
761 .init_data = &mmc0_fixed_voltage_init_data,
762};
763
764static struct platform_device mmc0_fixed_voltage = {
765 .name = "reg-fixed-voltage",
05132182 766 .id = FIXED_REG_ID_MMC0,
a8928ce7
KP		 767 .dev = {
768 .platform_data = &mmc0_fixed_voltage_config,
769 },
770};
771
772/* SD */
773static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
774 .max_width = 4,
775 .host_caps = MMC_CAP_4_BIT_DATA |
776 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
777 MMC_CAP_DISABLE,
d11135ca 778 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
a8928ce7
KP		 779 .ext_cd_gpio_invert = 1,
780 .cd_type = S3C_SDHCI_CD_GPIO,
781 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
782};
783
784/* WiFi */
785static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
786 .max_width = 4,
787 .host_caps = MMC_CAP_4_BIT_DATA |
788 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
789 MMC_CAP_DISABLE,
790 .cd_type = S3C_SDHCI_CD_EXTERNAL,
791};
792
793static void __init universal_sdhci_init(void)
794{
795 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
796 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
797 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
798}
799
3b7998f5
KP		 800/* I2C1 */
801static struct i2c_board_info i2c1_devs[] __initdata = {
802 /* Gyro, To be updated */
803};
804
f3f5bfe2
MS		 805/* Frame Buffer */
806static struct s3c_fb_pd_win universal_fb_win0 = {
807 .win_mode = {
808 .left_margin = 16,
809 .right_margin = 16,
810 .upper_margin = 2,
811 .lower_margin = 28,
812 .hsync_len = 2,
813 .vsync_len = 1,
814 .xres = 480,
815 .yres = 800,
816 .refresh = 55,
817 },
818 .max_bpp = 32,
819 .default_bpp = 16,
820};
821
822static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
823 .win[0] = &universal_fb_win0,
824 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
825 VIDCON0_CLKSEL_LCD,
826 .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
827 | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
828 .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
829};
830
05132182
SN		 831static struct regulator_consumer_supply cam_i_core_supply =
832 REGULATOR_SUPPLY("core", "0-001f");
833
834static struct regulator_init_data cam_i_core_reg_init_data = {
835 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
836 .num_consumer_supplies = 1,
837 .consumer_supplies = &cam_i_core_supply,
838};
839
840static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
841 .supply_name = "CAM_I_CORE_1.2V",
842 .microvolts = 1200000,
843 .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
844 .enable_high = 1,
845 .init_data = &cam_i_core_reg_init_data,
846};
847
848static struct platform_device cam_i_core_fixed_reg_dev = {
849 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
850 .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
851};
852
853static struct regulator_consumer_supply cam_s_if_supply =
854 REGULATOR_SUPPLY("d_sensor", "0-001f");
855
856static struct regulator_init_data cam_s_if_reg_init_data = {
857 .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
858 .num_consumer_supplies = 1,
859 .consumer_supplies = &cam_s_if_supply,
860};
861
862static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
863 .supply_name = "CAM_S_IF_1.8V",
864 .microvolts = 1800000,
865 .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
866 .enable_high = 1,
867 .init_data = &cam_s_if_reg_init_data,
868};
869
870static struct platform_device cam_s_if_fixed_reg_dev = {
871 .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
872 .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
873};
874
875static struct s5p_platform_mipi_csis mipi_csis_platdata = {
876 .clk_rate = 166000000UL,
877 .lanes = 2,
878 .alignment = 32,
879 .hs_settle = 12,
880 .phy_enable = s5p_csis_phy_enable,
881};
882
883#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
884#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
885#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
886
887static int m5mols_set_power(struct device *dev, int on)
888{
889 gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
890 gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
891 return 0;
892}
893
894static struct m5mols_platform_data m5mols_platdata = {
895 .gpio_reset = GPIO_CAM_MEGA_nRST,
896 .reset_polarity = 0,
897 .set_power = m5mols_set_power,
898};
899
900static struct i2c_board_info m5mols_board_info = {
901 I2C_BOARD_INFO("M5MOLS", 0x1F),
902 .platform_data = &m5mols_platdata,
903};
904
905static struct s5p_fimc_isp_info universal_camera_sensors[] = {
906 {
907 .mux_id = 0,
908 .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
909 V4L2_MBUS_VSYNC_ACTIVE_LOW,
910 .bus_type = FIMC_MIPI_CSI2,
911 .board_info = &m5mols_board_info,
912 .i2c_bus_num = 0,
913 .clk_frequency = 21600000UL,
914 .csi_data_align = 32,
915 },
916};
917
918static struct s5p_platform_fimc fimc_md_platdata = {
919 .isp_info = universal_camera_sensors,
920 .num_clients = ARRAY_SIZE(universal_camera_sensors),
921};
922
923struct platform_device s5p_device_fimc_md = {
924 .name = "s5p-fimc-md",
925 .id = -1,
926};
927
928static struct gpio universal_camera_gpios[] = {
929 { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
930 { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
931 { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
932 { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
933};
934
935static void universal_camera_init(void)
936{
937 s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
938 &s5p_device_mipi_csis0);
939 s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
940 &s5p_device_fimc_md);
941
942 if (gpio_request_array(universal_camera_gpios,
943 ARRAY_SIZE(universal_camera_gpios))) {
944 pr_err("%s: GPIO request failed\n", __func__);
945 return;
946 }
947
948 if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
949 m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
950 else
951 pr_err("Failed to configure 8M_ISP_INT GPIO\n");
952
953 /* Free GPIOs controlled directly by the sensor drivers. */
954 gpio_free(GPIO_CAM_MEGA_nRST);
955 gpio_free(GPIO_CAM_8M_ISP_INT);
956
957 if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
958 pr_err("Camera port A setup failed\n");
959}
960
34d79315 961static struct platform_device *universal_devices[] __initdata = {
a8928ce7 962 /* Samsung Platform Devices */
05132182 963 &s5p_device_mipi_csis0,
edd967b8
MS		 964 &s5p_device_fimc0,
965 &s5p_device_fimc1,
966 &s5p_device_fimc2,
967 &s5p_device_fimc3,
a8928ce7
KP		 968 &mmc0_fixed_voltage,
969 &s3c_device_hsmmc0,
970 &s3c_device_hsmmc2,
971 &s3c_device_hsmmc3,
05132182 972 &s3c_device_i2c0,
0b398b69 973 &s3c_device_i2c3,
4d838ec0 974 &s3c_device_i2c5,
d737cf29
TS		 975 &s5p_device_i2c_hdmiphy,
976 &hdmi_fixed_voltage,
977 &exynos4_device_pd[PD_TV],
978 &s5p_device_hdmi,
979 &s5p_device_sdo,
980 &s5p_device_mixer,
a8928ce7
KP		 981
982 /* Universal Devices */
b908af44 983 &i2c_gpio12,
34d79315 984 &universal_gpio_keys,
acf5eda9 985 &s5p_device_onenand,
f3f5bfe2 986 &s5p_device_fimd0,
b14f04db
KD		 987 &s5p_device_mfc,
988 &s5p_device_mfc_l,
989 &s5p_device_mfc_r,
990 &exynos4_device_pd[PD_MFC],
f3f5bfe2 991 &exynos4_device_pd[PD_LCD0],
05132182
SN		 992 &exynos4_device_pd[PD_CAM],
993 &cam_i_core_fixed_reg_dev,
994 &cam_s_if_fixed_reg_dev,
995 &s5p_device_fimc_md,
34d79315
KP		 996};
997
516607d6
KP		 998static void __init universal_map_io(void)
999{
1000 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
1001 s3c24xx_init_clocks(24000000);
1002 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
1003}
1004
d737cf29
TS		 1005void s5p_tv_setup(void)
1006{
1007 /* direct HPD to HDMI chip */
1008 gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
1009
1010 gpio_direction_input(EXYNOS4_GPX3(7));
1011 s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
1012 s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
1013
1014 /* setup dependencies between TV devices */
1015 s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
1016 s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
1017}
1018
b14f04db
KD		 1019static void __init universal_reserve(void)
1020{
1021 s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
1022}
1023
516607d6
KP		 1024static void __init universal_machine_init(void)
1025{
a8928ce7 1026 universal_sdhci_init();
d737cf29 1027 s5p_tv_setup();
a8928ce7 1028
05132182 1029 s3c_i2c0_set_platdata(&universal_i2c0_platdata);
3b7998f5
KP		 1030 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
1031
0b398b69
MS		 1032 universal_tsp_init();
1033 s3c_i2c3_set_platdata(NULL);
1034 i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
1035
4d838ec0 1036 s3c_i2c5_set_platdata(NULL);
d737cf29 1037 s5p_i2c_hdmiphy_set_platdata(NULL);
4d838ec0
MS		 1038 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
1039
f3f5bfe2
MS		 1040 s5p_fimd0_set_platdata(&universal_lcd_pdata);
1041
b908af44
MS		 1042 universal_touchkey_init();
1043 i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
1044 ARRAY_SIZE(i2c_gpio12_devs));
1045
05132182
SN		 1046 universal_camera_init();
1047
34d79315
KP		 1048 /* Last */
1049 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
05132182 1050
b14f04db 1051 s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
f3f5bfe2 1052 s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
05132182
SN		 1053
1054 s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1055 s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1056 s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1057 s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
1058 s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
516607d6
KP		 1059}
1060
1061MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
1062 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
516607d6 1063 .boot_params = S5P_PA_SDRAM + 0x100,
d11135ca 1064 .init_irq = exynos4_init_irq,
516607d6
KP		 1065 .map_io = universal_map_io,
1066 .init_machine = universal_machine_init,
d11135ca 1067 .timer = &exynos4_timer,
b14f04db 1068 .reserve = &universal_reserve,
516607d6 1069MACHINE_END
Linux kernel - Deliverables
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