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7d30e8b3 | 1 | /* linux/arch/arm/mach-exynos4/platsmp.c |
2b12b5c4 | 2 | * |
7d30e8b3 KK |
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | |
2b12b5c4 CY |
5 | * |
6 | * Cloned from linux/arch/arm/mach-vexpress/platsmp.c | |
7 | * | |
8 | * Copyright (C) 2002 ARM Ltd. | |
9 | * All Rights Reserved | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/jiffies.h> | |
21 | #include <linux/smp.h> | |
22 | #include <linux/io.h> | |
23 | ||
24 | #include <asm/cacheflush.h> | |
0f7b332f | 25 | #include <asm/hardware/gic.h> |
2b12b5c4 CY |
26 | #include <asm/smp_scu.h> |
27 | #include <asm/unified.h> | |
28 | ||
29 | #include <mach/hardware.h> | |
30 | #include <mach/regs-clock.h> | |
31 | ||
7d30e8b3 | 32 | extern void exynos4_secondary_startup(void); |
2b12b5c4 CY |
33 | |
34 | /* | |
35 | * control for which core is the next to come out of the secondary | |
36 | * boot "holding pen" | |
37 | */ | |
38 | ||
39 | volatile int __cpuinitdata pen_release = -1; | |
40 | ||
3705ff6d RK |
41 | /* |
42 | * Write pen_release in a way that is guaranteed to be visible to all | |
43 | * observers, irrespective of whether they're taking part in coherency | |
44 | * or not. This is necessary for the hotplug code to work reliably. | |
45 | */ | |
46 | static void write_pen_release(int val) | |
47 | { | |
48 | pen_release = val; | |
49 | smp_wmb(); | |
50 | __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); | |
51 | outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); | |
52 | } | |
53 | ||
2b12b5c4 CY |
54 | static void __iomem *scu_base_addr(void) |
55 | { | |
56 | return (void __iomem *)(S5P_VA_SCU); | |
57 | } | |
58 | ||
59 | static DEFINE_SPINLOCK(boot_lock); | |
60 | ||
aab74d3e CY |
61 | static void __cpuinit exynos4_gic_secondary_init(void) |
62 | { | |
63 | void __iomem *dist_base = S5P_VA_GIC_DIST + | |
64 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | |
65 | void __iomem *cpu_base = S5P_VA_GIC_CPU + | |
66 | (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); | |
67 | int i; | |
68 | ||
69 | /* | |
70 | * Deal with the banked PPI and SGI interrupts - disable all | |
71 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
72 | */ | |
73 | __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); | |
74 | __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | |
75 | ||
76 | /* | |
77 | * Set priority on PPI and SGI interrupts | |
78 | */ | |
79 | for (i = 0; i < 32; i += 4) | |
80 | __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); | |
81 | ||
82 | __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK); | |
83 | __raw_writel(1, cpu_base + GIC_CPU_CTRL); | |
84 | } | |
85 | ||
2b12b5c4 CY |
86 | void __cpuinit platform_secondary_init(unsigned int cpu) |
87 | { | |
2b12b5c4 CY |
88 | /* |
89 | * if any interrupts are already enabled for the primary | |
90 | * core (e.g. timer irq), then they will not have been enabled | |
91 | * for us: do so | |
92 | */ | |
aab74d3e | 93 | exynos4_gic_secondary_init(); |
2b12b5c4 CY |
94 | |
95 | /* | |
96 | * let the primary processor know we're out of the | |
97 | * pen, then head off into the C entry point | |
98 | */ | |
3705ff6d | 99 | write_pen_release(-1); |
2b12b5c4 CY |
100 | |
101 | /* | |
102 | * Synchronise with the boot thread. | |
103 | */ | |
104 | spin_lock(&boot_lock); | |
105 | spin_unlock(&boot_lock); | |
106 | } | |
107 | ||
108 | int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |
109 | { | |
110 | unsigned long timeout; | |
111 | ||
112 | /* | |
113 | * Set synchronisation state between this boot processor | |
114 | * and the secondary one | |
115 | */ | |
116 | spin_lock(&boot_lock); | |
117 | ||
118 | /* | |
119 | * The secondary processor is waiting to be released from | |
120 | * the holding pen - release it, then wait for it to flag | |
121 | * that it has been released by resetting pen_release. | |
122 | * | |
123 | * Note that "pen_release" is the hardware CPU ID, whereas | |
124 | * "cpu" is Linux's internal ID. | |
125 | */ | |
3705ff6d | 126 | write_pen_release(cpu); |
2b12b5c4 CY |
127 | |
128 | /* | |
129 | * Send the secondary CPU a soft interrupt, thereby causing | |
130 | * the boot monitor to read the system wide flags register, | |
131 | * and branch to the address found there. | |
132 | */ | |
0f7b332f | 133 | gic_raise_softirq(cpumask_of(cpu), 1); |
2b12b5c4 CY |
134 | |
135 | timeout = jiffies + (1 * HZ); | |
136 | while (time_before(jiffies, timeout)) { | |
137 | smp_rmb(); | |
138 | if (pen_release == -1) | |
139 | break; | |
140 | ||
141 | udelay(10); | |
142 | } | |
143 | ||
144 | /* | |
145 | * now the secondary core is starting up let it run its | |
146 | * calibrations, then wait for it to finish | |
147 | */ | |
148 | spin_unlock(&boot_lock); | |
149 | ||
150 | return pen_release != -1 ? -ENOSYS : 0; | |
151 | } | |
152 | ||
153 | /* | |
154 | * Initialise the CPU possible map early - this describes the CPUs | |
155 | * which may be present or become present in the system. | |
156 | */ | |
157 | ||
158 | void __init smp_init_cpus(void) | |
159 | { | |
160 | void __iomem *scu_base = scu_base_addr(); | |
161 | unsigned int i, ncores; | |
162 | ||
163 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | |
164 | ||
165 | /* sanity check */ | |
2b12b5c4 CY |
166 | if (ncores > NR_CPUS) { |
167 | printk(KERN_WARNING | |
7d30e8b3 | 168 | "EXYNOS4: no. of cores (%d) greater than configured " |
2b12b5c4 CY |
169 | "maximum of %d - clipping\n", |
170 | ncores, NR_CPUS); | |
171 | ncores = NR_CPUS; | |
172 | } | |
173 | ||
174 | for (i = 0; i < ncores; i++) | |
175 | set_cpu_possible(i, true); | |
0f7b332f RK |
176 | |
177 | set_smp_cross_call(gic_raise_softirq); | |
2b12b5c4 CY |
178 | } |
179 | ||
05c74a6c | 180 | void __init platform_smp_prepare_cpus(unsigned int max_cpus) |
2b12b5c4 | 181 | { |
2b12b5c4 CY |
182 | int i; |
183 | ||
2b12b5c4 CY |
184 | /* |
185 | * Initialise the present map, which describes the set of CPUs | |
186 | * actually populated at the present time. | |
187 | */ | |
188 | for (i = 0; i < max_cpus; i++) | |
189 | set_cpu_present(i, true); | |
190 | ||
05c74a6c RK |
191 | scu_enable(scu_base_addr()); |
192 | ||
2b12b5c4 | 193 | /* |
05c74a6c RK |
194 | * Write the address of secondary startup into the |
195 | * system-wide flags register. The boot monitor waits | |
196 | * until it receives a soft interrupt, and then the | |
197 | * secondary CPU branches to this address. | |
2b12b5c4 | 198 | */ |
7d30e8b3 | 199 | __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); |
2b12b5c4 | 200 | } |