[deliverable/linux.git] / arch / arm / mach-footbridge / dc21285-timer.c

/*
 *  linux/arch/arm/mach-footbridge/dc21285-timer.c
 *
 *  Copyright (C) 1998 Russell King.
 *  Copyright (C) 1998 Phil Blundell
 */
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <asm/irq.h>

#include <asm/hardware/dec21285.h>
#include <asm/mach/time.h>
#include <asm/system_info.h>

#include "common.h"

static cycle_t cksrc_dc21285_read(struct clocksource *cs)
{
	return cs->mask - *CSR_TIMER2_VALUE;
}

static int cksrc_dc21285_enable(struct clocksource *cs)
{
	*CSR_TIMER2_LOAD = cs->mask;
	*CSR_TIMER2_CLR = 0;
	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
	return 0;
}

static void cksrc_dc21285_disable(struct clocksource *cs)
{
	*CSR_TIMER2_CNTL = 0;
}

static struct clocksource cksrc_dc21285 = {
	.name		= "dc21285_timer2",
	.rating		= 200,
	.read		= cksrc_dc21285_read,
	.enable		= cksrc_dc21285_enable,
	.disable	= cksrc_dc21285_disable,
	.mask		= CLOCKSOURCE_MASK(24),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
	struct clock_event_device *c)
{
	switch (mode) {
	case CLOCK_EVT_MODE_RESUME:
	case CLOCK_EVT_MODE_PERIODIC:
		*CSR_TIMER1_CLR = 0;
		*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
		*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
				   TIMER_CNTL_DIV16;
		break;

	default:
		*CSR_TIMER1_CNTL = 0;
		break;
	}
}

static struct clock_event_device ckevt_dc21285 = {
	.name		= "dc21285_timer1",
	.features	= CLOCK_EVT_FEAT_PERIODIC,
	.rating		= 200,
	.irq		= IRQ_TIMER1,
	.set_mode	= ckevt_dc21285_set_mode,
};

static irqreturn_t timer1_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	*CSR_TIMER1_CLR = 0;

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

static struct irqaction footbridge_timer_irq = {
	.name		= "dc21285_timer1",
	.handler	= timer1_interrupt,
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &ckevt_dc21285,
};

/*
 * Set up timer interrupt.
 */
void __init footbridge_timer_init(void)
{
	struct clock_event_device *ce = &ckevt_dc21285;

	clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16);

	setup_irq(ce->irq, &footbridge_timer_irq);

	ce->cpumask = cpumask_of(smp_processor_id());
	clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-footbridge/dc21285-timer.c
	3	*
	4	* Copyright (C) 1998 Russell King.
	5	* Copyright (C) 1998 Phil Blundell
	6	*/
4e8d7637 RK	7	#include <linux/clockchips.h>
4e8d7637 RK	8	#include <linux/clocksource.h>
1da177e4 LT	9	#include <linux/init.h>
1da177e4 LT	10	#include <linux/interrupt.h>
55e86989	11	#include <linux/irq.h>
1da177e4 LT	12
	13	#include <asm/irq.h>
	14
	15	#include <asm/hardware/dec21285.h>
	16	#include <asm/mach/time.h>
9f97da78	17	#include <asm/system_info.h>
1da177e4 LT	18
	19	#include "common.h"
	20
4e8d7637 RK	21	static cycle_t cksrc_dc21285_read(struct clocksource *cs)
	22	{
	23	return cs->mask - *CSR_TIMER2_VALUE;
	24	}
1da177e4	25
4e8d7637	26	static int cksrc_dc21285_enable(struct clocksource *cs)
1da177e4	27	{
4e8d7637 RK	28	*CSR_TIMER2_LOAD = cs->mask;
	29	*CSR_TIMER2_CLR = 0;
	30	*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_DIV16;
	31	return 0;
	32	}
1da177e4	33
f2e0bf21	34	static void cksrc_dc21285_disable(struct clocksource *cs)
4e8d7637 RK	35	{
4e8d7637 RK	36	*CSR_TIMER2_CNTL = 0;
1da177e4 LT	37	}
1da177e4 LT	38
4e8d7637 RK	39	static struct clocksource cksrc_dc21285 = {
	40	.name = "dc21285_timer2",
	41	.rating = 200,
	42	.read = cksrc_dc21285_read,
	43	.enable = cksrc_dc21285_enable,
	44	.disable = cksrc_dc21285_disable,
	45	.mask = CLOCKSOURCE_MASK(24),
	46	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	47	};
	48
	49	static void ckevt_dc21285_set_mode(enum clock_event_mode mode,
	50	struct clock_event_device *c)
1da177e4	51	{
4e8d7637 RK	52	switch (mode) {
	53	case CLOCK_EVT_MODE_RESUME:
	54	case CLOCK_EVT_MODE_PERIODIC:
	55	*CSR_TIMER1_CLR = 0;
	56	CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 HZ) / (16 * HZ);
	57	*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE \| TIMER_CNTL_AUTORELOAD \|
	58	TIMER_CNTL_DIV16;
	59	break;
	60
	61	default:
	62	*CSR_TIMER1_CNTL = 0;
	63	break;
	64	}
	65	}
	66
	67	static struct clock_event_device ckevt_dc21285 = {
	68	.name = "dc21285_timer1",
	69	.features = CLOCK_EVT_FEAT_PERIODIC,
	70	.rating = 200,
	71	.irq = IRQ_TIMER1,
	72	.set_mode = ckevt_dc21285_set_mode,
	73	};
	74
	75	static irqreturn_t timer1_interrupt(int irq, void *dev_id)
	76	{
	77	struct clock_event_device *ce = dev_id;
	78
1da177e4 LT	79	*CSR_TIMER1_CLR = 0;
1da177e4 LT	80
4e8d7637	81	ce->event_handler(ce);
1da177e4	82
1da177e4 LT	83	return IRQ_HANDLED;
	84	}
	85
	86	static struct irqaction footbridge_timer_irq = {
4e8d7637	87	.name = "dc21285_timer1",
1da177e4	88	.handler = timer1_interrupt,
b30fabad	89	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
4e8d7637	90	.dev_id = &ckevt_dc21285,
1da177e4 LT	91	};
	92
	93	/*
	94	* Set up timer interrupt.
	95	*/
6bb27d73	96	void __init footbridge_timer_init(void)
1da177e4	97	{
4e8d7637 RK	98	struct clock_event_device *ce = &ckevt_dc21285;
	99
	100	clocksource_register_hz(&cksrc_dc21285, (mem_fclk_21285 + 8) / 16);
	101
	102	setup_irq(ce->irq, &footbridge_timer_irq);
1da177e4	103
7d7975a0	104	ce->cpumask = cpumask_of(smp_processor_id());
838a2ae8	105	clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
1da177e4	106	}